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CN109962036B - Semiconductor structure and method of forming the same - Google Patents

Semiconductor structure and method of forming the same Download PDF

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CN109962036B
CN109962036B CN201711338364.0A CN201711338364A CN109962036B CN 109962036 B CN109962036 B CN 109962036B CN 201711338364 A CN201711338364 A CN 201711338364A CN 109962036 B CN109962036 B CN 109962036B
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layer
forming
epitaxial layer
side wall
fin
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CN109962036A (en
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周飞
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Semiconductor Manufacturing International Shanghai Corp
SMIC Advanced Technology R&D Shanghai Corp
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Semiconductor Manufacturing International Shanghai Corp
SMIC Advanced Technology R&D Shanghai Corp
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    • H—ELECTRICITY
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0151—Manufacturing their isolation regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3738—Semiconductor materials
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    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/85—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs
    • H—ELECTRICITY
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0158—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including FinFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/834—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET] comprising FinFETs

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Abstract

一种半导体结构及其形成方法，其中，所述形成方法包括：提供衬底，所述衬底上具有鳍部，所述鳍部包括散热区和位于所述散热区上的器件区；形成外延层和隔离结构，所述外延层位于所述散热区鳍部侧壁表面，且暴露出所述器件区鳍部，所述隔离结构覆盖所述外延层侧壁，所述外延层的导热系数大于所述隔离结构的导热系数。由于所述外延层的导热系数大于所述隔离结构的导热系数，所述器件区鳍部产生的热量能够通过所述外延层释放。因此，所述外延层能够增加散热区的散热性能，从而降低所形成半导体结构的自加热效应。

Figure 201711338364

A semiconductor structure and a method for forming the same, wherein the forming method includes: providing a substrate with fins on the substrate, the fins including a heat dissipation area and a device area located on the heat dissipation area; forming an epitaxy layer and isolation structure, the epitaxial layer is located on the surface of the sidewall of the heat dissipation area fin and exposes the device area fin, the isolation structure covers the sidewall of the epitaxial layer, and the thermal conductivity of the epitaxial layer is greater than The thermal conductivity of the isolation structure. Since the thermal conductivity of the epitaxial layer is greater than that of the isolation structure, the heat generated by the device region fins can be released through the epitaxial layer. Therefore, the epitaxial layer can increase the heat dissipation performance of the heat dissipation region, thereby reducing the self-heating effect of the formed semiconductor structure.

Figure 201711338364

Description

Semiconductor structure and forming method thereof
Technical Field
The present invention relates to the field of semiconductor manufacturing technologies, and in particular, to a semiconductor structure and a method for forming the same.
Background
With the rapid development of semiconductor manufacturing technology, semiconductor devices are being developed toward higher element density and higher integration. As the element density and integration of semiconductor devices increase, the size of transistors also becomes smaller, and the reduction in the size of transistors makes short-channel effects more and more significant.
To reduce short channel effects, finfets operate. The grid electrode of the fin field effect transistor is in a fork-shaped 3D structure similar to a fish fin. The grid electrode of the fin field effect transistor can be switched on and off in the multi-side control circuit of the fin part, so that the short channel effect of the transistor can be well inhibited. As the size of the transistor decreases, the fin width of the finfet decreases, resulting in poor fin heat dissipation.
In summary, the conventional semiconductor structure has a problem of poor heat dissipation effect.
Disclosure of Invention
The invention provides a semiconductor structure and a forming method thereof, which can improve the heat dissipation performance of the formed semiconductor structure.
In order to solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, wherein the substrate is provided with a fin part, and the fin part comprises a heat dissipation area and a device area positioned on the heat dissipation area; and forming an epitaxial layer and an isolation structure, wherein the epitaxial layer is positioned on the surface of the side wall of the fin part in the heat dissipation area and exposes the fin part in the device area, the isolation structure covers the side wall of the epitaxial layer, and the thermal conductivity coefficient of the material of the epitaxial layer is greater than that of the material of the isolation structure.
Optionally, the epitaxial layer is made of monocrystalline silicon, monocrystalline germanium, monocrystalline silicon germanium, or monocrystalline III-V element.
Optionally, the process of forming the epitaxial layer includes an epitaxial growth process.
Optionally, the thickness of the epitaxial layer is 1 nm-5 nm; the size of the epitaxial layer along the direction vertical to the surface of the substrate is 2 nm-30 nm.
Optionally, the step of forming the epitaxial layer includes: forming a side wall covering the side wall of the fin part device area, wherein the side wall is exposed out of the side wall of the fin part of the heat dissipation area; forming an epitaxial layer on the surface of the side wall of the fin part exposed by the side wall by taking the side wall as a mask; and after the epitaxial layer is formed, removing the side wall.
Optionally, the sidewall is made of silicon nitride, silicon oxide, or silicon oxynitride.
Optionally, the step of forming the side wall includes: forming a sacrificial layer on the substrate, wherein the sacrificial layer covers the side wall of the fin part in the heat dissipation area, the fin part in the device area is exposed out of the sacrificial layer, and the material of the sacrificial layer is different from that of the side wall; forming a side wall on the side wall of the fin part exposed out of the sacrificial layer; after the side wall is formed, removing the sacrificial layer; after the epitaxial layer is formed, the isolation structure is formed.
Optionally, before the isolation structure is formed, removing the side wall; or, after the isolation structure is formed, removing the side wall.
Optionally, the step of forming a sidewall on the sidewall of the fin portion exposed by the sacrificial layer includes: forming a side wall layer covering the sacrificial layer, the exposed side wall of the fin part of the sacrificial layer and the top of the fin part; and removing the side wall layer covering the sacrificial layer to form the side wall.
Optionally, the process of removing the sidewall layer covering the sacrificial layer includes: and (3) an anisotropic dry etching process.
Optionally, the sacrificial layer is made of spin-on carbon layer, silicon oxide, silicon nitride, or organic dielectric layer.
Optionally, when the sacrificial layer is made of a spin-on carbon layer, silicon oxide, or an organic dielectric layer, the process for forming the sacrificial layer includes a spin-on process; when the material of the sacrificial layer is silicon oxide or silicon nitride, the process for forming the sacrificial layer comprises a chemical vapor deposition process, a physical vapor deposition process or an atomic layer deposition process.
Optionally, the step of forming the epitaxial layer and the isolation structure includes: forming an initial epitaxial layer on the surfaces of the side walls of the fin parts of the device region and the heat dissipation region; after an initial epitaxial layer is formed, forming an isolation structure on the substrate, wherein the isolation structure covers the side wall of the initial epitaxial layer of the heat dissipation area; and removing the initial epitaxial layer of the device region by taking the isolation structure as a mask to form an epitaxial layer.
Optionally, the epitaxial layer and the fin portion are made of different materials.
Optionally, the step of removing the initial epitaxial layer of the device region includes: after the isolation structure is formed, carrying out oxidation treatment on the initial epitaxial layer of the device region to form an oxide layer; and removing the oxide layer.
Optionally, the surface of the isolation structure is higher than or flush with the top surface of the epitaxial layer.
Optionally, after the epitaxial layer and the isolation structure are formed, the method further includes: and forming a gate structure crossing the fin part of the device region, wherein the gate structure covers part of the side wall and the top surface of the fin part of the device region.
Optionally, the fin is made of monocrystalline silicon, monocrystalline germanium, monocrystalline silicon germanium, or monocrystalline III-V element.
Optionally, before the epitaxial layer is formed, a mask layer is arranged on the top of the fin portion, and the mask layer is made of an amorphous material.
Correspondingly, the technical scheme of the invention also provides a semiconductor structure, which comprises: a substrate; a fin portion on the substrate, the fin portion including a heat dissipation region and a device region on the heat dissipation region; the epitaxial layer is positioned on the surface of the side wall of the fin part of the heat dissipation area; the isolation structure is positioned on the substrate, the isolation structure covers the side wall of the epitaxial layer, and the heat conductivity coefficient of the epitaxial layer is greater than that of the isolation structure.
Compared with the prior art, the technical scheme of the invention has the following advantages:
the forming method of the semiconductor structure provided by the technical scheme of the invention comprises the step of forming the epitaxial layer, wherein the epitaxial layer is positioned on the surface of the side wall of the fin part in the heat dissipation area. Because the heat conductivity coefficient of the epitaxial layer is larger than that of the isolation structure, heat generated by the fin part in the device area can be released through the epitaxial layer. In addition, the contact area between the fin part of the heat dissipation area and the substrate and the contact area between the epitaxial layer and the substrate are larger, so that a channel for releasing heat generated by the fin part of the device area to the substrate can be increased. Therefore, the epitaxial layer can increase the heat dissipation performance of the heat dissipation area, and the self-heating effect of the formed semiconductor structure is reduced.
Furthermore, the fin portion is made of a single crystal of silicon germanium or III-V element materials, stress exists in the single crystal of the silicon germanium or the III-V element materials, the migration rate of carriers in the fin portion of the device area can be increased, and therefore performance of the formed semiconductor structure is improved.
Further, the epitaxial layer is made of silicon. Silicon has a high thermal conductivity coefficient, and can increase the heat dissipation performance of the heat dissipation area, thereby reducing the self-heating effect of the formed semiconductor structure.
Further, the surface of the isolation structure is higher than or flush with the top surface of the epitaxial layer, so that the epitaxial layer does not increase the width of the semiconductor material below the gate structure. The width of the semiconductor material below the grid structure is small, and in the working process of the formed semiconductor structure, the fin parts of the device region form channels, so that the control effect of the grid structure on current carriers can be increased, and further the leakage current is reduced.
In the semiconductor structure provided by the technical scheme of the invention, the surface of the side wall of the fin part of the heat dissipation area is provided with the epitaxial layer. Because the heat conductivity coefficient of the epitaxial layer is larger than that of the isolation structure, the heat dissipation performance of the heat dissipation area can be improved by the epitaxial layer, and therefore the self-heating effect of the formed semiconductor structure is reduced.
Drawings
FIG. 1 is a schematic diagram of a semiconductor structure;
FIGS. 2-11 are schematic structural diagrams illustrating steps of a method of forming a semiconductor structure according to an embodiment of the present invention;
fig. 12 to 15 are schematic structural views of steps of another embodiment of a method for forming a semiconductor structure according to the present invention.
Detailed Description
The semiconductor structure formed by the prior art has a plurality of problems, such as: the resulting semiconductor structure has poor heat dissipation.
Now, with reference to a semiconductor structure, the reason for the poor heat dissipation performance of the semiconductor structure is analyzed:
fig. 1 is a schematic structural diagram of a semiconductor structure.
Referring to fig. 1, the semiconductor structure includes: a substrate 100 having a fin 130 thereon; an isolation structure 110 on the substrate 100, wherein the isolation structure 110 covers a portion of the sidewall of the fin 130; and the gate structure 120 crosses over the fin 130, and the gate structure 120 covers part of the sidewall and the top surface of the fin 130.
The material of the fin 130 is a single crystal of silicon germanium or a III-V element material, and the single crystal of silicon germanium or a III-V element material can increase the mobility rate of carriers in the fin 130; in addition, in order to make the fin 130 above the isolation structure 110 easy to invert after the channel is opened, the control effect of the gate structure 120 on carriers in the channel is increased, and thus the width of the fin 130 is smaller.
However, the material of the isolation structure 110 is silicon oxide, which has good electrical insulation. However, since the thermal conductivity of silicon oxide is small, the heat dissipation performance of the isolation structure 110 is poor, and heat is mainly released through the fin 130 and the substrate 100. The width of the fin portion 130 is small, the contact area between the fin portion 130 and the substrate 100 is small, and heat generated in the fin portion 130 is not easily released through the fin portion 130 and the substrate 100; in addition, the single crystal of silicon germanium or III-V material has poor heat dissipation performance, so that the heat generated in the fin 130 is not easily released, and the self-heating effect of the semiconductor structure is severe.
In order to solve the technical problem, the invention provides a method for forming a semiconductor structure, which comprises the following steps: and forming an epitaxial layer and an isolation structure on the substrate, wherein the thermal conductivity of the epitaxial layer is greater than that of the isolation structure. The heat generated by the device region fin can be released through the epitaxial layer. Therefore, the epitaxial layer can increase the heat dissipation performance of the heat dissipation area, and the self-heating effect of the formed semiconductor structure is reduced.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 2 to 11 are schematic structural diagrams of steps of a method for forming a semiconductor structure according to an embodiment of the present invention.
A substrate is provided, and the substrate is provided with a fin portion.
In this embodiment, the steps of forming the substrate and the fin portion are as shown in fig. 2 to 3.
Referring to fig. 2, a substrate 200 is provided, and a fin layer 210 is formed on the substrate 200.
The fin layer 210 is used for subsequently formed fins.
In this embodiment, the substrate 200 is made of silicon. The silicon has good heat dissipation performance and can effectively reduce the self-heating effect of the formed semiconductor structure. In other embodiments, the substrate material may also be a single crystal of germanium, silicon germanium, or a III-V element including InAs, GaAs, InGaAs, InAs, InAlAs, or InP.
In this embodiment, the semiconductor structure formed is a PMOS transistor. In other embodiments, the semiconductor structure formed may be a diode or a triode.
In this embodiment, the fin layer 210 is made of silicon germanium or a single crystal of a III-V element material. Due to the stress in the single crystal of silicon germanium or a III-V material, the subsequently formed transistor channel has stress, which can increase the mobility rate of channel carriers in the formed fin.
In other embodiments, the material of the fin layer may also be silicon. If the formed semiconductor structure is an NMOS transistor, the material of the fin portion layer is monocrystalline silicon, silicon carbide or III-V group element materials, and the monocrystalline III-V group element materials comprise InAs, GaAs, InGaAs, InAs, InAlAs or InP.
Referring to fig. 2, the fin layer 210 (shown in fig. 1) is patterned to form a fin 211, where the fin 211 includes a heat dissipation region II and a device region I located on the heat dissipation region II.
The heat dissipation area II is used for releasing heat generated by the device area I, and the device area I is used for forming a channel of a transistor.
In this embodiment, the fin 211 is used to form a channel of a MOS transistor. In other embodiments, the fin is used to form an electrode of a diode or a transistor.
In this embodiment, the step of patterning the fin portion layer 210 includes: forming a patterned mask layer 203 on the fin portion layer 210; and etching the fin portion layer 210 by using the mask layer 203 as a mask to form the fin portion 211.
The process for etching the fin portion layer 210 includes a dry etching process. The dry etching has a good line width control, so that the fin 211 formed has good verticality with the surface of the substrate 200. In other embodiments, the process of etching the initial substrate comprises a wet etch process.
The mask layer 203 is made of silicon nitride, silicon oxide or silicon oxynitride.
The mask layer 203 is used as a mask for etching the fin portion layer 210. In this embodiment, the mask layer 203 is further used for protecting the top of the fin 211 and preventing an epitaxial layer material from being formed on the top surface of the fin 211 in a subsequent epitaxial layer forming process.
If the width of the fin portion 211 is too large, the formed semiconductor structure is not beneficial to enabling the fin portion 211 below the gate structure to be inverted in the working process, so that the control of the fin portion 211 on current carriers in a channel is not beneficial to increasing, and the leakage current is easy to increase; if the width of the fin portion 211 is too small, the difficulty of the patterning process is easily increased, and specifically, the width of the fin portion 211 is 4nm to 15 nm.
Referring to fig. 4, a buffer layer 204 is formed on the sidewall surface of the fin 211.
The buffer layer 204 is used for protecting the fin portion 211 in the subsequent etching process of the sacrificial layer 220.
In this embodiment, the fin 211 is made of sige, and the buffer layer 204 is made of sige oxide. In other embodiments, the fin is made of silicon, and the buffer layer is made of silicon oxide.
In this embodiment, the process of forming the buffer layer 204 includes a thermal oxidation process or an in-situ water vapor generation process. In other embodiments, the process of forming the buffer layer includes a chemical deposition process or an atomic layer deposition process.
And forming an epitaxial layer and an isolation structure on the substrate, wherein the epitaxial layer is positioned on the surface of the side wall of the fin part 211 in the heat dissipation area II and exposes the fin part 211 in the device area I, the isolation structure covers the side wall of the epitaxial layer, and the thermal conductivity of the epitaxial layer is greater than that of the isolation structure.
In this embodiment, the steps of forming the epitaxial layer and the isolation structure are as shown in fig. 5 to 11.
And subsequently forming a side wall covering the side wall of the device region I of the fin 211, wherein the side wall 230 exposes the side wall of the fin 211 of the heat dissipation region II. In this embodiment, the step of forming the sidewall is shown in fig. 5 to 7.
Referring to fig. 5, a sacrificial layer 220 is formed on the substrate, the sacrificial layer 220 covers sidewalls of the heat dissipation region II fin 211, and the sacrificial layer 220 exposes the device region I fin 211.
In this embodiment, the surface of the sacrificial layer 220 is lower than the top surface of the heat dissipation region II. In other embodiments, the sacrificial layer surface may also be flush with the heat dissipation region top surface.
The sacrificial layer 220 is used to cover the sidewalls of the heat dissipation region II fin 211, so as to avoid forming sidewalls 230 on the sidewalls of the heat dissipation region II fin 211.
In this embodiment, a buffer layer 204 is disposed between the heat dissipation region II fin 211 and the sacrificial layer 220.
The sacrificial layer 220 is made of spin-on carbon layer, silicon oxide or organic dielectric layer. In the subsequent process of removing the sacrificial layer 220, the sacrificial layer 220 has a larger etching selection ratio with respect to the fin portion 211 and a larger etching selection ratio with respect to a subsequently formed side wall, so that the loss of the fin portion 211 and the side wall can be reduced. In other embodiments, the material of the sacrificial layer may also be silicon nitride.
The step of forming the sacrificial layer 220 includes: forming an initial sacrificial layer on the substrate 200, the initial sacrificial layer surface being higher than or flush with the fin 211 top surface; and etching the initial sacrificial layer to form a sacrificial layer 220, wherein the surface of the sacrificial layer 220 is lower than or flush with the top surface of the fin portion 211.
In this embodiment, the process of forming the initial sacrificial layer includes a spin coating process. In other embodiments, when the material of the initial sacrificial layer is silicon oxide or silicon nitride, the process of forming the initial sacrificial layer is a chemical vapor deposition process, a physical vapor deposition process or an atomic layer deposition process.
If the thickness of the sacrificial layer 220 is too large, the height of the fin portion 211 exposed by the sacrificial layer 220 is small, and the width of a channel of a subsequently formed transistor is small, the resistance of the channel is easily increased; if the thickness of the sacrificial layer 220 is too small, the dimension of the epitaxial layer 240 formed subsequently in the direction perpendicular to the surface of the substrate 200 is too small, which is not favorable for increasing the heat dissipation performance of the heat dissipation region II. Therefore, in the present embodiment, the thickness of the sacrificial layer 220 is 2nm to 8 nm.
In this embodiment, the surface of the sacrificial layer 220 is lower than the top surface of the heat dissipation region II. In other embodiments, the sacrificial layer surface may be higher than or flush with the heat dissipation region top surface.
The surface of the sacrificial layer 220 is lower than or even with the top surface of the heat dissipation region II, and the top of the epitaxial layer 240 formed subsequently is lower than or even with the top surface of the heat dissipation region II. The epitaxial layer 240 does not increase the width of the semiconductor material below the subsequently formed gate. The width of the semiconductor material below the gate structure is small, and in the working process of the formed semiconductor structure, the I fin parts 211 of the device region form channels, so that the control effect of the gate structure on current carriers can be increased, and further, the leakage current is reduced.
Referring to fig. 6, a sidewall spacer 230 is formed on the sidewall of the fin 211 exposed by the sacrificial layer 220, and the material of the sidewall spacer 230 is different from that of the sacrificial layer 220.
The sacrificial layer 220 exposes the device region I fin 211 and the sidewalls of a portion of the heat dissipation region II fin 211, and the sidewalls 230 cover the sidewalls of the device region I fin 211.
The side walls 230 are used for protecting the device region I-fin portion 211 in the subsequent epitaxial layer 240 forming process, and preventing an epitaxial layer 240 material from being formed on the surface of the device region I-fin portion 211, so that the control effect of the gate structure on carriers in a channel can be increased, and leakage current can be reduced.
The sidewall spacers 230 are made of silicon nitride. In other embodiments, the material of the sidewall is silicon oxide or silicon oxynitride.
The step of forming the sidewall spacers 230 on the sidewalls of the fin 211 exposed by the sacrificial layer 220 includes: forming a side wall layer covering the sacrificial layer 220 and the sidewalls and the top of the fin portion 211 exposed by the sacrificial layer 220; the sidewall layer covering the sacrificial layer 220 is removed.
In this embodiment, the sidewall layer is made of silicon nitride, SiOCN, or SiBCN.
The step of forming the sidewall layer comprises a chemical vapor deposition process, a physical vapor deposition process or an atomic layer deposition process.
The process of removing the sidewall layer covering the sacrificial layer 220 includes an anisotropic dry etching process. The etching rate of the anisotropic dry etching process in the transverse direction is less than that in the longitudinal direction, so that the side wall layer of the side wall of the fin portion 211 can be reserved while the sacrificial layer 220 and the sacrificial layer 220 on the top of the fin portion 211 are removed.
If the thickness of the side wall layer is too large, the difficulty of etching the side wall layer is easily increased; if the thickness of the sidewall layer is too small, the sidewall spacers 230 protect the I-fin 211 in the device region during the subsequent formation of the epitaxial layer 240. Specifically, the thickness of the side wall layer is 1 nm-5 nm.
Under the condition that the height of the fin portion 211 is constant, if the dimension of the sidewall 230 in the direction perpendicular to the surface of the substrate 200 is too large, the dimension of the subsequently formed epitaxial layer 240 in the direction perpendicular to the surface of the substrate 200 is too small, which is not favorable for increasing the heat dissipation performance of the formed semiconductor structure; if the dimension of the sidewall spacers 230 in the direction perpendicular to the surface of the substrate 200 is too small, the width of the channel of the formed transistor is small, and the channel resistance is large, which may easily affect the performance of the formed transistor. Specifically, in this embodiment, the size of the sidewall 230 along the direction perpendicular to the surface of the substrate 200 is 30nm to 80 nm.
Referring to fig. 7, after the sidewalls 230 are formed, the sacrificial layer 220 is removed (as shown in fig. 6).
In this embodiment, after removing the sacrificial layer 220, removing the buffer layer 204 of the heat dissipation region II is further included.
And removing the sacrificial layer 220 and the buffer layer 204 to expose the heat dissipation region II of the fin 211, so that an epitaxial layer can be formed on the surface of the sidewall of the heat dissipation region II of the fin 211 to increase the heat dissipation of the formed semiconductor structure.
In this embodiment, the process of removing the sacrificial layer 220 includes an isotropic dry etching process. In other embodiments, the process of removing the sacrificial layer comprises a wet etch process.
Specifically, in this embodiment, the etching gas for removing the sacrificial layer 220 includes CH3F、N2And O2。
In this embodiment, the process parameters for removing the sacrificial layer 220 include: CH (CH)3The flow rate of F is 8sccm to 50 sccm; n is a radical of2The flow rate is 180sccm to 220 sccm; o is2The flow rate of the liquid is 9sccm to 11 sccm; the radio frequency power is 90W-110W, the bias voltage is 30V-100V, the etching time is 4 s-50 s, and the gas pressure is 10 mtorr-200 mtorr.
Referring to fig. 8, with the sidewall spacers 230 as masks, an epitaxial layer 240 is formed on the sidewall surfaces of the fin portions 211 exposed by the sidewall spacers 230, and a thermal conductivity of the epitaxial layer 240 is greater than a thermal conductivity of a subsequently formed isolation structure.
Since the thermal conductivity of the epitaxial layer 240 is greater than that of the isolation structure, the heat generated by the I-fin portion of the device region can be released through the epitaxial layer 240. In addition, the contact area between the heat dissipation region II fin portion 211 and the epitaxial layer 240 and the substrate 200 is large, so that a channel for releasing heat generated by the device region I fin portion 211 to the substrate 200 can be increased. Therefore, the epitaxial layer 240 can increase the heat dissipation performance of the heat dissipation region II, thereby reducing the self-heating effect of the formed semiconductor structure.
The side walls 230 are used for protecting the device region I-fin portion 211 and preventing the epitaxial layer 240 from being formed on the surface of the side wall of the device region I-fin portion 211 in the process of forming the epitaxial layer 240, so that the influence of the epitaxial layer 240 on the device region I-fin portion 211 can be prevented.
In this embodiment, the epitaxial layer 240 is made of silicon. The silicon has good heat dissipation performance, and can increase the heat dissipation performance of the fin portion 211, so that the self-heating effect of the formed semiconductor structure is further reduced.
If the thickness of the epitaxial layer 240 is too small, it is not beneficial to increase the heat dissipation performance of the formed semiconductor structure; if the thickness of the epitaxial layer 240 is too large, the distance between the epitaxial layers 240 between adjacent fins 211 is easily reduced, thereby easily increasing leakage current. Specifically, in this embodiment, the thickness of the epitaxial layer 240 is 1nm to 5 nm.
The dimension of the epitaxial layer 240 in the direction of the surface of the substrate 200 is equal to the thickness of the sacrificial layer 220 (shown in fig. 6). Specifically, in this embodiment, the dimension of the epitaxial layer 240 along the surface of the substrate 200 is 2nm to 30 nm.
The process of forming the epitaxial layer 240 includes an epitaxial growth process.
In this embodiment, the reaction gas for forming the epitaxial layer 240 includes: silicon source gas, germanium source gas, ion source gas, H2And HCl; the silicon source gas includes: SiH4Or SiH2Cl2One or a combination of the above, the germanium source gas comprises GeH4。
Specifically, in this embodiment, the process parameter for forming the epitaxial layer 240 includes SiH4、SiH2Cl2、GeH4The flow rate of HCl and HCl are all 1 sccm-1000 sccm; h2The flow rate of (2) is 0.1slm to 50 slm.
Referring to fig. 9, after the epitaxial layer 240 is formed, the sidewalls 230 are removed (as shown in fig. 8).
In this embodiment, the process of removing the sidewall spacers 230 includes a wet etching process. The wet etching has good selectivity, so that the loss of the fin 211 and the epitaxial layer 240 can be reduced. In other embodiments, the process of removing the sidewall spacers includes an isotropic dry etching process.
Specifically, the etching solution for removing the sidewall spacers 230 includes phosphoric acid.
In this embodiment, after removing the sidewall spacers 230, removing the buffer layer 204 on the sidewalls of the device region I-fin 211 (as shown in fig. 8) is further included. In other embodiments, the buffer layer may not be removed.
It should be noted that, in this embodiment, before the epitaxial layer 240 is formed, a sidewall spacer 230 is formed on the sidewall of the device region I-fin 211, and the sidewall spacer 230 can prevent the epitaxial layer 240 material from being formed on the surface of the device region I-fin 211. Therefore, after the epitaxial layer 240 is formed, the sidewall spacers 230 are removed.
In the process of removing the side wall 230, the etching selectivity of the side wall 230 and the fin 211 device region I is relatively large, so that the loss of the fin 211 is relatively small in the process of removing the side wall 230. Therefore, the forming method can improve the performance of the semiconductor structure.
Referring to fig. 10, after the epitaxial layer 240 is formed, the isolation structure 250 is formed, and the isolation structure 250 covers the sidewall of the epitaxial layer 240.
In this embodiment, the surface of the isolation structure 250 is higher than the top surface of the epitaxial layer 240. Specifically, the surface of the isolation structure 250 is flush with the top surface of the heat dissipation area II.
The surface of the isolation structure 250 is higher than or flush with the top surface of the epitaxial layer 240, so that the epitaxial layer 240 does not increase the width of the semiconductor material below the subsequent gate structure. The width of the semiconductor material below the gate structure is small, and in the working process of the formed semiconductor structure, the I fin parts 211 of the device region form channels, so that the control effect of the gate structure on current carriers can be increased, and further, the leakage current is reduced.
The isolation structures 250 are used to achieve electrical isolation between adjacent fins 211.
The isolation structure 250 is made of silicon oxide, which has good insulating property and can reduce the leakage between the fin portions 211. In other embodiments, the isolation structure is made of silicon oxynitride or a low-k dielectric material.
The step of forming the isolation structure 250 includes: forming an initial isolation structure on the substrate 200, the initial isolation structure surface being higher than or flush with the fin 211 top surface; the initial isolation structure is etched to form an isolation structure 250.
The process of forming the initial isolation structure comprises a fluid chemical vapor deposition process.
In this embodiment, after removing the sidewall spacers 230, the isolation structure 250 is formed. In other embodiments, the surface of the isolation structure is lower than or flush with the top surface of the epitaxial layer, and the sidewall spacers may be removed after the isolation structure is formed.
Referring to fig. 11, after the isolation structure 250 and the epitaxial layer 240 are formed, the method further includes: forming a gate structure 260 crossing the device region Ifin 211, wherein the gate structure 260 covers the sidewall and the top surface of the device region Ifin 211.
The fin 211 is used to form a channel under the gate structure 260.
The gate structure 260 includes: the gate dielectric layer crosses the fin portion 211 in the device region I, and the gate dielectric layer covers partial side wall and the top surface of the fin portion 211; and the grid electrode is positioned on the grid dielectric layer.
The grid is made of metal or polysilicon.
In other embodiments, the fin is used to form a transistor or a diode. The forming method does not include the step of forming a gate structure.
Fig. 12 to 15 are schematic structural views of steps of another embodiment of a method for forming a semiconductor structure according to the present invention.
The same points of this embodiment as the previous embodiment are not described herein, but the differences are: the steps of forming the epitaxial layer and the isolation structure are shown in fig. 12 to 15.
Referring to fig. 12, fig. 12 is a schematic diagram of a subsequent step based on fig. 3, in which an initial epitaxial layer 310 is formed on the sidewall surfaces of the fins 211 in the device region I and the heat dissipation region II.
The process of forming the initial epitaxial layer 310 includes an epitaxial growth process.
The thickness and material of the initial epitaxial layer 310 is referenced to the thickness and material of the epitaxial layer in the previous embodiment.
In this embodiment, the material of the initial epitaxial layer 310 is different from the material of the fin 211. The material of the initial epitaxial layer 310 is silicon. The silicon has a larger heat conductivity coefficient, and can increase the heat dissipation performance of the subsequently formed epitaxial layer. In other embodiments, the material of the initial epitaxial layer may be the same as the material of the fin.
Referring to fig. 13, after forming the initial epitaxial layer 310, an isolation structure 250 is formed on the substrate 200, wherein the isolation structure 250 covers the sidewall of the initial epitaxial layer 310 of the heat dissipation region II, and the surface of the isolation structure 250 is flush with the top surface of the device region I.
And then, removing the initial epitaxial layer 310 of the device region I by using the isolation structure 250 as a mask to form an epitaxial layer.
In this embodiment, the step of removing the initial epitaxial layer 310 of the device region I is shown in fig. 14 and fig. 15.
Referring to fig. 14, the device region I initial epitaxial layer 310 is oxidized to form an oxide layer 320.
The oxidation treatment is used for oxidizing the initial epitaxial layer 310 of the device region I, so that the etching selectivity of the oxide layer 320 and the initial epitaxial layer 310 is relatively high in the subsequent process of removing the oxide layer 320, and further the loss of the fin portion 211 in the process of removing the oxide layer 320 is reduced.
In this embodiment, the device region I-fin portion 211 is not oxidized, and the thickness of the oxide layer 320 is the same as the thickness of the initial epitaxial layer 310. In other embodiments, a portion of the device region fin may be oxidized to form an oxide layer.
In this embodiment, the oxidation process includes plasma oxidation. The thickness of the oxide layer 320 formed by plasma oxidation is easier to control. In other embodiments, the oxidation process may also be a thermal oxidation process or a rapid thermal oxidation process.
In this embodiment, the reactant for the oxidation treatment includes N2And O2。
In this embodiment, the process parameters of the oxidation treatment include: the etching temperature is 700-1000 ℃, the etching time is 8-200 s, the gas pressure is 50-300 torr, and O2And N2The flow rate ratio of 1/20 to 1/5.
In this embodiment, the initial epitaxial layer 310 is made of silicon, and the oxide layer 320 is made of silicon oxide.
In this embodiment, after the oxidation treatment, the epitaxial layer 311 is formed on the epitaxial layer 310 in the heat dissipation region II.
Referring to fig. 15, the oxide layer 320 is removed (as shown in fig. 14).
The process for removing the oxide layer 320 includes one or a combination of a wet etching process and an isotropic dry etching process.
In this embodiment, after the device region iiitial epitaxial layer 310 (as shown in fig. 13) is oxidized, the device region iiitial epitaxial layer 310 is removed by removing the oxide layer 320. In the process of removing the oxide layer 320, the etching selection of the oxide layer 320 and the fin portion 211 is relatively large, so that the loss of the fin portion 211 in the device region I can be reduced, and the performance of the formed semiconductor structure can be improved. In other embodiments, the step of removing the initial epitaxial layer of the device region comprises: and etching the initial epitaxial layer of the device region by an etching process to remove the initial epitaxial layer of the device region.
With continued reference to fig. 11, embodiments of the present invention also provide a semiconductor structure comprising: a substrate 200; a fin 211 located on the substrate 200, the fin 211 including a heat dissipation region II and a device region I located on the heat dissipation region II; an epitaxial layer 240 on the sidewall surface of the heat dissipation region II fin portion 211; an isolation structure 250 located on the substrate 200, wherein the isolation structure 250 covers the sidewall of the epitaxial layer 240, and the thermal conductivity of the epitaxial layer 240 is greater than that of the isolation structure 250.
The semiconductor structure further includes: and a gate structure 260 crossing the fin 211, wherein the gate structure 260 covers part of the sidewall and the top surface of the fin 211.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (20)

1. A method of forming a semiconductor structure, comprising:
providing a substrate, wherein the substrate is provided with a fin part, and the fin part comprises a heat dissipation area and a device area positioned on the heat dissipation area;
forming an epitaxial layer and an isolation structure, wherein the epitaxial layer is positioned on the surface of the side wall of the fin part in the heat dissipation area and exposes the fin part in the device area, the isolation structure covers the side wall of the epitaxial layer, and the thermal conductivity coefficient of the material of the epitaxial layer is greater than that of the material of the isolation structure;
forming a side wall covering the side wall of the fin part device area, wherein the side wall is exposed out of the side wall of the fin part of the heat dissipation area; and forming an epitaxial layer on the surface of the side wall of the fin part exposed by the side wall by taking the side wall as a mask.
2. The method of forming a semiconductor structure of claim 1, wherein the epitaxial layer is a single crystal of silicon, germanium, silicon germanium, or a group III-V material.
3. The method of forming a semiconductor structure of claim 1, wherein the process of forming the epitaxial layer comprises an epitaxial growth process.
4. The method of claim 1, wherein the epitaxial layer has a thickness of 1nm to 5 nm; the size of the epitaxial layer along the direction vertical to the surface of the substrate is 2 nm-30 nm.
5. The method for forming a semiconductor structure according to claim 1, wherein the side walls are removed after the epitaxial layer is formed.
6. The method for forming the semiconductor structure according to claim 5, wherein the material of the sidewall is silicon nitride, silicon oxide or silicon oxynitride.
7. The method for forming the semiconductor structure according to claim 5, wherein the step of forming the side walls comprises: forming a sacrificial layer on the substrate, wherein the sacrificial layer covers the side wall of the fin part in the heat dissipation area, the fin part in the device area is exposed out of the sacrificial layer, and the material of the sacrificial layer is different from that of the side wall; forming a side wall on the side wall of the fin part exposed out of the sacrificial layer; after the side wall is formed, removing the sacrificial layer;
after the epitaxial layer is formed, the isolation structure is formed.
8. The method for forming the semiconductor structure according to claim 7, wherein the side wall is removed before the isolation structure is formed; or, after the isolation structure is formed, removing the side wall.
9. The method of forming a semiconductor structure of claim 7, wherein the step of forming a sidewall spacer on the exposed fin sidewall of the sacrificial layer comprises: forming a side wall layer covering the sacrificial layer, the exposed side wall of the fin part of the sacrificial layer and the top of the fin part; and removing the side wall layer covering the sacrificial layer to form the side wall.
10. The method of claim 9, wherein removing the sidewall layer overlying the sacrificial layer comprises: and (3) an anisotropic dry etching process.
11. The method of claim 7, wherein the sacrificial layer is a spin-on carbon layer, a silicon oxide, a silicon nitride, or an organic dielectric layer.
12. The method of claim 7, wherein when the sacrificial layer is a spin-on carbon layer, a silicon oxide layer, or an organic dielectric layer, the process of forming the sacrificial layer comprises a spin-on process;
when the material of the sacrificial layer is silicon oxide or silicon nitride, the process for forming the sacrificial layer comprises a chemical vapor deposition process, a physical vapor deposition process or an atomic layer deposition process.
13. The method of forming a semiconductor structure of claim 1, wherein the step of forming the epitaxial layer and isolation structure comprises: forming an initial epitaxial layer on the surfaces of the side walls of the fin parts of the device region and the heat dissipation region; after an initial epitaxial layer is formed, forming an isolation structure on the substrate, wherein the isolation structure covers the side wall of the initial epitaxial layer of the heat dissipation area; and removing the initial epitaxial layer of the device region by taking the isolation structure as a mask to form an epitaxial layer.
14. The method of forming a semiconductor structure of claim 13, wherein a material of the epitaxial layer is different from a material of the fin.
15. The method of forming a semiconductor structure of claim 13, wherein removing the device region initial epitaxial layer comprises: after the isolation structure is formed, carrying out oxidation treatment on the initial epitaxial layer of the device region to form an oxide layer; and removing the oxide layer.
16. The method of forming a semiconductor structure of claim 1, wherein the isolation structure surface is higher than or flush with the top surface of the epitaxial layer.
17. The method of forming a semiconductor structure of claim 1 or 16, further comprising, after forming the epitaxial layer and isolation structure: and forming a gate structure crossing the fin part of the device region, wherein the gate structure covers part of the side wall and the top surface of the fin part of the device region.
18. The method of claim 1, wherein the fin is formed from a single crystal of silicon, germanium, silicon germanium, or a group III-V material.
19. The method of claim 1, wherein a mask layer is provided on top of the fin before the epitaxial layer is formed, the mask layer being formed of an amorphous material.
20. A semiconductor structure, comprising:
a substrate;
a fin portion on the substrate, the fin portion including a heat dissipation region and a device region on the heat dissipation region;
the side wall is positioned on the surface of the side wall of the fin part of the heat dissipation area, and the side wall is exposed out of the side wall of the fin part of the heat dissipation area;
the epitaxial layer is positioned on the side wall of the fin part of the heat dissipation area exposed by the side wall, and is formed by taking the side wall as a mask;
the isolation structure is positioned on the substrate, the isolation structure covers the side wall of the epitaxial layer, and the heat conductivity coefficient of the epitaxial layer is greater than that of the isolation structure.
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CN106910713A (en) * 2015-12-22 2017-06-30 中芯国际集成电路制造(北京)有限公司 Semiconductor device and its manufacture method
CN107170723A (en) * 2016-03-07 2017-09-15 中芯国际集成电路制造(上海)有限公司 A kind of semiconductor devices and preparation method thereof, electronic installation

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