CN109960605A - A kind of ECC memory that support section is write and the method that data portion is written - Google Patents
A kind of ECC memory that support section is write and the method that data portion is written Download PDFInfo
- Publication number
- CN109960605A CN109960605A CN201910256708.6A CN201910256708A CN109960605A CN 109960605 A CN109960605 A CN 109960605A CN 201910256708 A CN201910256708 A CN 201910256708A CN 109960605 A CN109960605 A CN 109960605A
- Authority
- CN
- China
- Prior art keywords
- module
- write
- command
- memory
- command process
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 238000000034 method Methods 0.000 title claims abstract description 75
- 230000015654 memory Effects 0.000 title claims abstract description 69
- 230000011664 signaling Effects 0.000 claims abstract description 17
- FGUUSXIOTUKUDN-IBGZPJMESA-N C1(=CC=CC=C1)N1C2=C(NC([C@H](C1)NC=1OC(=NN=1)C1=CC=CC=C1)=O)C=CC=C2 Chemical compound C1(=CC=CC=C1)N1C2=C(NC([C@H](C1)NC=1OC(=NN=1)C1=CC=CC=C1)=O)C=CC=C2 FGUUSXIOTUKUDN-IBGZPJMESA-N 0.000 claims description 6
- GNFTZDOKVXKIBK-UHFFFAOYSA-N 3-(2-methoxyethoxy)benzohydrazide Chemical compound COCCOC1=CC=CC(C(=O)NN)=C1 GNFTZDOKVXKIBK-UHFFFAOYSA-N 0.000 claims description 3
- 230000002457 bidirectional effect Effects 0.000 abstract description 3
- 230000004048 modification Effects 0.000 description 5
- 238000012986 modification Methods 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 3
- 238000001514 detection method Methods 0.000 description 2
- 230000006399 behavior Effects 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000007774 longterm Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
- G06F11/1044—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices with specific ECC/EDC distribution
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
- G06F11/1048—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using arrangements adapted for a specific error detection or correction feature
- G06F11/1056—Updating check bits on partial write, i.e. read/modify/write
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
- Memory System Of A Hierarchy Structure (AREA)
Abstract
The invention discloses a kind of ECC memories that support section is write, including command process module, instruction cache module, memory module, signaling module, coding module and decoding module are controlled, wherein command process module receives and analyzes new command, internal setting instruction flag position RMW_flag comes whether mark can receive new command simultaneously, while caching instructions to be performed is carried out by instruction cache module.The present invention provides a kind of ECC memory that support section is write, and introduces and reads the clock cycle that flag bit RMW_flag to obtain operation bidirectional memory for part write command, to solve by partial write bring address conflict issues.
Description
Technical field
The present invention relates to the sides that memory technology more particularly to a kind of ECC memory that support section is write and data portion are written
Method.
Background technique
Since volatile ram is widely used in main control chip very much, in order to ensure main control chip is reliably and with long-term and to transport
Work is stablized, and suitably mechanism for correcting errors is required.
Due to data with different attribute, the write-in of memory is likely to be partial write (partial write), it is further contemplated that system is transported
The stability of work added mechanism for correcting errors, and the operation of partial write must be divided into 3 steps " reading --- modification --- to write ", part
The operation write compared to conventional write and read operation for, have more the access once to memory, and this extra primary visit
Ask can the read or write to after cause address conflict, to cause to perplex to user.
Summary of the invention
It is an object of the invention to overcome the deficiencies of existing technologies, a kind of ECC memory that support section is write is provided, is introduced
It reads the clock cycle that flag bit RMW_flag to obtain operation bidirectional memory for part write command, to solve by partial write bring
Address conflict issues.
To achieve the above object, the following technical solutions are proposed: a kind of ECC memory that support section is write by the present invention, comprising:
One command process module, is communicated with external circuit, receives the new command that external circuit sends over, and analyze and determine
Whether new command is part write command, is equipped with instruction flag position RMW_flag, described instruction mark in described instruction processing module
Position has 0 and 1 two states, and 0 indicates to can receive new instruction, and 1 indicates that new instruction cannot be received:
One instruction cache module, connect with command process module, caches pending instruction when instruction flag position is 1；
One memory module；
One control signaling module, connect with command process module and memory module, the control sent according to command process module respectively
Signal processed, control memory module carry out storage or read operation, while feeding back and completing signal to command process module；
One coding module, connect with command process module and memory module respectively, compiles to the logic word of command process module input
Code, generates corresponding parity check bit and logic word composition physics word is sent into memory module；
One decoding module, connect with command process module and memory module respectively, and physics word is read from memory module and is solved
Code error correction generates error correcting code, sends decoded logic word and error correcting code to command process module.
Preferably, the part write command includes reading, modifying and write three operations.
The preferred error correcting code is extended hamming code.
A kind of method of ECC data in EMS memory partial write, includes the following steps:
A, command process module receives external new command, reads the value of instruction flag position RMW_flag, just send new command if 1
Enter in instruction cache module, waiting receives next time, receives new command if 0, and execute step b；
B, the enable signal that command process module reads data bit in new command indicates that this refers to if the enable signal is all effective
Order is not part write command, thens follow the steps c, if the enable signal part is effective, indicates that the instruction is part write command, executes
Step f；
Control signal in instruction is sent to control signaling module and is sent into memory module by c command process module, and in instructing
Logic word send to coding module and encoded；
D, coding module encodes logic word, and is sent into memory module and is stored；
E, control signaling module feedback operation completes signal to command process module, completes new command write-in, return step a；
F, command process module sends read command, based on the data word provided according to decoding module, is repaired according to part write order
Change data word content, retransmit write order, executes step g, while setting 1 for instruction flag position,
G, command process module encodes modified data word feeding encoder, and is sent into memory module and is stored,
The control signal in the write command of part is sent to control signaling module and is sent into memory module by command process module simultaneously；
H, control signaling module feedback operation completes signal to command process module, completes the write-in of part write command, will instruct
Flag bit is set as 0, return step a.
Preferably, controlling signal in the step c includes read signal or write signal and address signal.
Preferably, coding module encodes logic word in the step d, logic word and corresponding is exported
Parity check bit.
Preferably, in the step f decoding module read memory module physics word, according to coding schedule to logic word into
Row ECC operation generates error correcting code together with logic word and forms data word feeding command process module.
Compared with prior art, the ECC memory that a kind of disclosed support section is write, draws in processing module
Flag bit RMW_flag is studied in, the clock cycle of operation bidirectional memory is obtained for part write command, solution is brought by partial write
Address conflict issues, realize memory partial write operation.
Detailed description of the invention
Fig. 1 is memory modules figure of the invention；
Fig. 2 is the block diagram of tissue physics word of the present invention；；
Fig. 3 is the discriminatory analysis process of command process module in the present invention.
Specific embodiment
Below in conjunction with attached drawing of the invention, clear, complete description is carried out to the technical solution of the embodiment of the present invention.
As shown in Figure 1, the ECC memory that a kind of disclosed support section is write, including command process module, instruction
Cache module, memory module control signaling module, coding module and decoding module, in which:
Command process module is communicated with external circuit, receives new command (including the conventional read-write that external circuit sends over
Instruction and part write command), instruction flag position RMW_flag is provided in the command process module to determine whether can receive
New command, the instruction flag position have 0 and 1 two state, and 0 indicates that new command can be received, and 1 indicates that inside will enforcement division
Divide write command, new command can not be received, furthermore command process module can also analyze received instruction, pass through and read number
According to the effectiveness of position enable signal carry out decision instruction classification.
Described instruction cache module is connect with command process module, and when instruction flag position is 1, command process module can not
Reading instruction is executed, and the instruction in the input of this clock cycle inside and outside can not be dealt with immediately, then be sent into instruction cache module
Middle caching, the command information of caching include read/write, address, data, gating signal, and when command process module can receive newly
When instruction, instruction in priority processing cache module, and for being newly sent into then successively storing to instruction cache module for instruction.
Further, since partial write operation delay always that memory module is updated more than general read-write operation several
(be set as M), if to the progress read operation of same address, memory module in M clock cycle after a part write order
Output is rather than the updated new data with regard to data, then instruction cache module sends caution signal to command process module
It is handled.
The memory module is for the relevant instruction information in storage circuit.
The control signaling module is connect with command process module and memory module respectively, is sent according to command process module
Control signal (including read/write, address), control memory module carry out storage or read operation, while feed back complete signal (packet
Include run through and address) to command process module.
The coding module is connect with command process module and memory module respectively, to the logic of command process module input
Word is encoded, and generates corresponding parity check bit and logic word composition physics word is sent into memory module；
The decoding module is connect with command process module and memory module respectively, according to extended hamming code decoding principle, from depositing
Physics word is read in storage module to be decoded, and the data word and its error detection (there are 0/1/2 bit errors) Jing Guo error correction are exported,
Institute's data word is made of logic word and error correcting code, and error correcting code is extended hamming code.
The part write command includes reading, modifying and write three operations, wherein reading is to read storage mould by decoding module
Original data word in block, modification, which is command process module, carries out data word in conjunction with part write command according to original data word
Modification, writing is that modified data word is recompiled feeding memory module by coding module.
As shown in Fig. 2, physics word 13 in total in memory module, including 8 data bit (d0 ~ d7), 4 error correcting codes (h0 ~
) and 1 bit parity check position (p) h3.
A kind of method that the present invention discloses ECC data in EMS memory partial write, includes the following steps:
A, command process module receives external new command, reads the value of instruction flag position RMW_flag, just send new command if 1
Enter in instruction cache module, waiting receives next time, receives new command if 0, and it is as shown in Figure 3 to execute step b()；
B, the enable signal that command process module reads data bit in new command indicates that this refers to if the enable signal is all effective
Order is not part write command, thens follow the steps c, if the enable signal part is effective, indicates that the instruction is part write command, executes
Step f(is as shown in Figure 3)；
Control signal in instruction is sent to control signaling module and is sent into memory module by c command process module, and in instructing
Logic word send to coding module and encoded；
D, coding module encodes logic word, and is sent into memory module and is stored；
E, control signaling module feedback operation completes signal to command process module, completes new command write-in, return step a；
F, command process module sends read command, based on the data word provided according to decoding module, is repaired according to part write order
Change data word content, retransmit write order, executes step g, while setting 1 for instruction flag position,
G, command process module encodes modified data word feeding encoder, and is sent into memory module and is stored,
The control signal in the write command of part is sent to control signaling module and is sent into memory module by command process module simultaneously；
H, control signaling module feedback operation completes signal to command process module, completes the write-in of part write command, will instruct
Flag bit is set as 0, return step a.
It includes read signal or write signal and address signal that signal is controlled in the step c；Coding module pair in the step d
Logic word is encoded, and logic word and corresponding parity check bit are exported；Decoding module reads storage in the step f
The physics word of module carries out ECC operation to logic word according to coding schedule, generates error correcting code together with logic word and forms data word feeding
Command process module.
Under partial write operation, first read operation also has corresponding decoded operation, and similarly, ECC exports decoding module
Output data and the record of error detection or error correction；Differently, in the case where partial write, third write operation can will decode process
Error correction result substitutes into, and at this moment position selects signal all effective, i.e., corrects the single-bit error in memory module automatically.
Present invention improves over the storage mode of ECC memory, the support to partial write is increased, and solve by partial write
Bring address conflict issues make it not influence the error correction of error correcting code and subsequent read-write behaviour in the case where partial write
Make.
Technology contents and technical characteristic of the invention have revealed that as above, however those skilled in the art still may base
Make various replacements and modification without departing substantially from spirit of that invention, therefore, the scope of the present invention in teachings of the present invention and announcement
It should be not limited to the revealed content of embodiment, and should include various without departing substantially from replacement and modification of the invention, and be this patent Shen
Please claim covered.
Claims (7)
1. a kind of ECC memory that support section is write, characterized by comprising:
One command process module, is communicated with external circuit, receives the new command that external circuit sends over, and analyze and determine
Whether new command is part write command, is equipped with instruction flag position RMW_flag, described instruction mark in described instruction processing module
Position has 0 and 1 two states, and 0 indicates to can receive new instruction, and 1 indicates that new instruction cannot be received:
One instruction cache module, connect with command process module, caches pending finger when instruction flag position RMW_flag is 1
It enables；
One memory module；
One control signaling module, connect with command process module and memory module, the control sent according to command process module respectively
Signal processed, control memory module carry out storage or read operation, while feeding back and completing signal to command process module；
One coding module, connect with command process module and memory module respectively, compiles to the logic word of command process module input
Code, generates corresponding parity check bit and logic word composition physics word is sent into memory module；
One decoding module, connect with command process module and memory module respectively, and physics word is read from memory module and is solved
Code error correction generates error correcting code, sends decoded logic word and error correcting code to command process module.
2. the ECC memory that support section according to claim 1 is write, it is characterised in that: the part write command include read,
Modify and write three operations.
3. the ECC memory that support section according to claim 1 is write, it is characterised in that: the error correcting code is extension Hamming
Code.
4. a kind of method of ECC data in EMS memory partial write is realized based on ECC memory described in claim 1, it is characterised in that
Including following content:
A, command process module receives external new command, reads the value of instruction flag position RMW_flag, just send new command if 1
Enter in instruction cache module, waiting receives next time, receives new command if 0, and execute step b；
B, the enable signal that command process module reads data bit in new command indicates that this refers to if the enable signal is all effective
Order is not part write command, thens follow the steps c, if the enable signal part is effective, indicates that the instruction is part write command, executes
Step f；
C, the control signal in instruction is sent to control signaling module and is sent into memory module by command process module, and in instructing
Logic word send to coding module and encoded；
D, coding module encodes logic word, and is sent into memory module and is stored；
E, control signaling module feedback operation completes signal to command process module, completes new command write-in, return step a；
F, command process module sends read command, based on the data word provided according to decoding module, is repaired according to part write order
Change data word content, retransmit write order, executes step g, while setting 1 for instruction flag position,
G, command process module encodes modified data word feeding encoder, and is sent into memory module and is stored,
The control signal in the write command of part is sent to control signaling module and is sent into memory module by command process module simultaneously；
H, control signaling module feedback operation completes signal to command process module, completes the write-in of part write command, will instruct
Flag bit is set as 0, return step a.
5. the method for ECC data in EMS memory partial write according to claim 4, it is characterised in that: controlled in the step c
Signal processed includes read signal or write signal and address signal.
6. the method for ECC data in EMS memory partial write according to claim 4, it is characterised in that: compiled in the step d
Code module encodes logic word, exports logic word and corresponding parity check bit.
7. the method for ECC data in EMS memory partial write according to claim 4, it is characterised in that: translated in the step f
Code module reads the physics word of memory module, carries out ECC operation to logic word according to coding schedule, generates error correcting code together with logic word
It forms data word and is sent into command process module.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910256708.6A CN109960605A (en) | 2019-04-01 | 2019-04-01 | A kind of ECC memory that support section is write and the method that data portion is written |
| PCT/CN2019/103951 WO2020199492A1 (en) | 2019-04-01 | 2019-09-02 | Ecc memory supporting partial write, and partial data write method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910256708.6A CN109960605A (en) | 2019-04-01 | 2019-04-01 | A kind of ECC memory that support section is write and the method that data portion is written |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN109960605A true CN109960605A (en) | 2019-07-02 |
Family
ID=67025509
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910256708.6A Withdrawn CN109960605A (en) | 2019-04-01 | 2019-04-01 | A kind of ECC memory that support section is write and the method that data portion is written |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN109960605A (en) |
| WO (1) | WO2020199492A1 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2020199492A1 (en) * | 2019-04-01 | 2020-10-08 | 江苏华存电子科技有限公司 | Ecc memory supporting partial write, and partial data write method |
| CN113495862A (en) * | 2021-06-29 | 2021-10-12 | 山东华芯半导体有限公司 | Bus bridge device with ECC function |
| CN114047950A (en) * | 2021-11-05 | 2022-02-15 | 山东云海国创云计算装备产业创新中心有限公司 | Vector register system and processor supporting flexible grouping of ultra-wide registers |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007133986A (en) * | 2005-11-11 | 2007-05-31 | Nec Electronics Corp | Semiconductor memory |
| GB2516831B (en) * | 2013-07-31 | 2020-10-21 | Advanced Risc Mach Ltd | Error code management in systems permitting partial writes |
| CN106991073B (en) * | 2016-01-20 | 2020-06-05 | 中科寒武纪科技股份有限公司 | Data read-write scheduler and reservation station for vector operation |
| US10372531B2 (en) * | 2017-01-05 | 2019-08-06 | Texas Instruments Incorporated | Error-correcting code memory |
| CN109960605A (en) * | 2019-04-01 | 2019-07-02 | 江苏华存电子科技有限公司 | A kind of ECC memory that support section is write and the method that data portion is written |
-
2019
- 2019-04-01 CN CN201910256708.6A patent/CN109960605A/en not_active Withdrawn
- 2019-09-02 WO PCT/CN2019/103951 patent/WO2020199492A1/en active Application Filing
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2020199492A1 (en) * | 2019-04-01 | 2020-10-08 | 江苏华存电子科技有限公司 | Ecc memory supporting partial write, and partial data write method |
| CN113495862A (en) * | 2021-06-29 | 2021-10-12 | 山东华芯半导体有限公司 | Bus bridge device with ECC function |
| CN114047950A (en) * | 2021-11-05 | 2022-02-15 | 山东云海国创云计算装备产业创新中心有限公司 | Vector register system and processor supporting flexible grouping of ultra-wide registers |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2020199492A1 (en) | 2020-10-08 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8493797B2 (en) | Memory system and method having volatile and non-volatile memory devices at same hierarchical level | |
| US7921339B2 (en) | Flash storage device with data correction function | |
| CN109960605A (en) | A kind of ECC memory that support section is write and the method that data portion is written | |
| CN112823340B (en) | In-package sequencer for performing error correction and memory test operations | |
| CN105340022A (en) | Circuits, apparatuses, and methods for correcting data errors | |
| US7979737B2 (en) | Method for accessing a Flash memory, and associated memory device and controller thereof | |
| US20130283081A1 (en) | Memory Array Power Cycling | |
| CN109903806A (en) | A kind of double mode error detection memory and double mode error-detecting method | |
| US11573734B2 (en) | Method for improving read-retry of flash memory and related controller and storage device | |
| KR102774807B1 (en) | Nonvolatile memory device and memory system including nonvolatile memory device | |
| KR20210024188A (en) | Write buffer management | |
| US11675714B2 (en) | Memory sub-system including an in package sequencer separate from a controller | |
| US11567817B2 (en) | Providing bandwidth expansion for a memory sub-system including a sequencer separate from a controller | |
| CN103995785A (en) | Information processing method and system | |
| US20180275917A1 (en) | Memory controller, memory system, and control method | |
| US12334168B2 (en) | Flash memory module testing method and associated memory controller and memory device | |
| KR20140108886A (en) | Method and apparatus for controlling memory in mobile communication system | |
| US10180888B2 (en) | Memory sparing on memory modules | |
| US20150363330A1 (en) | Flash NAND device bad page replacement | |
| KR100280457B1 (en) | How to read and write data in flash memory | |
| US11327770B2 (en) | Data storage devices, access device and data processing methods | |
| JPS5857700A (en) | Processing system for single bit error of memory | |
| JPS59114654A (en) | Memory device | |
| JPS61248140A (en) | Redundant code checking system |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| WW01 | Invention patent application withdrawn after publication | ||
| WW01 | Invention patent application withdrawn after publication |
Application publication date: 20190702 |