CN109936378B - Method and device for realizing disorder decoding of LDPC (Low Density parity check) - Google Patents
Method and device for realizing disorder decoding of LDPC (Low Density parity check) Download PDFInfo
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Abstract
The invention provides a method and a device for realizing LDPC out-of-order decoding. The method comprises the following steps: selecting a mother sequence aiming at a base graph used by the LDPC code, wherein the mother sequence is a disordered sequence aiming at the maximum row number preset according to the LDPC code with different code rates of the base graph; selecting the disorder sequence of the row block for decoding from the mother sequence according to the row index number required by decoding; performing row disorder on the basic matrix of the LDPC code according to the disorder sequence of the row block for decoding; layering the rows of the base matrix after disorder; and carrying out pipeline decoding on the layered basic matrix. The invention can realize the out-of-order layered decoding of the NR LDPC codes with different code rates only by one out-of-order sequence for the same base graph, thereby reducing the hardware cost.
Description
Technical Field
The invention relates to the technical field of wireless communication, in particular to a method and a device for realizing out-of-order decoding of LDPC (Low Density parity check code).
Background
For BP (Belief Propagation) decoding or Min-sum (minimum sum) decoding of LDPC (Low Density Parity Check code), within each iteration, serial layered decoding can save half of the number of iterations as compared to full parallel flood decoding. However, this condition is satisfied on the premise that: (1) the rows within each layer of the layered decoding are orthogonal; (2) the decoding of the previous layer requires updating of the soft information of the codeword bits before the decoding of the next layer starts. For QC-LDPC (Quasi-Cyclic, Quasi-Cyclic LDPC) of NR (New Radio, New gap), condition (1) is satisfied.
For a hardware-implemented LDPC layered decoder, decoding of each layer generally requires p clock cycles (typical value of p is 5-8). In the clock period, the layer has not obtained the soft information decoding result output of the code word bit. In order to reduce the decoding delay, the pipeline structure shown in fig. 1 is used for decoding between different layers. As can be seen from fig. 1, in p clock cycles, the layer decoded later cannot use the decoding result of the layer decoded earlier. Therefore, the condition (2) is not satisfied, which affects the iterative convergence speed of the layered decoding, i.e., increases the number of required iterations.
If one can try to minimize the "conflict" between different layers over p clock cycles, one can expect that the impact on the iteration convergence speed will be reduced. That is, a scheme with small "collisions" between different layers requires fewer iterations for the same decoding performance than a scheme with large "collisions". Here, "collision" means the number of "1" corresponding to the same position in each row in the check matrix for two layers belonging to different row blocks. (if both layers belong to the same row block, the collision is 0, since the different rows within the row block are orthogonal).
The existing solution is to change the decoding order of different layers by layer disorder, so as to minimize the conflict between layers in p clock cycles. Layer out-of-order is achieved by an out-of-order sequence stored in firmware.
Since the NR LDPC code supports a variety of code rates by the scaling of the base pattern, the number of rows of the base pattern is variable. For example, for the base graph 1 shown in fig. 2, the number of complete rows is 46 (corresponding to the lowest bitrate 1/3), and only 4 rows are supported when the highest bitrate 22/24 is supported.
In addition to the variable number of lines, due to the presence of HARQ (Hybrid Automatic Repeat reQuest), different RVs (Redundancy versions) may also cause the lines required for decoding to be variable. For example, the starting position of RV0 is column 0, and if the initial transmission rate is 22/25, the index number of the row involved in the initial transmission decoding is 5 rows, which is 0-4; and the RV2 starting position of the first retransmission is column 33 (corresponding to row 13), and the retransmission length is the same as the initial transmission length, then after the first retransmission, RV0 and RV2 are merged, and the index numbers of the involved rows of decoding are 0-4 and 13-45, which are 38 rows.
According to the existing general disorder implementation method, only the scalable code rate is considered, and the layer disorder for carrying out layered decoding on 43 disorder sequences of 4-46 rows needs to be designed for the base map 1; similarly, 39 out-of-order sequences for 4-42 rows need to be designed for the base graph 2 shown in fig. 3 (the possibility of the required rows due to HARQ RV has not been considered above). For hardware implementation, only the rate firmware needs to store up to 43+ 39-82 out-of-order sequences, and considering that the HARQ RV has more sequences to store, the hardware overhead is too high.
Disclosure of Invention
The method and the device for realizing the disorder decoding of the LDPC provided by the invention can realize the disorder layered decoding of the NR LDPC codes with different code rates by only needing one disorder sequence for the same base graph, thereby reducing the hardware cost.
In a first aspect, the present invention provides a method for implementing LDPC out-of-order decoding, including:
selecting a mother sequence aiming at a base graph used by the LDPC code, wherein the mother sequence is a disordered sequence aiming at the maximum row number preset according to the LDPC code with different code rates of the base graph;
selecting the disorder sequence of the row block for decoding from the mother sequence according to the row index number required by decoding;
performing line disorder on the basic matrix of the LDPC code according to the disorder sequence of the line block for decoding;
layering the rows of the base matrix after disorder;
and carrying out pipeline decoding on the layered basic matrix.
Optionally, the selecting, according to the row index number required for decoding, an out-of-order sequence of row blocks for decoding from the mother sequence includes: and selecting the row index numbers required by decoding from the mother sequence to form a subsequence which is used as a disorder sequence of the row blocks for decoding.
Optionally, the layering the rows of the out-of-order base matrix comprises: and layering the rows of the base matrix after disorder according to the layer size determined by the hardware parallel capability.
Optionally, the layering the rows of the base matrix after the out-of-order according to the layer size determined by the hardware parallelism capability includes: determining the number of row blocks of the check matrix capable of being processed in parallel according to the hardware parallel capability, and layering the row blocks of each check matrix after disorder according to the number of the row blocks of the check matrix capable of being processed in parallel, wherein rows of the base matrix are the row blocks of the check matrix.
In a second aspect, the present invention provides an apparatus for implementing LDPC out-of-order decoding, comprising:
a first selecting unit, configured to select a mother sequence for a base graph used by an LDPC code, where the mother sequence is a disordered sequence for a maximum number of rows preset according to LDPC codes of different code rates of the base graph;
the second selection unit is used for selecting the disorder sequence of the row block for decoding from the mother sequence according to the row index number required by decoding;
a disorder unit, configured to perform row disorder on the basic matrix of the LDPC code according to a disorder sequence of the row block for decoding;
the layering unit is used for layering the rows of the base matrix after disorder;
and the decoding unit is used for carrying out pipeline decoding on the layered basic matrix.
Optionally, the second selecting unit is configured to select a row index number required for decoding from the parent sequence to form a subsequence, which is used as an out-of-order sequence of the row block for decoding.
Optionally, the layering unit is configured to layer the rows of the base matrix after the misordering according to a layer size determined by the hardware parallelism.
Optionally, the layering unit is configured to determine, according to the hardware parallel capability, a number of row blocks of a check matrix that can be processed in parallel, and layer, according to the number of row blocks of the check matrix that can be processed in parallel, the row blocks of each out-of-order check matrix, where a row of the base matrix is a row block of the check matrix.
The method and the device for realizing the disordered decoding of the LDPC code provided by the embodiment of the invention select a mother sequence aiming at a base graph used by the LDPC code, wherein the mother sequence is a disordered sequence aiming at the maximum row number preset according to the LDPC code with different code rates of the base graph, select a disordered sequence of a row block for decoding from the mother sequence according to a row index number required by decoding, disorder a basic matrix of the LDPC code according to the disordered sequence of the row block for decoding, and layer rows of the disordered basic matrix; and carrying out pipeline decoding on the layered basic matrix. Compared with the prior art, the invention can realize the out-of-order layered decoding of the NR LDPC codes with different code rates only by one out-of-order sequence for the same base graph, thereby reducing the hardware cost.
Drawings
FIG. 1 is a schematic diagram of LDPC decoding using a pipeline structure in the prior art;
FIG. 2 is a diagram of the basic diagram of an NR LDPC code 1;
FIG. 3 is a diagram of the base of an NR LDPC code 2;
FIG. 4 is a flowchart of a method for implementing LDPC out-of-order decoding according to an embodiment of the present invention;
FIG. 5 is a decoding flow diagram of an implementation method of LDPC out-of-order decoding according to an embodiment of the present invention;
FIG. 6 is a schematic view of another decoding flow chart of an LDPC out-of-order decoding implementation method according to an embodiment of the present invention;
fig. 7 is a schematic structural diagram of an LDPC out-of-order decoding implementation apparatus according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The embodiment of the invention provides a method for realizing disordered decoding of LDPC (low density parity check), which comprises the following steps of:
s11, selecting a mother sequence aiming at a base graph used by the LDPC code, wherein the mother sequence is a disordered sequence aiming at the maximum row number preset according to the LDPC code with different code rates of the base graph.
Wherein, the base graph is a characteristic expression mode of the QC-LDPC check matrix. An element "0" in the base diagram indicates that the corresponding position of the check matrix is a Z × Z all-zero matrix, and an element "1" indicates that the corresponding position of the check matrix is a Z × Z identity matrix or a cyclic right shift of the identity matrix.
And S12, selecting the disorder sequence of the row block for decoding from the mother sequence according to the row index number required by decoding.
Specifically, the row index number required for decoding is selected from the parent sequence to form a subsequence which is used as the disorder sequence of the row block for decoding.
And S13, performing row disordering on the basic matrix of the LDPC code according to the disordering sequence of the row block for decoding.
Wherein, the basic matrix is a characteristic expression mode of the QC-LDPC check matrix. An element "-1" in the base matrix indicates that the corresponding position of the check matrix is an all-zero matrix of Z × Z, and an element "N" greater than or equal to 0 indicates that the corresponding position of the check matrix is a cyclic right shift of the identity matrix of Z × Z by N bits. The base matrix corresponds exclusively to the check matrix of the code.
And S14, layering the rows of the base matrix after disorder.
Specifically, the number of rows of the check matrix capable of being processed in parallel is determined according to the hardware parallel capability, and the row blocks of each check matrix after disorder are layered according to the number of rows of the check matrix capable of being processed in parallel, wherein one row block of the check matrix (i.e., Z rows of the check matrix) corresponds to one row of the base graph or the base matrix.
And S15, performing pipeline decoding on the layered basic matrix.
The method for realizing the disordered decoding of the LDPC code provided by the embodiment of the invention selects a mother sequence aiming at a base graph used by the LDPC code, wherein the mother sequence is a disordered sequence aiming at the maximum row number preset according to the LDPC code with different code rates of the base graph, selects a disordered sequence of a row block for decoding from the mother sequence according to a row index number required by decoding, conducts the disordered sequence on a basic matrix of the LDPC code according to the disordered sequence of the row block for decoding, and divides the rows of the disordered basic matrix into layers; and carrying out pipeline decoding on the layered basic matrix. Compared with the prior art, the invention can realize the out-of-order layered decoding of the NR LDPC codes with different code rates only by one out-of-order sequence for the same base graph, thereby reducing the hardware cost.
The method for implementing LDPC out-of-order decoding of the present invention is explained in detail below.
The invention uses the sequence with the characteristic of 'nesting', and provides the LDPC codes with different code rates of the base graph 1 and the base graph 2 with only one disorder sequence aiming at the maximum row number respectively, which is called as a mother sequence 1 and a mother sequence 2 respectively. For the LDPC decoding under the condition of less than the maximum row number, the row index number required by decoding is selected from the mother sequence 1 or 2 to form a disorder sequence suitable for the decoding, and the decoding sequence of each layer of the layered decoding is disordered. This is also the meaning of the "nested" feature. The NR LDPC decoding adopting the technical scheme of the invention specifically comprises the following steps:
(1) selecting a mother sequence 1 or 2 according to a base graph 1 or 2 used by the LDPC code respectively;
(2) aiming at the row index number related to decoding, selecting the related row index number from the mother sequence 1 or 2 as a disorder sequence for decoding;
(3) the basic matrix is subjected to line disorder through a disorder sequence;
(4) the rows of the out-of-order base matrix (i.e., row blocks of the check matrix) are layered according to a layer size determined by the hardware parallelism capability (typically, a row block may be divided into 1 layer, 2 layers, or more).
(5) And carrying out pipeline decoding on the layered basic matrix.
The method for implementing the LDPC out-of-order decoding is described in detail below with reference to specific embodiments.
Example 1:
[0,4,5,6, (null), 13,14,15,16,17,18,19,20,
1,7,8, (null), 21,22,23,24,25,26,27,28,29,
2,9,10, (empty), 30,31,32,33,34,35,36,37,
3,11,12, (null), 38,39,40,41,42,43,44,45]
The "null" in the parent sequence refers to the clock cycle, and the decoder does not perform any decoding, or to an empty run.
Parent sequence 2 of base FIG. 2:
[0,4,8,12, (null), 16,18,19,20,21,22,23,
1,5,9,13, (null), 17,24,25,26,27,28,29,
2,6,10,14, (null), 30,31,32,33,34,35,
3,7,11,15, (null), 36,37,38,39,40,41]
For the NR LDPC code based on the basic graph 1, the involved basic graph line numbers are 0-4 and 13-45 decoding involves the steps executed according to the technical scheme described above:
(1) the mother sequence 1 was selected from the base fig. 1.
(2) For the row index numbers involved, the following out-of-order sequence is chosen from the mother sequence 1.
[0,4, (null), 13,14,15,16,17,18,19,20,
1, (null), 21,22,23,24,25,26,27,28,29,
2, (empty), 30,31,32,33,34,35,36,37,
3, (null), 38,39,40,41,42,43,44,45
(3) And (3) performing row disorder on the basic matrix of the LDPC code according to the disorder sequence obtained in the step (2).
(4) Assuming that the current hardware capability can only process half line blocks in parallel, each line block after disorder is divided into two layers.
(5) The decoding pipeline is as shown in fig. 5 (assuming that each layer of decoding requires 8 clock cycles).
Example 2:
the parent sequence 1 and parent sequence 2 of FIGS. 1 and 2 are the same as those of example 1.
For the NR LDPC code based on the base graph 2, the decoding of the related base graph row numbers of 0-3 involves the steps executed according to the technical scheme described above:
(1) the mother sequence 2 is selected from the base fig. 2.
(2) For the involved row index numbers, the following out-of-order sequence is selected from the mother sequence 1:
[0, (null), 1, (null), 2, (null), 3, (null) ]
(3) And (3) performing row disorder on the basic matrix of the LDPC code according to the disorder sequence obtained in the step (2).
(4) Assuming that the current hardware capability can only process the whole line block in parallel, each out-of-order line block is divided into one layer.
(5) The decoding pipeline is as shown in fig. 6 (assuming that each layer of decoding requires 8 clock cycles).
An embodiment of the present invention further provides an apparatus for implementing out-of-order decoding of LDPC, as shown in fig. 7, the apparatus includes:
a first selecting unit 11, configured to select a mother sequence for a base graph used by an LDPC code, where the mother sequence is a disordered sequence for a maximum number of rows preset according to LDPC codes of different code rates of the base graph;
a second selecting unit 12, configured to select an out-of-order sequence of a row block for decoding from the mother sequence according to a row index number required for decoding;
a disorder unit 13, configured to perform row disorder on the basic matrix of the LDPC code according to the disorder sequence of the row block for decoding;
a layering unit 14 configured to layer the rows of the out-of-order base matrix;
and a decoding unit 15, configured to perform pipeline decoding on the layered base matrix.
The device for realizing disordered decoding of the LDPC provided by the embodiment of the invention selects a mother sequence aiming at a base graph used by the LDPC, wherein the mother sequence is a disordered sequence aiming at the maximum row number preset according to the LDPC with different code rates of the base graph, selects a disordered sequence of a row block for decoding from the mother sequence according to a row index number required by decoding, conducts disordered sequence on a basic matrix of the LDPC according to the disordered sequence of the row block for decoding, and divides rows of the disordered basic matrix into layers; and carrying out pipeline decoding on the layered basic matrix. Compared with the prior art, the invention can realize the out-of-order layered decoding of the NR LDPC codes with different code rates only by one out-of-order sequence for the same base graph, thereby reducing the hardware cost.
Optionally, the second selecting unit 12 is configured to select a row index number required for decoding from the parent sequence to form a subsequence, and the subsequence is used as a disorder sequence of the row block for decoding.
Optionally, the layering unit 14 is configured to layer the rows of the base matrix after the disorder according to a layer size determined by the hardware parallelism.
Optionally, the layering unit 14 is configured to determine the number of row blocks of the check matrix that can be processed in parallel according to the hardware parallel capability, and layer the row blocks of each out-of-order check matrix according to the number of row blocks of the check matrix that can be processed in parallel, where rows of the base matrix are row blocks of the check matrix.
The apparatus of this embodiment may be configured to implement the technical solutions of the above method embodiments, and the implementation principles and technical effects are similar, which are not described herein again.
It will be understood by those skilled in the art that all or part of the processes of the methods of the embodiments described above can be implemented by a computer program, which can be stored in a computer-readable storage medium, and when executed, can include the processes of the embodiments of the methods described above. The storage medium may be a magnetic disk, an optical disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), or the like.
The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are also within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (6)
1. An out-of-order decoding implementation method of LDPC is characterized by comprising the following steps:
selecting a mother sequence aiming at a base graph used by the LDPC code, wherein the mother sequence is a disordered sequence aiming at the maximum row number preset according to the LDPC code with different code rates of the base graph;
selecting the disorder sequence of the row block for decoding from the mother sequence according to the row index number required by decoding;
performing row disorder on the basic matrix of the LDPC code according to the disorder sequence of the row block for decoding;
layering the rows of the base matrix after disorder;
performing pipeline decoding on the layered basic matrix;
the selecting the disorder sequence of the row block for decoding from the mother sequence according to the row index number required by decoding comprises the following steps: and selecting the line index numbers required by decoding from the mother sequence to form a subsequence serving as a disorder sequence of the line blocks for decoding.
2. The method of claim 1, wherein layering the rows of the out-of-order base matrix comprises: and layering the rows of the base matrix after disorder according to the layer size determined by the hardware parallel capability.
3. The method of claim 2, wherein layering the rows of the out-of-order base matrix according to the layer size determined by the hardware parallelism capability comprises: determining the number of row blocks of the check matrix capable of being processed in parallel according to the hardware parallel capability, and layering the row blocks of each check matrix after disorder according to the number of the row blocks of the check matrix capable of being processed in parallel, wherein rows of the base matrix are the row blocks of the check matrix.
4. An apparatus for implementing out-of-order decoding of LDPC codes, comprising:
a first selecting unit, configured to select a mother sequence for a base graph used by an LDPC code, where the mother sequence is a disordered sequence for a maximum number of rows preset according to LDPC codes of different code rates of the base graph;
the second selection unit is used for selecting the disorder sequence of the row block for decoding from the mother sequence according to the row index number required by decoding;
a disorder unit, configured to perform row disorder on the basic matrix of the LDPC code according to a disorder sequence of the row block for decoding;
the layering unit is used for layering the rows of the disordered basic matrix;
the decoding unit is used for carrying out pipeline decoding on the layered basic matrix;
the second selecting unit is further configured to select a row index number required for decoding from the parent sequence to form a subsequence, which is used as a disorder sequence of the row block for decoding.
5. The apparatus of claim 4, wherein the layering unit is configured to layer the out-of-order rows of the base matrix according to a layer size determined by a hardware parallelism capability.
6. The apparatus according to claim 5, wherein the layering unit is configured to determine a number of row blocks of the check matrix that can be processed in parallel according to the hardware parallelism capability, and layer the row blocks of each out-of-order check matrix according to the number of row blocks of the check matrix that can be processed in parallel, where rows of the base matrix are the row blocks of the check matrix.
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