CN109936371A - Continuous asymptotic buffer formula quantizer and continuous time delta-sigma modulator - Google Patents
Continuous asymptotic buffer formula quantizer and continuous time delta-sigma modulator Download PDFInfo
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Abstract
The invention discloses a continuous asymptotic buffer formula quantizers and continuous time delta-sigma modulator.The continuous asymptotic buffer formula quantizer can generate M high bits as a digital output signal, and generate L low level member to execute noise shaping operations according to the L low level member.Therefore, the continuous asymptotic buffer formula quantizer and the continuous time delta-sigma modulator can reduce the demand of the circuit area of logarithm mode converter, and can reduce critical path delay, to improve efficiency and reduce cost.
Description
Technical field
The present invention relates to quantizers and delta-sigma modulator, especially with respect to the quantizer with noise shaping function
With the delta-sigma modulator using the quantizer.
Background technique
In recent years, this field is for continuous time delta-sigma modulator (continuous-time sigma-delta
Modulator, CTSDM) performance requirement it is higher and higher, therefore, part CTSDM uses more bit numbers (be not less than 4)
Quantizer, however, in the case of the bit number of quantizer is high, the digital analog converter (digital-to-analog of CTSDM
Converter, DAC) in order to meet the requirements the design that (such as: efficiency, cost) is arranged in pairs or groups seem unable to do what one wishes, above-mentioned design
One of e.g. following technology:
One, DAC alignment technique.This technology may have different calibration results, and the school of this technology to the DAC of different chips
Plus effect specific frequency or at a temperature of may be good, but may not under other frequencies or temperature (such as: high frequency or high temperature)
It is good.
Two, DAC is designed to meet the dynamic model of analog-digital converter (analog-to-digital converter, ADC)
Enclose (dynamic range, DR).The area that this technology will lead to DAC is quite big, and then leads to cost increase.
Three, DAC using dynamic element matching (dynamic element matching, DEM) technology (such as: data adds
Weight average (data weighted averaging, DWA) technology).This technology may have critical path delay (critical
Path delay) too long problem, it will affect the loop-delay (excess loop delay) of CTSDM.
Four, digital trigonometric integral cropper (the digital delta-sigma truncator) technology of DAC collocation and choosing
It arranges in pairs or groups to selecting property DEM technology.This technology may have the problem of bulk delay overlong time, will affect the loop-delay of CTSDM.
Related prior art is found in following documents:
One, Chi-Yun Wang, Shu-Wei Chu, Tzu-Hsuin Peng, Jen-Che Tsai, and Chih-Hong
Lou,"A Mode-Configurable Analog Baseband for Wi-Fi 11ac Direct-Conversion
Receiver Utilizing a Single Filtering ADC",2016IEEE Radio Frequency
Integrated Circuits Symposium。
Two, Yonghua Cong, Student Member, IEEE, and Randall L.Geiger, Fellow,
IEEE,"A 1.5-V 14-Bit 100-MSs Self-Calibrated DAC",IEEE JOURNAL OF SOLID-STATE
CIRCUITS, VOL.38, NO.12,2003 December.
Three, John G.Kauffman, Student Member, IEEE, Pascal Witte, Member, IEEE,
Joachim Becker,Member,IEEE,and Maurits Ortmanns,Senior Member,IEEE,"An 8.5mW
Continuous-Time Modulator With 25MHz Bandwidth Using Digital Background DAC
Linearization to Achieve 63.5dB SNDR and 81dB SFDR",John G.Kauffman,Student
Member,IEEE,Pascal Witte,Member,IEEE,Joachim Becker,Member,IEEE,and Maurits
Ortmanns,Senior Member,IEEE。
Four, Hung-Chieh Tsai, Chi-Lun Lo, Chen-Yen Ho, Member, IEEE, and Yu-Hsin
Lin,"A 64-fJ_Conv.-Step Continuous-Time Sigma Delta Modulator in 40-nm CMOS
Using Asynchronous SAR Quantizer and Digital Delta Sigma Truncator",IEEE
JOURNAL OF SOLID-STATE CIRCUITS, VOL.48, NO.11,2013 November.
Five, the United States Patent (USP) of the patent No. 8,928,511.
Summary of the invention
One of present invention be designed to provide a kind of bit removable noise shaping continuously asymptotic buffer formula quantizer with
A kind of continuous time delta-sigma modulator, can take into account efficiency and cost.
The invention discloses a kind of continuous asymptotic buffer formula quantizer of bit removable noise shaping, one embodiment packets
Containing one, continuously the high bit switching circuit of asymptotic buffer formula, a low level member switching circuit, a comparison circuit, a high bit control are electric
Road and a low level member control circuit.The continuous asymptotic high bit switching circuit of buffer formula is used to according to a simulation input
Signal and a first switch control signal, sequentially generate M high bit sampling results, and wherein the M is more than or equal to (not small
In) 1 integer.The low level member switching circuit is used to sequentially produce according to the analog input signal and a second control signal
Raw L low level member sampling result, wherein the L is positive integer.The comparison circuit be used to according to the M high bit sampling results according to
Sequence generates M high bit comparison results, and is used to sequentially generate L low level member according to the L low level member sampling result and compares knot
Fruit.The high bit control circuit is used to generate first switch control signal according to the M high bit comparison results, and is used to
A digital output signal is exported according to the M high bit comparison results.The low level member control circuit is used to according to previous L
Low level member comparison result and the L low level member comparison result, generate the second control signal.
The invention also discloses a kind of continuous time delta-sigma modulator, one embodiment includes a computing circuit, one
Filter circuit, a bit removable noise shaping continuously asymptotic buffer formula quantizer and a digital analog converter.The operation
Circuit is used to generate a signal to be filtered according to an input signal and a feedback signal.The filter circuit is used to be filtered according to this
Wave signal generates a filtering signal.Continuously asymptotic buffer formula quantizer is amount of the invention to the bit removable noise shaping
Change device or its analog, is used to generate a digital output signal according to the filtering signal, wherein the bit removable noise shaping
Continuous asymptotic buffer formula quantizer generates M high bits as the digital output signal, and generating L low level member should with foundation
L low level member executes noise shaping operations, and it is positive integer that wherein the M, which is more than or equal to 1 integer and the L,.The digital-to-analogue
Converter is used to generate the feedback signal according to the digital output signal.
Feature, implementation and effect for the present invention, cooperation schema makees preferred embodiment, and detailed description are as follows.
Detailed description of the invention
[Fig. 1] shows an embodiment of bit removable noise shaping SAR quantizer of the invention；
[Fig. 2] shows an embodiment of the SAR high bit switching circuit of Fig. 1
[Fig. 3] shows an embodiment of the low level member switching circuit of Fig. 1；
[Fig. 4] shows another embodiment of bit removable noise shaping SAR quantizer of the invention；
[Fig. 5] shows an embodiment of continuous time delta-sigma modulator of the invention；
[Fig. 6] shows another embodiment of continuous time delta-sigma modulator of the invention；And
[Fig. 7] shows an embodiment of the dynamic element matching circuit of Fig. 6.
Specific embodiment
The term of following description is the idiom referring to the art, is added as this specification has part term
To illustrate or define, the explanation of the part term is to be subject to the explanation or definition of this specification.
The disclosure includes bit removable noise shaping continuously asymptotic buffer formula quantizer (bit-
Reducing noise-shaping successive approximation register (SAR) quantizer) and it is continuous
Time delta-sigma modulator (continuous-time sigma-delta modulator, CTSDM), can reduce logarithm
The demand of the circuit area of mode converter (DAC), and critical path delay (critical path delay) can be reduced, to mention
It is high-effect and reduce cost.
Fig. 1 shows an embodiment of bit removable noise shaping SAR quantizer of the invention, and it is suitable for single ended inputs
The application of (single-ended input).The bit removable noise shaping SAR quantizer 100 of Fig. 1 includes one continuous asymptotic
Buffer formula (SAR) Gao Weiyuan switching circuit 110, a low level member switching circuit 120, a comparison circuit 130, a high bit control
Circuit 140, a low level member control circuit 150 and a sampling control switch 160.Above-mentioned bit removable noise shaping SAR amount
Change device 100 based on considering for circuit area and power consumption is saved, using SAR framework；However, implementing present inventor can adopt according to its demand
Bit removable noise shaping SAR quantizer 100 is realized with other quantizer framework circuits.Above-mentioned sampling control switch 160
For controlling SAR quantizer 100 to an analog input signal according to a sampling control signal CLKS (such as: a clock signal)
VINThe time being sampled；In other words, sampling control signal CLKS determines bit removable noise shaping SAR quantizer 100
An operation period (or say analog input signal VINOne sampling and quantization the period).
Please refer to Fig. 1.SAR high bit switching circuit 110 is used to according to analog input signal VINAn and first switch control
Signal Ctrl_1 processed generates M high bit sampling results by a predetermined order, and wherein the predetermined order is, for example, and has from a highest
Bit (most significant bit, MSB) (such as: first bit) is imitated toward a least significant bit (least
Significant bit, LSB) at least part of a bit sequence that (such as: (M+L) a bit) successively decreases, which is big
In or equal to 1 integer.One embodiment of SAR high bit switching circuit 110 is as shown in Fig. 2, include a first capacitor circuit 210
With a first switch circuit 220, first capacitor circuit 210 is used to according to analog input signal VINAnd multiple first reference voltages
(such as: a reference voltage and a ground voltage) it is sampled operation and charge redistribution operation, first switch circuit 220
For controlling signal Ctrl_1, control first capacitor circuit 210 and multiple first reference voltage end (examples according to the first switch
Such as: a reference voltage end VREFWith a ground voltage terminal) between connection relationship, wherein multiple first reference voltage end use
To provide multiple first reference voltage.Due to the first capacitor circuit 210 of Fig. 2 and the framework of first switch circuit 220 and behaviour
Make and the capacitor of general SAR analog-digital converter (SAR analog-to-digital converter, SAR ADC) and switch electricity
The framework on road and operation are similar, therefore details is omitted herein.
Please refer to Fig. 1.Low level member switching circuit 120 is used to according to analog input signal VINAn and second control signal
Ctrl_2 generates L low level member sampling result by a predetermined order (such as: at least part of aforementioned bit sequence), wherein
The L is positive integer.It is worth noting that, previous low level member comparison result (such as: SAR quantizer 100 is in previous running
Low level member comparison result caused by period) when not yet generating (such as: in first operation period of SAR quantizer 100),
The previous low level member comparison result is the value of zero or not sampling result for materially affect SAR quantizer 100.Low level member
One embodiment of switching circuit 120 is a SAR low level member switching circuit as shown in figure 3, comprising one second condenser network 310 and one
Second switch circuit 320, the second condenser network 310 are used to according to analog input signal VINAnd multiple second reference voltage (examples
It such as: a reference voltage and a ground voltage) is sampled operation and charge redistribution operation, second switch circuit 320 is used
Come according to the second control signal, and the second condenser network of control 310 and multiple second reference voltage ends (such as: one is positive with reference to electricity
Pressure side 2VREF, a reference voltage end VREFAnd a ground voltage terminal) between connection relationship, wherein multiple second reference
Voltage end is used to provide multiple second reference voltage.It is worth noting that, in an operation period of SAR quantizer 100, figure
2 high bit control circuit 140 controls signal Ctrl_1 by first switch, at the beginning by the every of first switch circuit 220
One switch be connected to one of multiple first reference voltage end (such as: aforementioned reference voltage end VREF), foundation again later
Aftermentioned high bit comparison result come determine the connection between first switch circuit 220 and multiple first reference voltage end close
System, however, the low level member control circuit 150 of Fig. 3 is opened by second control signal Ctrl_2 one within the same cycle of operation
Begin to determine the company between second switch circuit 320 and multiple second reference voltage end according to previous low level member comparison result
Connect relationship (such as: when previous low level member comparison result according to aforementioned predetermined order be 11 ... when 0, second switch circuit 320
Switch is respectively connected to above-mentioned reference voltage end 2V according to the predetermined orderREF, above-mentioned reference voltage end 2VREF..., Yi Jishang
State ground voltage terminal；When previous low level member comparison result is 1 according to aforementioned predetermined order ... when 01, second switch circuit 320
Switch is respectively connected to reference voltage end 2V according to the predetermined orderREF, the ground voltage terminal and the reference voltage end
2VREF；More examples can and so on), determine second switch circuit 320 according to aftermentioned low level member comparison result again later
With the coupling relationship between multiple second reference voltage end.
It is worth noting that, the SAR low level member of Fig. 3 is cut in the case of being able to reflect previous low level member comparison result
Change circuit 120 capacitor array and reference voltage design (such as: the number and capacitance of capacitor and the number of reference voltage
Mesh and voltage value) and its control logic can elasticity adjust, for example, the second reference voltage end of Fig. 3 may be implemented in than
Compared with device negative terminal, at this point, the low level member control circuit 150 is by known or independently developed technology, by the previous low level member ratio
Relatively result is converted to comparison circuit 130 of the comparator input voltage (being contained in the second control signal Ctrl_2) as Fig. 3
The received input voltage V of instituteCOMP, which can be related with the previous low level member comparison result, and SAR is low
The operation of bit switching circuit 120 can be similar with the operation of general SARADC.Separately it is worth noting that, low level member switching circuit
120 are also possible to the circuit of other forms, as long as the circuit can reflect previous low level member comparison result and to current
Analog input signal VINIt is sampled to generate current low level member sampling result.
Please refer to Fig. 1.Comparison circuit 130 is used to according to input voltage VCOMP(such as: ground voltage or aforementioned comparator are defeated
Enter voltage) and the M high bit sampling results sequentially generate M high bit comparison results, and be used to according to input voltage VCOMP
And the L low level member sampling result sequentially generates L low level member comparison result.High bit control circuit 140 is used to according to the
One control logic (such as: control logic of the general SAR ADC for switching circuit) and the M high bit comparison results generation
The first switch controls signal, and is used to export a digital output signal D according to the M high bit comparison resultsOUT, non-one
In restrictive embodiment, digital output signal DOUTBit number be equal to the M；In another unrestricted embodiment,
Digital output signal DOUTBit number be greater than or equal to 1.Low level member control circuit 150 is used to according to the second control logic (example
Such as: in preceding description, controlling the logic of second switch circuit 320), L previous low level member comparison result and the L are a low
Bit comparison result generates the second control signal, which can change according to the implementation of low level member switching circuit 120
Selectively comprising switch control signal (such as: the signal of the second switch circuit 320 of control figure 3), voltage signal (such as:
Aforementioned comparator input voltage) etc..The framework of above-mentioned comparison circuit 130 and operation and the comparison circuit of general SAR ADC
Framework is impartial with similar or function is operated, therefore details is omitted herein.Above-mentioned high bit control circuit 140 and low level member control circuit
150 framework is impartial with similar or function is operated with operation with the framework of the control circuit of general SAR ADC, therefore details saves herein
Slightly.
Fig. 4 shows another embodiment of bit removable noise shaping SAR quantizer of the invention, and it is suitable for differential defeated
Enter the application of (differential input).The bit removable noise shaping SAR quantizer 400 of Fig. 4 includes two continuous
Asymptotic buffer formula (SAR) Gao Weiyuan switching circuit 410 (that is, two SAR high bit switching circuits 410 are a SAR high positions
Two sub-circuits that first switching circuit is included), two low level member switching circuits 420 (that is, two low level member switching circuits
420 be two sub-circuits that a low level member switching circuit is included), a comparison circuit 430, a high bit control circuit 440 with
An and low level member control circuit 450.One embodiment of each high bit switching circuit 410 is aforementioned high bit switching circuit 110.
Each low level member switching circuit 420 is aforementioned low level member switching circuit 120.Comparison circuit 430 is distinguished by two input terminals
Receive the positive end signal V of differential inputIN(P)Sampling result and differential input negative terminal signal VIN(N)Sampling result, and can
Depending on implementation demand selectively include more input terminals receive converted as previous low level member comparison result obtained by compare
Compared with device input signal, then it is pocessed.Due to the common knowledge that the principle of single ended input and differential input is this field, therefore ability
Domain tool usually intellectual is capable of the disclosure of embodiment referring to figs. 1 to Fig. 3 to understand the implementation detail and change of the embodiment of Fig. 4
Change, in other words, therefore the technical characteristic of the embodiment of Fig. 1 to Fig. 3, can repeat and superfluous rationally applied in the embodiment of Fig. 4
Remaining explanation is in this memorandum.
Fig. 5 shows continuous time delta-sigma modulator (continuous-time sigma-delta of the invention
Modulator, CTSDM) an embodiment.The CTSDM 500 of Fig. 5 includes a computing circuit 510, a filter 520, a bit
Removable noise shaping SAR quantizer 530 and a digital analog converter (digital-to-analog converter, DAC)
540.Computing circuit 510 is used to according to an input signal VINPUTWith a feedback signal VFGenerate a signal V to be filteredSUB, citing and
Speech, computing circuit 510 is a subtracter or it is impartial, is used to input signal VINPUTSubtract feedback signal VFIt is to be filtered to generate
Signal VSUB.Filter 520 is used to according to signal V to be filteredSUBGenerate a filtering signal VH(S), for example, filter 520 is
One integrator is used to according to signal V to be filteredSUBGenerate filtering signal VH(S).Noise shaping SAR quantizer 530 is above-mentioned makes an uproar
Sound shaping SAR quantizer 100 or its analog are used to according to filtering signal VH(S)Generate a digital output signal DOUT, wherein making an uproar
Sound shaping SAR quantizer 530 is according to filtering signal VH(S)It generates M high bits (M bits) and is used as digital output signal DOUT,
And according to filtering signal VH(S)L low level member is generated to execute noise shaping operations according to the L low level member, therefore reduces the L
The problem of loop-delay (excess loop delay) caused by a low level member.DAC 540 is used to according to digital output signal
DOUTGenerate feedback signal VF.Belong to this field for either one or two of above-mentioned computing circuit 510, filter 520 and DAC 540 are independent
Well-known technique, the details of which omits herein.
In order to avoid the area of DAC 540 excessive under the premise of meeting efficiency, CTSDM of the invention can be used further
Dynamic element matching (dynamic element matching, DEM) technology.Fig. 6 shows another implementation of CTSDM of the invention
Example, the CTSDM 600 of Fig. 6 further include a DEM circuit 610, are coupled to noise shaping SAR quantizer 530 and DAC 540
Between, it is used to according to digital output signal DOUTGenerate a digital input signals DIN, DAC 540 is again according to digital input signals DIN
Generate feedback signal VF.Above-mentioned DEM circuit 610 belongs to techniques known, therefore its details is omitted herein.
In addition, in order to avoid digital output signal DOUTAll bits via DEM circuit 610 handle and lead to CTSDM
600 loop-delay (excess loop delay) is too long, as shown in fig. 7, DEM circuit 610 can only handle digital output signal
DOUTB high bit (B bit (s)) (i.e. digital output signal DOUTMSB and (B-1) a bit after it), with output
The digital input signals D handled through DEMINA part to DAC 540, DEM circuit 610 is separately by digital output signal DOUTQ
Low level member (Q bit (s)) (i.e. digital output signal DOUTLSB and it before (Q-1) a bit) be directly output to DAC
540, which, without DEM processing, is as digital input signals DINOther parts, wherein the B and Q is positive
Integer, and the B is with the Q's and equal to the M.The technology of above-mentioned DEM circuit 610 can be described as the randomization that the high bit of DAC limits
Technology (DAC MSB-only Randomization).
Since one skilled in the art can understand Fig. 5 to Fig. 7 referring to figs. 1 to the disclosure of the embodiment of Fig. 4
Embodiment implementation detail and variation, in other words, the technical characteristic of the embodiment of Fig. 1 to Fig. 4 can rationally be applied to Fig. 5 extremely
In the embodiment of Fig. 7, therefore, repeats and the explanation of redundancy is in this memorandum.
It note that under the premise of being embodied as possible, before the art tool usually intellectual optionally implements
Part or all technical features in any embodiment are stated, or selectively implement part or all of technology in aforesaid plurality of embodiment
The combination of feature increases the elasticity when present invention is implemented whereby.
In conclusion bit removable noise shaping SAR quantizer of the invention is exported according to high bit comparison result
Digital output signal, therefore, the conversion of SAR ADC involved in bit removable noise shaping SAR quantizer of the invention prolong
Late only include the transfer lag of high bit, but do not include the transfer lag of low level member, therefore bit removable noise of the invention is whole
Shape SAR quantizer can reach preferable efficiency.In addition, CTSDM of the invention, which is removed, can be used bit removable noise of the invention
Shaping SAR quantizer is to reach outside better performance, and the randomized technique that the high bit that DAC can be used limits, to reduce to DAC
Circuit area demand, and critical path delay caused by DEM technology is reduced, to improve efficiency and reduce cost.
Although the embodiment of the present invention is as described above, however those embodiments not are used to limit the present invention, this technology neck
The domain tool usually intellectual content that can express or imply according to the present invention imposes variation to technical characteristic of the invention, it is all this
Many variations may belong to patent protection scope sought by the present invention, and in other words, scope of patent protection of the invention must regard
Subject to the as defined in claim of this specification.
Symbol description
The continuous asymptotic buffer formula quantizer of 100 bit removable noise shapings
The 110 continuous asymptotic high bit switching circuits of buffer formula (SAR high bit switching circuit)
120 low level member switching circuits
130 comparison circuits
140 high bit control circuits
150 low level member control circuits
160 sampling control switches
CLKS sampling control signal
VINAnalog input signal
VCOMPInput voltage
DOUTDigital output signal
Ctrl_1 first switch controls signal
Ctrl_2 second control signal
210 first capacitor circuits
220 first switch circuits
VREFReference voltage end
310 second condenser networks
320 second switch circuits
2VREFReference voltage end
The continuous asymptotic buffer formula quantizer of 400 bit removable noise shapings
The 410 continuous asymptotic high bit switching circuits of buffer formula (SAR high bit switching circuit)
420 low level member switching circuits
430 comparison circuits
440 high bit control circuits
450 low level member control circuits
VIN(P)The positive end signal of differential input
VIN(N)The negative terminal signal of differential input
500 continuous time delta-sigma modulators
510 computing circuits
520 filters
Continuous asymptotic buffer formula quantizer (the bit removable noise shaping SAR amount of 530 bit removable noise shapings
Change device)
540 digital analog converters (DAC)
VINPUTInput signal
VFFeedback signal
VSUBSignal to be filtered
VH(S)Filtering signal
M bit of M bits digital output signal
600 continuous time delta-sigma modulators
610 dynamic element matching circuits (DEM)
DINDigital input signals
B high bits of B bit (s)
Q bit (s) Q low level member.
Claims (10)
1. a kind of continuous asymptotic buffer formula quantizer, includes:
The one continuous asymptotic high bit switching circuit of buffer formula is used to control according to an analog input signal and a first switch
Signal sequentially generates M high bit sampling results, and wherein the M is the integer more than or equal to 1；
One low level member switching circuit is used to sequentially generate L low level according to the analog input signal and a second control signal
First sampling result, wherein the L is positive integer；
One comparison circuit, for sequentially generating M high bit comparison results according to the M high bit sampling results, and be used to according to
L low level member comparison result is sequentially generated according to the L low level member sampling result；
One high bit control circuit for generating first switch control signal according to the M high bit comparison results, and is used to
A digital output signal is exported according to the M high bit comparison results；And
One low level member control circuit, for according to previous L low level member comparison result and the L low level member comparison result,
Generate the second control signal.
2. continuous asymptotic buffer formula quantizer as described in claim 1, wherein the bit number of the digital output signal is equal to
The M.
3. continuous asymptotic buffer formula quantizer as described in claim 1, wherein the continuous asymptotic high bit of buffer formula is cut
Changing circuit includes:
One first capacitor circuit, for being sampled operation and charge according to the analog input signal and multiple reference voltages
Operation is reassigned, to generate the M high bit sampling results；And
One first switch circuit is used to control signal according to the first switch, controls the first capacitor circuit and multiple with reference to electricity
Connection relationship between pressure side, wherein multiple reference voltage end is used to provide multiple reference voltage.
4. asymptotic buffer formula quantizer as claimed in claim 3 continuous, wherein the low level member switching circuit includes:
One second condenser network, for being sampled operation and charge according to the analog input signal and multiple reference voltages
Operation is reassigned, to generate the L low level member sampling result；And
One second switch circuit is used to control second condenser network and multiple reference voltage ends according to the second control signal
Between connection relationship, wherein multiple reference voltage end be used to multiple reference voltage is provided.
5. continuous asymptotic buffer formula quantizer as claimed in claim 4, wherein one in the analog input signal takes at present
Sample and in the quantization period, controls the second switch circuit by the second control signal, second condenser network and multiple ginseng
Examining the initial connection relationship between voltage end is to depend upon the L previous low level member comparison result.
6. asymptotic buffer formula quantizer as described in claim 1 continuous, wherein the low level member switching circuit includes:
One second condenser network, for being sampled operation and charge according to the analog input signal and multiple reference voltages
Operation is reassigned, to generate the L low level member sampling result；And
One second switch circuit is used to control second condenser network and multiple reference voltage ends according to the second control signal
Between connection relationship, wherein multiple reference voltage end be used to multiple reference voltage is provided.
7. continuous asymptotic buffer formula quantizer as claimed in claim 6, wherein one in the analog input signal takes at present
Sample and in the quantization period, controls the second switch circuit by the second control signal, second condenser network and multiple ginseng
Examining the initial connection relationship between voltage end is to depend upon the L previous low level member comparison result.
8. a kind of continuous time delta-sigma modulator, includes:
One computing circuit is used to generate a signal to be filtered according to an input signal and a feedback signal；
One filter circuit is used to generate a filtering signal according to the signal to be filtered；
The continuous asymptotic buffer formula quantizer of one bit removable noise shaping is used to generate a number according to the filtering signal defeated
Signal out, wherein continuously asymptotic buffer formula quantizer generates M high bits as the number to the bit removable noise shaping
Output signal, and generate L low level member to execute noise shaping operations according to L low level member, wherein the M be more than or equal to
1 integer and the L are positive integer；And
One digital analog converter, for generating the feedback signal according to the digital output signal.
9. continuous time delta-sigma modulator as claimed in claim 8, further includes:
One dynamic element matching circuit is coupled to the bit removable noise shaping continuously asymptotic buffer formula quantizer and the number
Between mode converter, it is used to generate a digital input signals according to the digital output signal,
Wherein the digital analog converter generates the feedback signal according to the digital input signals.
10. continuous time delta-sigma modulator as claimed in claim 9, wherein digital output signal includes B high bits
With Q low level member, which exports a part of the digital input signals according to the B high bits, and straight
Connect and export the other parts of the Q low level member as the digital input signals, wherein the B and the Q are positive integer, and the B and
The Q's and be equal to the M.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201711372526.2A CN109936371B (en) | 2017-12-19 | 2017-12-19 | Continuous asymptotic register type quantizer and continuous time delta-sigma modulator |
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| CN201711372526.2A CN109936371B (en) | 2017-12-19 | 2017-12-19 | Continuous asymptotic register type quantizer and continuous time delta-sigma modulator |
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| CN109936371A true CN109936371A (en) | 2019-06-25 |
| CN109936371B CN109936371B (en) | 2023-05-12 |
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| CN201711372526.2A Active CN109936371B (en) | 2017-12-19 | 2017-12-19 | Continuous asymptotic register type quantizer and continuous time delta-sigma modulator |
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| US20160126967A1 (en) * | 2014-11-05 | 2016-05-05 | Seung-Hyun OH | Apparatus and method for analog-digital converting |
| US9455737B1 (en) * | 2015-09-25 | 2016-09-27 | Qualcomm Incorporated | Delta-sigma analog-to-digital converter (ADC) with time-interleaved (TI) or two-step successive approximation register (SAR) quantizer |
| CN106055307A (en) * | 2016-05-23 | 2016-10-26 | 深圳华视微电子有限公司 | Random number generator |
| US20170250702A1 (en) * | 2015-07-08 | 2017-08-31 | Marvell World Trade Ltd. | Charge-sharing and charge-redistribution dac and method for successive approximation analog-to-digital converters |
| CN107465411A (en) * | 2016-06-03 | 2017-12-12 | 联发科技股份有限公司 | Quantizer |
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20160126967A1 (en) * | 2014-11-05 | 2016-05-05 | Seung-Hyun OH | Apparatus and method for analog-digital converting |
| US20170250702A1 (en) * | 2015-07-08 | 2017-08-31 | Marvell World Trade Ltd. | Charge-sharing and charge-redistribution dac and method for successive approximation analog-to-digital converters |
| US9455737B1 (en) * | 2015-09-25 | 2016-09-27 | Qualcomm Incorporated | Delta-sigma analog-to-digital converter (ADC) with time-interleaved (TI) or two-step successive approximation register (SAR) quantizer |
| CN106055307A (en) * | 2016-05-23 | 2016-10-26 | 深圳华视微电子有限公司 | Random number generator |
| CN107465411A (en) * | 2016-06-03 | 2017-12-12 | 联发科技股份有限公司 | Quantizer |
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