CN109935596A - 3D memory device and its manufacturing method - Google Patents
3D memory device and its manufacturing method Download PDFInfo
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- CN109935596A CN109935596A CN201910247962.XA CN201910247962A CN109935596A CN 109935596 A CN109935596 A CN 109935596A CN 201910247962 A CN201910247962 A CN 201910247962A CN 109935596 A CN109935596 A CN 109935596A
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Abstract
This application discloses a kind of 3D memory device and its manufacturing methods.The 3D memory device includes: semiconductor substrate；Array structure is located at semiconductor lining, including rhythmic structure of the fence；Multiple channel columns run through rhythmic structure of the fence, and contact with semiconductor substrate；Conductive channel runs through rhythmic structure of the fence, and contacts with semiconductor substrate；And sealing ring, it is extended in semiconductor substrate from array structure surface, and surround rhythmic structure of the fence, wherein, conductive channel includes the first conductive structure being filled in the first deep trouth, sealing ring includes the second conductive structure being filled in the second deep trouth, and the first deep trouth and the second deep trouth are formed by synchronous process.The 3D memory device forms the first deep trouth and the second deep trouth by synchronous process, avoids the problem that deep-hole etching process and deep etching technique cannot be compatible.
Description
Technical field
The present invention relates to memory technologies, more particularly, to a kind of 3D memory device and its manufacturing method.
Background technique
The raising of the storage density of memory device and the progress of semiconductor fabrication process are closely related.With semiconductors manufacture
The characteristic size of technique is smaller and smaller, and the storage density of memory device is higher and higher.In order to further increase storage density,
Develop the memory device (that is, 3D memory device) of three-dimensional structure.3D memory device includes along the multiple of vertical direction stacking
Storage unit can double up integrated level on the chip of unit area, and can reduce cost.
3D memory device provides the grid conductor of selection transistor and memory transistor using laminated construction, using channel column
The channel layer and gate medium lamination of selection transistor and memory transistor are provided, realized using the conductive channel through laminated construction
Array common source realizes that conductive channel, channel column and semiconductor substrate and external circuit connect using multiple electric connection structures respectively
It connects, the stress generated in encapsulation process using sealing ring (Seal Ring, SR) release, barrier 3D memory device, and obstructs 3D
Steam of the memory device when manufacture, using, to keep the reliability of 3D memory device.
In the prior art, sealing ring is extended in semiconductor substrate using deep trouth technique from array structure surface, and is used
In the electric connection structure of connection semiconductor substrate and external circuit using the manufacture of deep hole technique, sealing ring and electric connection structure exist
It is collectively formed in identical processing step, however, the number of plies with laminated construction is more and more, deep-hole etching process and deep trouth are carved
Etching technique cannot be compatible with, and the function of sealing ring is caused not to be able to satisfy the demand of 3D memory device.
In addition, the prior art is by physical vapour deposition (PVD) (Physical Vapor Deposition, PVD) technique in depth
The sealing ring that deposited metal tungsten is formed in slot, can make fluorine element content in 3D memory device excessively high (F rich), thus after interference
Continuous technique, causes to 3D out of memory.
Summary of the invention
The object of the present invention is to provide a kind of improved 3D memory device and its manufacturing method, the is formed by synchronous process
One deep trouth and the second deep trouth avoid the problem that deep-hole etching process and deep etching technique cannot be compatible.
According to an aspect of the present invention, a kind of 3D memory device is provided, comprising: semiconductor substrate；Array structure is located at institute
State semiconductor lining, including rhythmic structure of the fence；Multiple channel columns, run through the rhythmic structure of the fence, and with the semiconductor substrate
Contact；Conductive channel runs through the rhythmic structure of the fence, and contacts with the semiconductor substrate；And sealing ring, from the array
Body structure surface extends in the semiconductor substrate, and surrounds the rhythmic structure of the fence, wherein the conductive channel includes filling
The first conductive structure in the first deep trouth, the sealing ring includes the second conductive structure being filled in the second deep trouth, described
First deep trouth and second deep trouth are formed by synchronous process.
Preferably, first conductive structure includes the first core and the first conductive layer for surrounding first core, institute
State the conductive layer that the second conductive structure includes the second core with surrounds second core, wherein first conductive structure with
Second conductive structure is formed by synchronous process.
Preferably, the array structure further includes oxide layer, surrounds and covers the rhythmic structure of the fence, wherein described close
Seal ring extends in the semiconductor substrate from the oxidation layer surface.
Preferably, further include multiple first electric connection structures, extend through the part oxide layer and the multiple channel
Column electrical connection.
It preferably, further include multiple second electric connection structures, positioned at the two sides of the rhythmic structure of the fence, from the oxide layer
Surface extends in the semiconductor substrate.
Preferably, the sealing ring surrounds the multiple second electric connection structure.
Preferably, further includes: multiple third electric connection structures, oxide layer described in through part are electrically connected with the conductive channel
It connects；And the 4th electric connection structure, oxide layer described in through part are electrically connected with the sealing ring, wherein the multiple third
Electric connection structure is formed with the 4th electric connection structure by synchronous process.
Preferably, further include multiple separation layers, be located between the conductive channel and the rhythmic structure of the fence and
Between the sealing ring and the oxide layer.
Preferably, first core, second core material include the combination of tungsten or tungsten and polysilicon.
Preferably, first conductive layer, second conductive layer material include titanium and/or titanium nitride.
According to another aspect of the present invention, a kind of method for manufacturing 3D memory device is provided, comprising: on a semiconductor substrate
Form array structure, including rhythmic structure of the fence；Multiple channel columns are formed through the rhythmic structure of the fence, with the semiconductor substrate
Contact；Conductive channel is formed through the rhythmic structure of the fence, is contacted with the semiconductor substrate；And from the array structure table
Face, which extends in the semiconductor substrate, forms sealing ring, and the sealing ring surrounds the rhythmic structure of the fence, wherein the conduction
Channel includes the first conductive structure being filled in the first deep trouth, and the sealing ring includes that second be filled in the second deep trouth is led
Electric structure, first deep trouth and second deep trouth are formed by synchronous process.
Preferably, the array structure further includes oxide layer, surrounds and covers the rhythmic structure of the fence, wherein described close
Seal ring extends in the semiconductor substrate from the oxidation layer surface.
Preferably, the step of forming the conductive channel includes: to extend to described partly to lead from the rhythmic structure of the fence surface
First deep trouth is formed in body substrate；And first conductive structure is filled in first deep trouth, described first leads
Electric structure includes the first core and the first conductive layer for surrounding first core.
Preferably, the step of forming the sealing ring includes: to extend to the semiconductor substrate from the oxidation layer surface
The second deep trouth of middle formation, second deep trouth surround the rhythmic structure of the fence；And described is filled in second deep trouth
Two conductive structures, second conductive structure include the second core and the second conductive layer for surrounding second core, wherein institute
It states the first conductive structure and is formed with second conductive structure by synchronous process.
Preferably, the manufacturing method of the 3D memory device further include: through the oxide layer in the multiple channel column
On be respectively formed contact hole；And filling conductive material forms the first electric connection structure, first electricity in the contact hole
Connection structure is electrically connected with the channel column.
Preferably, the manufacturing method of the 3D memory device further include: in the rhythmic structure of the fence two sides from the oxidation
Layer surface, which extends in the semiconductor substrate, forms multiple contact holes；And filling conductive material is formed in the contact hole
Second electric connection structure, second electric connection structure are electrically connected with the semiconductor substrate, wherein the sealing ring surrounds institute
State multiple second electric connection structures.
Preferably, the manufacturing method of the 3D memory device further include: through the oxide layer the conductive channel with
Contact hole is respectively formed on the sealing ring；And it is respectively formed and the conductive channel in contact hole filling conductive material
The third electric connection structure of electrical connection and the 4th electric connection structure being electrically connected with the sealing ring, wherein the multiple
Three electric connection structures are formed in synchronous process with the 4th electric connection structure.
Preferably, the manufacturing method of the 3D memory device further includes forming multiple separation layers, the multiple separation layer point
Not between the conductive channel and the rhythmic structure of the fence and between the sealing ring and the oxide layer.
Preferably, first core, second core material include the combination of tungsten or tungsten and polysilicon.
Preferably, first conductive layer, second conductive layer material include titanium and/or titanium nitride.
3D memory device according to an embodiment of the present invention and its manufacturing method, by the sealing for surrounding the rhythmic structure of the fence
Ring has completely cut off steam, has obstructed stress, to achieve the purpose that protect 3D memory device, compared with prior art, in the present invention
In the 3D memory device of embodiment, the first deep trouth and the second deep trouth are formed by synchronous process, and respectively in the first deep trouth
It fills the first conductive structure and forms conductive channel, the second conductive structure is filled in the second deep trouth and forms sealing ring, due to conduction
Channel and sealing ring are all made of deep trouth technique, and the compatibility of the two is more preferable, avoid deep-hole etching process and deep etching technique
The problem that cannot be compatible with.
3D memory device according to an embodiment of the present invention and its manufacturing method, sealing ring is including the first core and around first
First conductive layer of core, the electric conductivity of sealing ring is increased by the first conductive layer, further improves 3D memory device
Performance.
In addition, the sealing ring of the embodiment of the present invention includes the first core and the first conductive layer for surrounding the first core, instead of
The scheme for forming sealing ring by tungsten completely in the prior art, avoids the excessively high problem of fluorine element content in device.
Detailed description of the invention
By referring to the drawings to the description of the embodiment of the present invention, above-mentioned and other purposes of the invention, feature and
Advantage will be apparent from.
The equivalent circuit diagram and structural schematic diagram of the memory cell string of 3D memory device is shown respectively in Fig. 1 a and 1b.
Fig. 2 a shows 3D memory device top view according to an embodiment of the present invention.
Fig. 2 b shows the sectional view in a according to fig. 2 along line A-A.
Fig. 3 to Figure 12 shows the sectional view in each stage of 3D memory device manufacturing method according to an embodiment of the present invention.
Figure 13 to 14b shows the effect analysis schematic diagram of 3D memory device according to an embodiment of the present invention.
Specific embodiment
Hereinafter reference will be made to the drawings, and the present invention will be described in more detail.In various figures, identical element is using similar attached
Icon is remembered to indicate.For the sake of clarity, the various pieces in attached drawing are not necessarily to scale.Furthermore, it is possible to be not shown certain
Well known part.For brevity, the semiconductor structure obtained after several steps can be described in a width figure.
It should be appreciated that being known as being located at another floor, another area when by a floor, a region in the structure of outlines device
When domain " above " or " top ", can refer to above another layer, another region, or its with another layer, it is another
Also comprising other layers or region between a region.Also, if device overturn, this layer, a region will be located at it is another
Layer, another region " following " or " lower section ".
If will use " directly exist ... herein to describe located immediately at another layer, another region above scenario
Above " or " ... abut above and therewith " form of presentation.
Many specific details of the invention, such as structure, material, size, the processing work of device is described hereinafter
Skill and technology, to be more clearly understood that the present invention.But it just as the skilled person will understand, can not press
The present invention is realized according to these specific details.
The present invention can be presented in a variety of manners, some of them example explained below.
The circuit diagram and structural schematic diagram of the memory cell string of 3D memory device is shown respectively in Fig. 1 a and 1b.In the embodiment
Shown in memory cell string include 4 storage units situation.It is appreciated that the invention is not limited thereto, in memory cell string
Number of memory cells can be to be any number of, for example, 32 or 64.
As shown in Figure 1a, the first end of memory cell string 100 is connected to bit line (Bit-Line, BL), and second end is connected to
Source electrode line (Source Line, SL).Memory cell string 100 includes the multiple crystalline substances being connected in series between the first end and a second end
Body pipe, comprising: first choice transistor Q1, memory transistor M1 to M4 and the second selection transistor Q2.First choice crystal
The grid of pipe Q1 is connected to string selection line (Selection Gate for Drain, SGD), the grid of the second selection transistor Q2
It is connected to source selection line (Selection Gate for Source, SGS).The grid of memory transistor M1 to M4 is separately connected
To the respective word of wordline (Word-Line) WL1 to WL4.
As shown in Figure 1 b, the selection transistor Q1 and Q2 of memory cell string 100 respectively include gate conductor layer 122 and 123,
Memory transistor M1 to M4 respectively includes gate conductor layer 121.In gate conductor layer 121,122 and 123 and memory cell string 100
Transistor stacking order it is consistent, separated each other using interlayer insulating film between adjacent gate conductor layer, to form grid
Laminated construction.Further, memory cell string 100 includes channel column 110.Channel column 110 is adjacent with rhythmic structure of the fence or passes through
Wear rhythmic structure of the fence.In the middle section of channel column 110, tunneling medium layer is accompanied between gate conductor layer 121 and channel layer 111
112, charge storage layer 113 and gate dielectric layer 114, to form memory transistor M1 to M4.At the both ends of channel column 110, grid
Gate dielectric layer 114 is accompanied between pole conductor layer 122 and 123 and channel layer 111, to form selection transistor Q1 and Q2.
In this embodiment, channel layer 111 is for example made of polysilicon, and tunneling medium layer 112 and gate dielectric layer 114 are distinguished
It is made of oxide, such as silica, charge storage layer 113 is made of the insulating layer comprising quantum dot or nanocrystal, example
The silicon nitride of particle such as comprising metal or semiconductor, gate conductor layer 121,122 and 123 is made of metal, such as tungsten.Ditch
Channel layer 111 is used to provide control selection transistor and control the channel region of transistor, the doping type and selection crystal of channel layer 111
It manages identical with the type of control transistor.For example, the selection transistor and control transistor, channel layer 111 for N-type can be
The polysilicon of n-type doping.
In this embodiment, the core of channel column 110 is channel layer 111, tunneling medium layer 112,113 and of charge storage layer
Gate dielectric layer 114 forms the laminated construction for surrounding core wall.In alternate embodiments, the core of channel column 110 is additional
Insulating layer, channel layer 111, tunneling medium layer 112, charge storage layer 113 and gate dielectric layer 114 are formed around around core wall
Laminated construction.
In this embodiment, selection transistor Q1 and Q2, memory transistor M1 to M4 use public channel layer 111 and grid
Dielectric layer 114.In channel column 110, channel layer 111 provides the source-drain area and channel layer of multiple transistors.In the implementation of substitution
Example in, can use step independent of one another, be respectively formed selection transistor Q1 and Q2 semiconductor layer and gate dielectric layer and
The semiconductor layer and gate dielectric layer of memory transistor M1 to M4.In channel column 110, the semiconductor layer of selection transistor Q1 and Q2
It is electrically connected to each other with the semiconductor layer of memory transistor M1 to M4.
In write operation, memory cell string 100 writes data into memory transistor M1 into M4 using FN tunneling effect
Selected memory transistor.By taking memory transistor M2 as an example, while source electrode line SL ground connection, source selection line SGS is biased to greatly
About zero volts, so that the selection transistor Q2 corresponding to source selection line SGS is disconnected, string selection line SGD is biased to high voltage
VDD, so that corresponding to the selection transistor Q1 conducting of string selection line SGD.Further, bit line BL is grounded, and wordline WL2 is offset to
Program voltage VPG, such as 20V or so, remaining wordline are offset to low-voltage VPS1.Due to the word of only selected memory transistor M2
Line voltage is higher than tunneling voltage, and therefore, the electronics of the channel region of memory transistor M2 reaches charge via tunneling medium layer 112
Accumulation layer 113, so that data are transformed into charge storage in the charge storage layer 113 of memory transistor M2.
In read operation, selected memory transistor of the memory cell string 100 according to memory transistor M1 into M4 is led
Logical state judges the quantity of electric charge in charge storage layer, to obtain the data of quantity of electric charge characterization.By taking memory transistor M2 as an example,
Wordline WL2, which is offset to, reads voltage VRD, remaining wordline is offset to high voltage VPS2.The on state of memory transistor M2 and its
Threshold voltage is related, i.e., related to the quantity of electric charge in charge storage layer, thus can be with according to the on state of memory transistor M2
Judge data value.Memory transistor M1, M3 and M4 are in the conductive state always, and therefore, the on state of memory cell string 100 takes
Certainly in the on state of memory transistor M2.Control circuit is according to the electric signal judgement storage detected on bit line BL and source electrode line SL
The on state of transistor M2, to obtain the data stored in memory transistor M2.
Fig. 2 a shows 3D memory device top view according to an embodiment of the present invention, and Fig. 2 b is shown in a according to fig. 2 along line A-A
Sectional view.For the sake of clarity, the oxide layer covering parts such as sealing ring and rhythmic structure of the fence are not shown in Fig. 2 a.
As shown in Fig. 2 a and Fig. 2 b, 3D memory device shown in the present embodiment include: semiconductor substrate 101, it is multiple every
Absciss layer 103, array structure, multiple channel columns 110, multiple conductive channels 130, sealing ring 140, multiple first electric connection structures
150, multiple second electric connection structures 160 and multiple third electric connection structures 170 and multiple 4th electric connection structures 180.
Array structure is located in semiconductor substrate 101, including rhythmic structure of the fence 120 and oxide layer 102, oxide layer 102 are enclosed
Around and cover rhythmic structure of the fence 120.Wherein, rhythmic structure of the fence 120 includes alternate multiple 121,122,123 and of gate conductor layer
Multiple interlayer insulating films 191.Wherein, the material of gate conductor layer 121,122,123 includes but is not limited to tungsten, oxide layer
102 and the material of interlayer insulating film 191 include but is not limited to silica.
Multiple channel columns 110 run through rhythmic structure of the fence 120, and contact with semiconductor substrate 101, the inside of channel column 110
Structure is as shown in Figure 1 b, and details are not described herein again.Memory cell string respectively include part corresponding to respective channel column 110 and
Public gate conductor layer 121,122 and 123.The heap of transistor in gate conductor layer 121,122 and 123 and memory cell string
Sequence consensus is folded, is separated each other using interlayer insulating film 191 between adjacent gate conductor layer, to form rhythmic structure of the fence
120。
Conductive channel 130 connects between multiple channel columns 110 through rhythmic structure of the fence 120 and with semiconductor substrate 101
Touching.Conductive channel 130 includes the first conductive structure that the first core is formed with the first conductive layer 131 around the first core, and
And first conductive structure be filled in the first deep trouth, wherein the first part 132a of the first core is located under conductive channel 130
Portion, the second part 132b of the first core are located at the top of conductive channel 130, the first part 132a of the first core and first
The first conductive layer 131 is spaced between the end for dividing 132b adjacent.
In the present embodiment, the material of the first conductive layer 131 includes titanium nitride and/or titanium, the first part of the first core
The material of 132a includes polysilicon, and the material of the second part 132b of the first core includes tungsten.Conductive channel 130 is led by first
The first part 132a of electric layer 131 and the first core realizes the electric connection with semiconductor substrate 101.
140 autoxidation layer of sealing ring, 102 surface extends in semiconductor substrate 101, and surrounds rhythmic structure of the fence 120.It is close
Seal ring 140 includes the second conductive structure that the second core is formed with the second conductive layer 141 around the second core, and second leads
Electric structure filling is in the second deep trouth, wherein the first part 142a of the second core is located at the lower part of sealing ring 140, the second core
The second part 142b in portion is located at the top of sealing ring 140, and the first part 142a of the second core is adjacent with second part 142b
End between be spaced the second conductive layer 141.
In the present embodiment, the material of the second conductive layer 141 includes titanium nitride and/or titanium, the first part of the second core
The material of 142a includes tungsten, and the material of the second part 142b of the second core includes polysilicon, and sealing ring 140 passes through second
The first part 142a of conductive layer 141 and the first core realizes the electric connection with semiconductor substrate 101.
First deep trouth and the second deep trouth are formed by synchronous process, and the first conductive structure with the second conductive structure by synchronous
Technique is formed, and therefore, conductive channel 130 and the internal structure of sealing ring 140, material are all the same, in some other embodiments,
First core is deposited to be formed by tungsten with the second core, and conductive channel 130 is real by the first conductive layer 131 and the first core
Now with the electric connection of semiconductor substrate 101, sealing ring 140 is by the second conductive layer 141 and the second core is realized and semiconductor
The electric connection of substrate 101.
However the embodiment of the present invention is not limited to this, those skilled in the art can as needed to conductive channel 130 with it is close
The material of seal ring 140 carries out other settings.
Multiple separation layers 103 are located between conductive channel 130 and rhythmic structure of the fence 120 and sealing ring 140 and oxygen
Change between layer 102.Separation layer 103 between conductive channel 130 and rhythmic structure of the fence 120 is used for multiple gate conductor layers
121,122,123 separate with conductive channel 130.Separation layer 103 between sealing ring 140 and oxide layer 102 improves close
The consistency of seal ring 140 and the external structure of conductive channel 130.Wherein, the material of separation layer 103 includes but is not limited to titanium dioxide
Silicon.
First electric connection structure 150 runs through the oxide layer 102 of covering channel column 110, and is electrically connected with channel column 110, leads to
Crossing the first electric connection structure 150 makes channel column 110 be connected to external circuit (such as bit line).
The surface of second electric connection structure, 160 autoxidation layer 102 extends in semiconductor substrate 101, surrounds gate stack knot
Structure is simultaneously surrounded by sealing ring 140, be used to for semiconductor substrate 101 connecting with external circuit (such as make external circuit to semiconductor
Well region power supply in substrate).
Third electric connection structure 170 runs through the oxide layer 102 of covering conductive channel 130, and is electrically connected with conductive channel 130
It connects.Third electric connection structure 170 includes first part 171 and second part 172, wherein and first part 171 is continuous structure,
Consistent with the extending direction of conductive channel 130, second part 172 is multiple column structures, is evenly distributed on first part 171
On.Third electric connection structure 170 connect the source region in semiconductor substrate 101 with external circuit by conductive channel 130.
4th electric connection structure 180 through the oxide layer 102 of covering sealing ring 140, and is electrically connected with sealing ring 140.The
Four electric connection structures 180 include first part 181 and second part 182, wherein first part 181 is the ring-type of continuous structure
Structure, consistent with the shape of sealing ring 140, second part 182 is multiple column structures, is evenly distributed in first part 181.
4th electric connection structure 180 connects 101 external circuit of semiconductor substrate by sealing ring 140.(such as ground connection).
Fig. 3 to Figure 12 shows the sectional view in each stage of 3D memory device manufacturing method according to an embodiment of the present invention.
The sectional view is intercepted along the AA line in Fig. 2 a.Below in conjunction with Fig. 3 to Figure 12 to the manufacturing method of invention memory construction
It is described in detail.
This method starts from semiconductor structure (multiple well region packets that multiple well regions are formed in semiconductor substrate 101
Include high-pressure trap area and source region), in this embodiment, semiconductor substrate 101 is, for example, monocrystalline substrate.
As shown in figure 3, forming the array structure including insulating laminate 180 in semiconductor substrate 101.In this step,
Being formed using depositing operation includes the multiple interlayer insulating films 191 and multiple sacrificial layers 192 being alternately stacked.Adjacent sacrificial layer
192 are separated from each other by interlayer insulating film 191.In this embodiment, interlayer insulating film 191 is for example made of silica, sacrificial layer
192 are for example made of silicon nitride.
As described below, sacrificial layer 192 will be replaced as gate conductor layer 121 to 123, and gate conductor layer 122 is connected to string
Selection line, gate conductor layer 123 are connected to the ground selection line, and gate conductor layer 121 is connected to wordline.In order to be formed from grid conductor
The conductive channel of 121 to 123 arrival ground selection line of layer, wordline and string selection line, multiple sacrificial layers 182 such as patterned
Scalariform, that is, the marginal portion of each sacrificial layer 192 provides electrical connection area relative to the sacrificial layer exposure of top.Multiple sacrificial
After the patterning step of domestic animal layer 192, insulating laminate structure 190 can be surrounded using oxide layer 102.
Further, multiple channel holes are formed through insulating laminate structure 190, in this embodiment, such as in semiconductor
Photoresist mask is formed on the surface of structure, then carries out anisotropic etching, forms ditch in insulating laminate structure 190
Road hole.Anisotropic etching can use dry etching, as ion beam milling etching, plasma etching, reactive ion etching, laser are burnt
Erosion.For example, by control etching period, so that the first surface for being etched in semiconductor substrate 101 nearby stops.After the etching
By dissolving or being ashed removal photoresist mask in a solvent.
Further, multiple channel columns 110 are formed in channel hole.Wherein, channel column 110 includes extending to from upper part
The channel layer of semiconductor substrate 101.For the sake of clarity, the internal structure of channel column 110 is not shown in Fig. 3.B referring to fig. 2,
In the middle section of channel column 110, channel column 110 includes the channel layer 111 stacked gradually, tunneling medium layer 112, charge storage
Layer 113 and block media layer 114, the lower end of channel column 110 and the source region position as described below phase in semiconductor substrate 101
Contact.In final 3D memory device, the upper end of channel column 110 will be connected with wiring layer, to form effective storage
Unit.The structure of channel column 110 is, for example, ONOP (oxidenitride oxide-polysilicon).
Further, self-insulating laminated construction surface, which extends in semiconductor substrate 101, forms grid line gap (the first depth
Slot) 104,102 surface of autoxidation layer, which extends in semiconductor substrate 101, forms the second deep trouth 105, as shown in Figure 4.
In this embodiment, such as on the surface of semiconductor structure form photoresist mask, then carry out it is each to
Grid line gap 104 and the second deep trouth 105 is collectively formed by synchronous process in anisotropic etch.Anisotropic etching can use dry method
Etching, such as ion beam milling etching, plasma etching, reactive ion etching, laser ablation.For example, by control etching period, so that
The face for being etched in semiconductor substrate 101 nearby stops.After the etching by dissolving or being ashed removal photoresist in a solvent
Agent mask.Second deep trouth 105 surrounds insulating laminate structure, forms ring-type, grid line gap 104 is between channel column 110.
Further, sacrificial layer is substituted for gate conductor layer to form rhythmic structure of the fence via grid line gap.
Firstly, being used as etching stopping layer using interlayer insulating film 191, sacrificed via grid line gap 104 by etching removal
Layer 192 is to form cavity 106, as shown in Figure 5.
When forming cavity 106, using grid line gap 104 as etchant channel, removed using isotropic etching exhausted
Sacrificial layer 192 in edge laminated construction is to form cavity 106.Isotropic etching can using selectivity wet etching or
Gas phase etching.Use etching solution as etchant in wet etching, wherein semiconductor structure is immersed in etching solution
In.Use etching gas as etchant in gas phase etching, wherein semiconductor structure is exposed in etching gas.
What interlayer insulating film 191 and sacrificial layer 192 in insulating laminate structure were made of silica and silicon nitride respectively
Under situation, C can be used in gas phase etching using phosphoric acid solution as etchant in wet etching4F8、C4F6、
CH2F2And O2One of or it is a variety of.In an etching step, etchant is full of grid line gap 104.It is sacrificial in insulating laminate structure
The end of domestic animal layer 192 is exposed in the opening in grid line gap 104, and therefore, sacrificial layer 192 touches etchant.Etchant is by grid
The opening of linear slit gap 104 is gradually to the etched inside sacrificial layer 192 of insulating laminate structure.Due to the selectivity of etchant, the erosion
It carves and removes sacrificial layer 192 relative to the interlayer insulating film 191 in insulating laminate structure.
Then, using grid line gap 104 as deposit channel, using atomic layer deposition (ALD), in grid line gap 104
Metal layer is filled in cavity 106.In this embodiment, metal layer is for example made of tungsten.Before being used in atomic layer deposition
Drive source is, for example, tungsten hexafluoride WF6, the reducing gas of use is, for example, silane SiH4Or diborane B2H6.In atomic layer deposition
In step, tungsten hexafluoride WF is utilized6With silane SiH4Reaction product chemisorption obtain tungsten material realize deposition process.
Finally, removal partial metal layers re-form grid line gap 104, and grid conductor 121 to 123 is formed, such as Fig. 6 institute
Show.
In the present embodiment, multiple grid conductors 121 to 123 and interlayer insulating film 161 are alternately stacked.Correspondingly, multiple
Channel column 110 runs through rhythmic structure of the fence 120.
Further, respectively in grid line gap and fill insulant 107 in the second deep trouth, as shown in Figure 7.
In the present embodiment, insulating materials 107 is filled out in grid line gap and the second deep trouth simultaneously for example, by using depositing operation,
Insulating materials 107 includes but is not limited to silica.
Further, second deep trouth of grid line gap 10 and 4 105 is re-formed through insulating materials, and in grid line gap 104
Retain portions of insulating material as separation layer 103, as shown in Figure 8 with the side wall of the second deep trouth 105.
In this embodiment, such as on the surface of semiconductor structure form photoresist mask, then carry out it is each to
Anisotropic etch re-forms grid line gap 104 and the second deep trouth 105.Anisotropic etching can use dry etching, such as ion
Mill etching, plasma etching, reactive ion etching, laser ablation.For example, by control etching period, so that being etched in extension
Stop after certain distance into semiconductor substrate 101.After the etching by dissolving or being ashed removal photoresist in a solvent
Agent mask.
Further, the first conductive structure is filled in grid line gap 104,105 in the second deep trouth in filling second lead
Electric structure.
First conductive layer 131 is formed on the bottom of cover grid linear slit gap 104, and covers bottom and the side wall of the second deep trouth 105
The second conductive layer 141 is formed, as shown in Figure 9.
In the present embodiment, the first conductive layer 131 is collectively formed in identical processing step with the second conductive layer 141,
The material of first conductive layer 131 and the second conductive layer 141 is titanium and/or titanium nitride.
However the embodiment of the present invention is not limited to this, those skilled in the art can according to need to the first conductive layer 131
Other settings are carried out with the material of the second conductive layer 141.
Further, filled in grid line gap the first core to formed run through rhythmic structure of the fence conductive channel,
The second core of filling of second deep trouth runs through the sealing ring of oxide layer to be formed, and, as shown in Figure 10.
The first part 132a of first core is located at the lower part of conductive channel 130, the second part of the first core 132b
In the top of conductive channel 130, is spaced between the end first part 132a of the first core adjacent with first part 132b
One conductive layer 131.
In the present embodiment, the material of the first conductive layer 131 includes titanium nitride and/or titanium, the first part of the first core
The material of 132a includes polysilicon, and the material of the second part 132b of the first core includes tungsten.Conductive channel 130 is led by first
The first part 132a of electric layer 131 and the first core realizes the electric connection with semiconductor substrate 101.
The first part 142a of second core is located at the lower part of sealing ring 140, and the second part 142b of the second core is located at
The top of sealing ring 140, interval second is led between the end first part 142a of the second core adjacent with second part 142b
Electric layer 141.
In the present embodiment, the material of the second conductive layer 141 includes titanium nitride and/or titanium, the first part of the second core
The material of 142a includes tungsten, and the material of the second part 142b of the second core includes polysilicon, and sealing ring 140 passes through second
The first part 142a of conductive layer 141 and the first core realizes the electric connection with semiconductor substrate 101.
Since the first deep trouth and the second deep trouth are formed by synchronous process, and the first conductive structure and the second conductive structure by
Synchronous process is formed, and therefore, the internal structure of conductive channel and sealing ring, material are all the same, in some other embodiments, the
One core is deposited to be formed by tungsten with the second core, and conductive channel 130 is realized by the first conductive layer 131 and the first core
With the electric connection of semiconductor substrate 101, sealing ring is by the second conductive layer 141 and the second core is realized and semiconductor substrate
101 electric connection.
However the embodiment of the present invention is not limited to this, those skilled in the art can be as needed to conductive channel and sealing ring
Material carry out other settings.
Further, deposition continues oxide layer 102 on semiconductor structure, as shown in figure 11.
In this step, oxide layer 102 covers channel column 110, rhythmic structure of the fence, conductive channel 130 and sealing ring
140。
Further, formed the first electric connection structure 150, the second electric connection structure 160, third electric connection structure 170 with
And the 4th electric connection structure 180, as shown in figure 12.
In this step, through part oxide layer 102 is formed on channel column, on conductive channel and on sealing ring respectively
Multiple contact holes, and extended in semiconductor substrate 101 on 102 surface of rhythmic structure of the fence two sides autoxidation layer and form multiple connect
Contact hole,
Filling conductive material is respectively formed the first electric connection structure 150, the second electric connection structure 160, the in the contact hole
Three electric connection structures 170 and the 4th electric connection structure 180, so that the first electric connection structure 150 is electrically connected with channel column 110,
Second electric connection structure 160 is electrically connected with semiconductor substrate 101, and third electric connection structure 170 is electrically connected with conductive channel 130,
4th electric connection structure 180 is electrically connected with sealing ring 140.Wherein, multiple third electric connection structures 170 and the 4th electric connection structure
180 are collectively formed in identical step, and sealing ring 140 surrounds the second electric connection structure 160.
In some other embodiments, due to the first electric connection structure 150, the second electric connection structure 160, third electrical connection
Structure 170 and the 4th electric connection structure 180 are all made of hole technique, therefore can be collectively formed in same steps.
Figure 13 to 14b shows the effect analysis schematic diagram of 3D memory device according to an embodiment of the present invention.Wherein, Figure 13
The structural schematic diagram of 3D memory device in the prior art is shown, Figure 14 a and Figure 14 b respectively illustrate the embodiment of the present invention and show
There is the forming step of the 3D memory device in technology.
As shown in figure 13,3D memory device in the prior art includes semiconductor substrate 201, is located at semiconductor substrate 201
The rhythmic structure of the fence of top, above semiconductor substrate 201 and around covering rhythmic structure of the fence oxide layer 202, run through grid
Multiple channel columns 210 of laminated construction, run through the conductive channel 230 for running through rhythmic structure of the fence between multiple channel columns 210
Oxide layer 202 and the first electric connection structure 240 being electrically connected with channel column 210, through oxide layer 202 and with conductive channel 230
Second electric connection structure 250 of electrical connection, 202 surface of autoxidation layer extend in semiconductor substrate 201 and are located at gate stack knot
The third electric connection structure 260 of structure two sides, 202 surface of autoxidation layer extend in semiconductor substrate 201 and around gate stack knot
The sealing ring 270 of structure and third electric connection structure 260.
As shown in figures 14a, the forming step of 3D memory device in the prior art is respectively as follows:
In step s101, insulating laminate structure and channel column are formed.
In step s 102, grid line gap is formed through photoetching, etching.
In step s 103, displacement forms gate conductor layer.
In step S104, filling grid line gap forms conductive channel.
In step s105, semiconductor devices is planarized.
In step s 106, multiple electric connection structures and sealing ring are formed simultaneously.
As shown in Figure 13 and Figure 14 a, there are following problems for 3D memory device in the prior art and its forming step.
Sealing ring 270 is extended in semiconductor substrate 201 using deep trouth technique from array structure surface, and due to connection half
The third electric connection structure 260 of conductor substrate 201 and external circuit is manufactured using deep hole technique, sealing ring 270 and third
Electric connection structure 260 carries out in same processing step, however, the number of plies with laminated construction is more and more, deep hole etches work
Skill cannot be compatible with deep etching technique, and the function of sealing ring is caused not to be able to satisfy the demand of 3D memory device.
In addition, being deposited in deep trouth by physical vapour deposition (PVD) (Physical Vapor Deposition, PVD) technique
The sealing ring 270 that tungsten is formed, can make fluorine element content in 3D memory device excessively high (F rich), to interfere subsequent work
Skill causes to 3D out of memory, and during deposited metal tungsten it is possible that gap or tomography are asked in deep trouth
Topic, causes sealing ring 270 that cannot realize effective electric connection with semiconductor substrate 201.
As shown in fig. 14b, and Fig. 3 to Figure 12 is combined, the forming step of the 3D memory device of the embodiment of the present invention is respectively as follows:
In step s 201, insulating laminate structure and channel column are formed.
In step S202, the first deep trouth and the second deep trouth are formed through photoetching, etching.
In step S203, displacement forms gate conductor layer.
In step S204, fills the first deep trouth and the second deep trouth is respectively formed conductive channel and sealing ring.
In step S205, semiconductor devices is planarized.
In step S206, multiple electric connection structures are formed.
3D memory device according to an embodiment of the present invention and its manufacturing method, by the sealing for surrounding the rhythmic structure of the fence
Ring has completely cut off steam, has obstructed stress, to achieve the purpose that protect 3D memory device, compared with prior art, in the present invention
In the 3D memory device of embodiment, the first deep trouth and the second deep trouth are formed by synchronous process, and respectively in the first deep trouth
It fills the first conductive structure and forms conductive channel, the second conductive structure is filled in the second deep trouth and forms sealing ring, due to conduction
Channel and sealing ring are all made of deep trouth technique, and the compatibility of the two is more preferable, avoid deep-hole etching process and deep etching technique
The problem that cannot be compatible with.
3D memory device according to an embodiment of the present invention and its manufacturing method, sealing ring is including the first core and around first
First conductive layer of core, the electric conductivity of sealing ring is increased by the first conductive layer, further improves 3D memory device
Performance.
3D memory device according to an embodiment of the present invention and its manufacturing method, the first core with surround the first core first
Conductive layer avoids fluorine element content mistake in device instead of the scheme for forming sealing ring by tungsten completely in the prior art
High problem.
3D memory device according to an embodiment of the present invention and its manufacturing method, since conductive channel and sealing ring are being synchronised
It being collectively formed in rapid, the first electric connection structure includes the etching technics in hole to the 4th electric connection structure, therefore compatibility is preferably,
It can be collectively formed in same steps.
In addition, the embodiment of the present invention under the premise of having not been changed the manufacturing process of conductive channel, realize conductive channel with
Sealing ring is collectively formed in synchronous process, so that simplifying the prior art is formed simultaneously multiple electric connection structures and sealing ring
Step saves the preparation cost.
In the above description, the technical details such as composition, the etching of each layer are not described in detail.But
It will be appreciated by those skilled in the art that can be by various technological means, come layer, the region etc. for forming required shape.In addition, being
Formation same structure, those skilled in the art can be devised by and process as described above not fully identical method.
In addition, although respectively describing each embodiment above, but it is not intended that the measure in each embodiment cannot be advantageous
Ground is used in combination.
The embodiment of the present invention is described above.But the purpose that these embodiments are merely to illustrate that, and
It is not intended to limit the scope of the invention.The scope of the present invention is limited by appended claims and its equivalent.This hair is not departed from
Bright range, those skilled in the art can make a variety of alternatives and modifications, these alternatives and modifications should all fall in of the invention
Within the scope of.
Claims (20)
1. a kind of 3D memory device characterized by comprising
Semiconductor substrate；
Array structure is located at the semiconductor lining, including rhythmic structure of the fence；
Multiple channel columns run through the rhythmic structure of the fence, and contact with the semiconductor substrate；
Conductive channel runs through the rhythmic structure of the fence, and contacts with the semiconductor substrate；And
Sealing ring extends in the semiconductor substrate from the array structure surface, and surrounds the rhythmic structure of the fence,
Wherein, the conductive channel includes the first conductive structure being filled in the first deep trouth, and the sealing ring includes being filled in
The second conductive structure in second deep trouth, first deep trouth and second deep trouth are formed by synchronous process.
2. 3D memory device according to claim 1, which is characterized in that first conductive structure include the first core with
Around the first conductive layer of first core,
Second conductive structure includes the second core and surround the conductive layer of second core,
Wherein, first conductive structure is formed with second conductive structure by synchronous process.
3. 3D memory device according to claim 2, which is characterized in that the array structure further includes oxide layer, is surrounded
And the rhythmic structure of the fence is covered,
Wherein, the sealing ring extends in the semiconductor substrate from the oxidation layer surface.
4. 3D memory device according to claim 3, which is characterized in that further include multiple first electric connection structures, respectively
Oxide layer described in through part is electrically connected with the multiple channel column.
5. 3D memory device according to claim 3, which is characterized in that further include multiple second electric connection structures, be located at
The two sides of the rhythmic structure of the fence extend in the semiconductor substrate from the oxidation layer surface.
6. 3D memory device according to claim 5, which is characterized in that the sealing ring is electrically connected around the multiple second
Binding structure.
7. 3D memory device according to claim 3, which is characterized in that further include:
Multiple third electric connection structures, oxide layer described in through part are electrically connected with the conductive channel；And
4th electric connection structure, oxide layer described in through part are electrically connected with the sealing ring,
Wherein, the multiple third electric connection structure is formed with the 4th electric connection structure by synchronous process.
8. 3D memory device according to claim 3, which is characterized in that further include multiple separation layers, be located at described
Between conductive channel and the rhythmic structure of the fence and between the sealing ring and the oxide layer.
9. 3D memory device according to claim 2, which is characterized in that the material of first core, second core
Material includes the combination of tungsten or tungsten and polysilicon.
10. 3D memory device according to claim 2, which is characterized in that first conductive layer, second conductive layer
Material include titanium and/or titanium nitride.
11. a kind of manufacturing method of 3D memory device characterized by comprising
Array structure, including rhythmic structure of the fence are formed on a semiconductor substrate；
Multiple channel columns are formed through the rhythmic structure of the fence, are contacted with the semiconductor substrate；
Conductive channel is formed through the rhythmic structure of the fence, is contacted with the semiconductor substrate；And
It is extended in the semiconductor substrate from the array structure surface and forms sealing ring, the sealing ring is folded around the grid
Layer structure,
Wherein, the conductive channel includes the first conductive structure being filled in the first deep trouth, and the sealing ring includes being filled in
The second conductive structure in second deep trouth, first deep trouth and second deep trouth are formed by synchronous process.
12. according to the method for claim 11, which is characterized in that the array structure further includes oxide layer, surrounds and covers
The rhythmic structure of the fence is covered,
Wherein, the sealing ring extends in the semiconductor substrate from the oxidation layer surface.
13. according to the method for claim 12, which is characterized in that the step of forming the conductive channel include:
It is extended in the semiconductor substrate from the rhythmic structure of the fence surface and forms first deep trouth；And
First conductive structure is filled in first deep trouth, first conductive structure is including the first core and surrounds institute
State the first conductive layer of the first core.
14. according to the method for claim 13, which is characterized in that the step of forming the sealing ring include:
It is extended in the semiconductor substrate from the oxidation layer surface and forms the second deep trouth, second deep trouth surrounds the grid
Laminated construction；And
Second conductive structure is filled in second deep trouth, second conductive structure is including the second core and surrounds institute
The second conductive layer of the second core is stated,
Wherein, first conductive structure is formed with second conductive structure by synchronous process.
15. according to the method for claim 14, which is characterized in that the manufacturing method of the 3D memory device further include:
Contact hole is respectively formed on the multiple channel column through the oxide layer；And
Filling conductive material forms the first electric connection structure, first electric connection structure and the channel in the contact hole
Column electrical connection.
16. according to the method for claim 14, which is characterized in that the manufacturing method of the 3D memory device further include:
It is extended in the semiconductor substrate in the rhythmic structure of the fence two sides from the oxidation layer surface and forms multiple contact holes；
And
Filling conductive material forms the second electric connection structure in the contact hole, and second electric connection structure is partly led with described
Body substrate electrical connection,
Wherein, the sealing ring surrounds the multiple second electric connection structure.
17. according to the method for claim 14, which is characterized in that the manufacturing method of the 3D memory device further include:
Contact hole is respectively formed on the conductive channel and the sealing ring through the oxide layer；And
The contact hole filling conductive material be respectively formed the third electric connection structure being electrically connected with the conductive channel and
The 4th electric connection structure being electrically connected with the sealing ring,
Wherein, the multiple third electric connection structure is formed in synchronous process with the 4th electric connection structure.
18. according to the method for claim 14, which is characterized in that the manufacturing method of the 3D memory device further includes being formed
Multiple separation layers,
The multiple separation layer is located between the conductive channel and the rhythmic structure of the fence and the sealing ring and institute
It states between oxide layer.
19. any method of 4-18 according to claim 1, which is characterized in that first core, second core
Material includes the combination of tungsten or tungsten and polysilicon.
20. any method of 4-18 according to claim 1, which is characterized in that first conductive layer, second conduction
The material of layer includes titanium and/or titanium nitride.
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