CN109933451B - An exception and interrupt processing system and method based on RISC-V architecture - Google Patents
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Abstract
本发明涉及低功耗内核中断处理技术领域，尤其涉及一种基于RISC‑V架构的异常和中断处理系统及方法，包括模式寄存器、异常向量基址寄存器、状态寄存器、异常原因寄存器、异常返回地址寄存器、中断向量基址寄存器、中断状态寄存器、中断返回地址寄存器。有益效果：通过在处理器的内核中分别增加模式寄存器、中断向量基址寄存器、中断状态寄存器及中断返回地址寄存器，将处理器的中断处理模式与异常处理模式分开处理，以使得异常嵌套中断时，处理器的程序能从异常处理模式与中断处理模式中退出，在存在异常嵌套中断时系统能够恢复。
The invention relates to the technical field of low-power-consumption kernel interrupt processing, and in particular, to an exception and interrupt processing system and method based on a RISC-V architecture, including a mode register, an exception vector base address register, a status register, an exception cause register, and an exception return address Register, interrupt vector base address register, interrupt status register, interrupt return address register. Beneficial effect: by adding a mode register, an interrupt vector base address register, an interrupt status register and an interrupt return address register in the core of the processor, the interrupt processing mode and the exception processing mode of the processor are processed separately, so that the exception nests interrupt At this time, the program of the processor can exit from the exception handling mode and the interrupt handling mode, and the system can recover when there is an exception nested interrupt.
Description
Technical Field
The invention relates to the technical field of low-power-consumption kernel interrupt processing, in particular to an exception and interrupt processing system and method based on a RISC-V framework.
Background
The Interrupt mechanism (Interrupt) is that the processor core is interrupted by another request suddenly in the process of executing the program instruction stream in sequence to stop executing the current program, and then processes another thing until the processor core finishes processing another thing, and then returns to the point of the previous program Interrupt to continue executing the previous program instruction stream. The "other requests" interrupting the execution of the program instruction stream by the processor are referred to as Interrupt requests (Interrupt requests), and the Source of the Interrupt requests is referred to as an Interrupt Source (Interrupt Source), and usually the Interrupt Source is mainly from a peripheral hardware device. The processor going to handle something else is called an Interrupt Service Routine (ISR).
Interrupt handling is a normal mechanism, not an error. After the processor receives the interrupt request, the current program site needs to be protected, which is referred to as a protection site for short. After the interrupt service routine is processed, the processor needs to resume the previous site to continue executing the previously interrupted routine, referred to as the resume site.
Exception (Exception) mechanism, i.e. the processor core suddenly encounters an Exception during the sequential execution of the program instruction stream and terminates the execution of the current program, and then handles the Exception. The "something unusual" encountered by the processor is called an Exception (Exception). An exception is caused by an event within the processor or an event in the execution of a program, such as a hardware fault, a program fault, or the execution of a special system service instruction, and is simply an internal cause. After the exception occurs, the processor may enter an exception service handler. Therefore, the RISC-V architecture has a problem that the system cannot be restored when the interrupt is abnormally nested.
Disclosure of Invention
In view of the above problems in the prior art, a system and method for processing exceptions and interrupts based on RISC-V architecture is now provided.
The specific technical scheme is as follows:
an RISC-V architecture based exception and interrupt handling system comprising:
a mode register for indicating the current operating mode of the system;
an abnormal vector base address register for storing the base address of the abnormal vector when the abnormal request occurs;
a status register for storing the status of exception handling when an exception request occurs;
an exception reason register, is used for storing the exception reason when the request of the exception takes place;
an exception return address register for storing the return address after exception processing when an exception request occurs;
an interrupt vector base register for storing the base of the interrupt vector when an interrupt occurs;
an interrupt status register for storing the status of interrupt processing when an interrupt occurs;
and the interrupt return address register is used for storing the return address after the interrupt processing is finished when the interrupt occurs.
Preferably, the exception and interrupt handling system further comprises an error address or instruction register for storing the access address of the memory or the illegal instruction encoding causing the current exception.
Preferably, the exception vector base address register and the exception return address register are both CSR registers.
Preferably, the status register is a CSR register.
Preferably, the working mode includes a machine sub-mode, a normal mode, an interrupt processing mode, an exception processing mode and a non-mask interrupt mode.
Preferably, the exception handling mode at least comprises an exception priority mode, an exception entering handling mode, an exception exit handling mode, an exception service program mode and an exception nesting mode;
the interrupt processing mode at least comprises an interrupt shielding mode, an interrupt priority and arbitration mode, an interrupt processing mode, an interrupt service program exiting interrupt processing mode, and an interrupt nesting mode.
The invention also includes an abnormality and interrupt processing method based on RISC-V architecture, which is used for any one of the above-mentioned abnormality and interrupt processing systems based on RISC-V architecture, and the abnormality and interrupt processing method based on RISC-V architecture includes an interrupt processing method, the interrupt processing method includes the following steps:
step S10, when the kernel of the processor responds to the interrupt request, the current state of the processor and the return address of the interrupt processing program of the processor are updated, the base address of the interrupt vector of the processor is obtained, and the interrupt processing mode corresponding to the interrupt request is executed;
Step S11, after the interrupt processing mode corresponding to the interrupt request is executed, updating the state of interrupt processing and the current state of the processor, recovering the instruction address of the processor from the return address of the interrupt handler of the processor, and exiting the interrupt processing mode corresponding to the interrupt request.
Preferably, the interrupt processing method further includes the steps of:
step S20, when the kernel of the processor responds to the interrupt request, the current state of the processor and the return address of the processor are updated, the base address of the interrupt vector of the processor is obtained, and the interrupt processing mode corresponding to the interrupt request is executed;
step S21, when the interrupt processing mode corresponding to the interrupt request is executed, an exception occurs, at this time, the kernel of the processor immediately responds to exception information, updates the current state of the processor and the return address of the exception handler storing the processor, respectively, and obtains the base address of the exception vector of the processor, and executes the corresponding exception processing mode;
step S22, after the exception handling mode is executed, updating the exception handling state and the current state of the processor, recovering the instruction address of the processor from the return address of the exception handling program of the processor, exiting the exception handling mode, and returning to the interrupt handling mode corresponding to the interrupt request again for execution;
Step S23, after the interrupt processing mode corresponding to the interrupt request is executed, updating the exception handling state and the current state of the processor, recovering the instruction address of the processor from the return address of the interrupt handler of the processor, and exiting the interrupt processing mode corresponding to the interrupt request.
The invention also comprises an abnormality and interrupt processing method based on the RISC-V architecture, which is used for any one of the above abnormality and interrupt processing systems based on the RISC-V architecture, wherein the abnormality and interrupt processing method based on the RISC-V architecture comprises an abnormality processing method, and the abnormality processing method comprises the following steps:
step S30, when the kernel of the processor responds to the abnormal request, updating the current state of the processor and the return address of the abnormal processing program for storing the processor, acquiring the base address of the abnormal vector of the processor, and starting to execute the abnormal processing mode corresponding to the abnormal request;
step S31, after the exception handling mode corresponding to the exception request is executed, updating the exception handling state and the current state of the processor, recovering the instruction address of the processor from the return address of the exception handler of the processor, and exiting the exception handling mode corresponding to the exception request.
Preferably, the exception handling method further includes the steps of:
step S40, when the kernel of the processor responds to the abnormal request, updating the current state of the processor and the return address of the abnormal processing program for storing the processor, acquiring the base address of the abnormal vector of the processor, and starting to execute the abnormal processing mode corresponding to the abnormal request;
step S41, when the exception handling mode corresponding to the exception request is executed, an exception occurs again, and at this time, the interrupt controller of the core of the processor determines whether the processor is in the exception handling mode before the exception handling mode according to the value of the state of the exception handling;
if yes, go to step S42;
if not, go to the step S44;
when the kernel of the processor responds to the exception again request in step S42, updating the current state of the processor and the return address of the exception handler storing the processor, acquiring the base address of the exception vector of the processor, and starting to execute the exception handling mode corresponding to the exception again;
step S43, after the execution of the exception handling mode corresponding to the reoccurrence of the exception request is completed, updating the state of the exception handling and the current state of the processor, recovering the instruction address of the processor from the return address of the exception handling program of the processor, exiting the exception handling mode corresponding to the reoccurrence of the exception request, and returning to the exception handling mode corresponding to the exception request again for execution;
Step S44, after the exception handling mode corresponding to the exception request is executed, updating the exception handling state and the current state of the processor, recovering the instruction address of the processor from the return address of the exception handler of the processor, and exiting the exception handling mode corresponding to the exception request.
The technical scheme of the invention has the beneficial effects that: the interrupt processing mode and the exception processing mode of the processor are processed separately by respectively adding the mode register, the interrupt vector base address register, the interrupt state register and the interrupt return address register in the kernel of the processor, so that the response speed of the interrupt is accelerated, and the program of the processor can exit from the exception processing mode and the interrupt processing mode when the exception nested interrupt is performed.
Drawings
Embodiments of the present invention will now be described more fully hereinafter with reference to the accompanying drawings. The drawings are, however, to be regarded as illustrative and explanatory only and are not restrictive of the scope of the invention.
FIG. 1 is a functional block diagram of an RISC-V architecture based exception and interrupt handling system according to an embodiment of the present invention;
FIG. 2 is a functional block diagram of the newly added registers of the RISC-V architecture based exception and interrupt handling system of an embodiment of the present invention;
FIG. 3 is a flowchart illustrating the steps of a first embodiment of an interrupt handling method of an exception and interrupt handling method based on RISC-V architecture according to an embodiment of the present invention;
FIG. 4 is a flowchart illustrating the steps of a second embodiment of an interrupt handling method of an exception and interrupt handling method based on RISC-V architecture according to an embodiment of the present invention;
FIG. 5 is a flowchart illustrating the steps of a first embodiment of an exception handling method of the RISC-V architecture based exception and interrupt handling method according to an embodiment of the present invention;
FIG. 6 is a flowchart illustrating the steps of a second embodiment of an interrupt handling method of an exception and interrupt handling method based on RISC-V architecture according to an embodiment of the present invention;
FIG. 7 is a schematic flow diagram of an embodiment of the RISC-V architecture based exception and interrupt handling method of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be obtained by a person skilled in the art without inventive efforts based on the embodiments of the present invention, shall fall within the scope of protection of the present invention.
It should be noted that the embodiments and features of the embodiments of the present invention may be combined with each other without conflict.
The invention is further described with reference to the following drawings and specific examples, which are not intended to be limiting.
In the prior art, the RISC-V architecture defines the CSR register mtvec register, mcause register, and mecc register. The mtvec register is the base address of an interrupt and exception handling entry, the mcause register is an exception cause register, and the mepc register is an exception return address register. The handling of interrupts and exceptions may share these registers. Therefore, if an external interrupt occurs, the processor automatically jumps to an mtvec register to execute (meanwhile, the value of the mecc register is automatically updated to a next unexecuted instruction by hardware), then software queries the mcause register to determine that the cause of the exception is the external interrupt, and then the software jumps to a corresponding external interrupt processing function to execute; similarly, when an exception occurs, the processor jumps to an mtvec register to execute (meanwhile, the value of the mecc register is automatically updated to the abnormal PC by hardware), then software queries the mcause register to determine which exception is the cause of the exception, and then the software jumps to a corresponding exception handling function to execute the exception. It should be noted that the exception may not be masked, that is, once the exception occurs, the processor must stop the current operation and enter the exception handling mode. Thus, an interrupt may be interrupted by an exception at any time. In practical application, if an exception (i.e. an exception nested interrupt) occurs in an interrupt service routine, for the RISC-V architecture, a mecc register and the like automatically saved by hardware when the interrupt occurs are covered when the exception occurs, so that non-recoverable (non-recoverable) results.
Therefore, in view of the above-mentioned drawbacks of the prior art, the present invention discloses an exception and interrupt handling system based on RISC-V architecture, which comprises:
a mode register 1 for indicating the current system operation mode;
an abnormal vector base address register 2, which is used for storing the base address of the abnormal vector when the abnormal request occurs;
a status register 3, for storing the status of exception handling when exception request occurs;
an exception cause register 4 for storing the exception cause when an exception request occurs;
an exception return address register 5, for storing the return address after the exception processing when the exception request occurs;
an interrupt vector base register 6 for storing the base of the interrupt vector when the interrupt occurs;
an interrupt status register 7 for storing the status of interrupt processing when an interrupt occurs;
and the interrupt return address register 8 is used for storing a return address after the interrupt processing is finished when the interrupt occurs.
Through the above-mentioned technical solution of the exception and interrupt handling system based on RISC-V architecture, as shown in fig. 1 and 2, the mode register 1 is an msubmode register, the exception vector base register 2 is an mtvec register, the status register 3 is an mstatus register, the error address or instruction register 9 is an mtval register, the exception cause register 4 is an mcause register, the exception return address register 5 is a mepc register, the interrupt vector base register 6 is a mivec register, the interrupt status register 7 is an istatus register, and the interrupt return address register 8 is a mipc register. It should be noted that the msubmode register, mtvec register, mstatus register, mtval register, mcause register, mcp register, mivec register, istatus register, and mipc register in this solution are different from the corresponding registers in the prior art because the functions of the respective registers are different.
Furthermore, compared with the architecture defined by RISC-V, the exception and interrupt processing system reserves the CSR registers such as the original mtvec register, mstatus register, mtval register, mcause register and mepc register, and also adds 4 CSR registers such as the mivec register, istatus register, mipc register and msubmode register, meanwhile, the mcause register defined in the RISC-V architecture is not used for interrupt processing any more, but is specially used for exception processing, only the MIE domain in the mstatus register is still used for interrupt processing, and other bits are specially used for exception processing.
Further, in the technical scheme, the mtvec register is no longer used as an entry address for interrupt processing, wherein a special entry address mivec register is interrupted; the MPIE field in the mstatus register is no longer related to the interrupt, the actual register of the interrupt has a special MPIE field, the MPS field in the mstatus register is no longer related to the interrupt, and the actual register of the interrupt has a special MPS field; the mcp register is no longer associated with interrupts, which have a dedicated mipc register for storing the return address of the interrupt.
In the technical scheme, the state of the processor when the interrupt occurs is saved through the interrupt return address register 8 and the interrupt state register 7, and only the values in the exception return address register 5 and the state register 3 are changed when the exception occurs, so that exception nesting and interrupt restorability are ensured under the condition that the interrupt return address register 8 and the interrupt state register 7 are not influenced.
Furthermore, the mode register 1, the interrupt vector base address register 6, the interrupt state register 7 and the interrupt return address register 8 are respectively added in the kernel of the processor, so that the interrupt processing mode and the exception processing mode of the processor are separately processed, the response speed of the interrupt is increased, and the program of the processor can exit from the exception processing mode and the interrupt processing mode when the exception nested interrupt occurs.
In the above technical solution, the exception and interrupt handling system further includes an error address or instruction register 9, which is used for storing an access address of the memory causing the current exception or an illegal instruction code.
In the above technical solution, the exception vector base register 2 and the exception return address register 5 are both CSR registers, and are readable and writable under the exception vector base register 2 and the exception return address register 5. Namely, the mtvec register and the mepc register are both CSR registers, and the mtvec register and the mepc register can be read and written.
In the above technical solution, the status register 3 is a CSR register, and under the status register 3, the MIE domain, the MPIE domain, the MPP domain, and the MPS domain are all readable and writable. Further, the MPIE field, the MPP field and the MPS field are respectively used for automatically storing the values of the MIE field, the privileged mode and the machine submode before entering the interrupt processing mode, and are used for automatically recovering when exiting the exception processing mode. Namely, the mstatus register is a CSR register, and the MIE domain, the MPIE domain, the MPP domain and the MPS domain of the mstatus register are readable and writable. Wherein, the bit of the MIE domain is 3, the bit of the MPIE domain is 7, and the bit of the MPP domain is 12-11.
Specifically, in the mstatus register, an MIE field is used for representing the global interrupt enable, an MPIE field is used for saving the value of the MIE field before the exception is entered, and an MPS field is used for saving the value of the privileged mode before the exception is entered; in the actual register, MPIE field is used to save the value of MIE field before the interrupt is entered, MPS field is used to save the value of privileged mode before the interrupt is entered.
In a preferred embodiment, the working mode includes machine sub-mode, normal mode, interrupt processing mode, exception processing mode, and unmasked interrupt mode.
Further, the exception handling mode includes at least a priority mode of the exception, an enter exception handling mode, an exit exception handling mode, an exception service routine mode, and an exception nesting mode.
Specifically, the exception in the processor core may not be masked, that is, once the exception occurs, the processor must stop the current operation and enter the exception handling mode.
Further, the priority pattern of the abnormality means that the smaller the number of abnormality numbers, the higher the priority of the abnormality. Further, when entering the exception handling mode, the hardware behavior of the processor includes: stopping executing the current program flow, and starting to execute from the PC address defined by the CSR mtvec register; the hardware is provided with a CSR register mcas register, a mcp register, an mtval register and a mstatus register at the same time, wherein the mcas register is updated to be a currently generated exception type, an exception return address mcp register is updated to be a currently generated exception instruction PC, the mtval register is updated to be a memory access address or an illegal instruction code causing current exception, and the mstatus register updates the value of an MIE field to be 0 and updates the value of an MPP field to be a Privilege Mode (Privilege Mode) before exception generation and updates the value of an MPS field to be a Machine Sub-Mode (Machine Sub-Mode) before exception generation; hardware updates the processor core's Privilege Mode (Privilege Mode) and Machine Sub-Mode (Machine Sub-Mode), mstatus register, MPIE field's value is updated to mstatus register before exception occurs, MIE field's value, processor core's Privilege Mode (Privilege Mode) is updated to normal (Machine Mode), processor core's Machine Sub-Mode (Machine Sub-Mode) is updated to exception handling Mode.
Further, when the exception handling mode is exited, the hardware behavior of the processor includes: stopping executing the current program flow, and starting to execute from the PC address defined by the CSR register mepc register; hardware updates the CSR register mstatus register, the value of MIE field is restored to the value of the current mstatus register MPIE field, the value of the current mstatus register MPIE field is updated to 1; the hardware updates both the processor core's privileged Mode (Privilege Mode) which returns to the mstatus register MPP field value and the Machine Sub-Mode (Machine Sub-Mode) which returns to the mstatus register MPP field value.
Further, anomalous nesting refers to: after entering the exception handler, the exception may be encountered again, which is called a Double exception Fault (Double Fault), and is often a very serious Fault. The value of the MPS domain determines whether the exception handling mode was in the exception handling mode before entry (i.e., the exception was nested) by determining its mstatus register after entry into the exception service routine.
Furthermore, the mode register 1, the interrupt vector base address register 6, the interrupt state register 7 and the interrupt return address register 8 are respectively added in the kernel of the processor, so that the interrupt processing mode and the exception processing mode of the processor are separately processed, the response speed of the interrupt is increased, and the program of the processor can exit from the exception processing mode and the interrupt processing mode when the exception nested interrupt occurs.
In a preferred embodiment, the interrupt handling modes include at least an interrupt mask mode, an interrupt priority and arbitration mode, an entry into an interrupt handling mode, an exit from an interrupt handling mode, an interrupt service routine mode, and an interrupt nesting mode.
Specifically, interrupt mask mode includes the MIE field of the mstatus register being used to control the global enabling of interrupts.
Furthermore, the interrupt mask mode further includes implementing an interrupt controller, where the interrupt controller manages all the interrupt sources in a unified manner, and the interrupt controller allocates a respective interrupt enable register to each interrupt source, so that a user can manage the mask of each interrupt source by configuring the register of the interrupt controller.
Further, the interrupt priority and arbitration mode refers to that the interrupt controller manages arbitration of all interrupt sources uniformly, the interrupt controller allocates a respective interrupt priority register for each interrupt source, and a user can manage the priority of each interrupt source by configuring the register of the interrupt controller.
Further, when entering the interrupt handling mode, the hardware behavior of the kernel of the processor includes: stopping executing the current program flow and starting to execute from the PC address defined by the CSR register mivec register; it also allows the hardware to update several other CSR registers simultaneously: a mipc register, an mstatus register, and an istatus register, the interrupt return address mipc register being pointed to the next instruction that has not yet been executed, the mstatus register, the value of the MIE field being updated to 0, the istatus register, the value of the MPIE field being updated to the mstatus register before the interrupt occurred, the value of the MIE field, the istatus register, the value of the MPP field being updated to the Privilege Mode (Privilege Mode) before the interrupt occurred, the istatus register, the value of the MPS field being updated to the Machine Sub-Mode (Machine Sub-Mode) before the interrupt occurred; in addition, entering the interrupt updates the Privilege Mode (privillemode) and the Machine Sub-Mode (Machine Sub-Mode) of the processor core, the Privilege Mode (privillemode) of the processor core is updated to the normal (Machine Mode), and the Machine Sub-Mode (Machine Sub-Mode) of the processor core is updated to the interrupt processing Mode.
Further, the hardware behavior of the kernel of the processor when exiting the interrupt handling mode includes: stopping executing the current program flow, and starting to execute from the PC address defined by the CSR register mipc register; updating CSR register mstatus register, istatus register, and update Privilege Mode (Privilege Mode), and Machine Sub-Mode (Machine Sub-Mode), mstatus register, the value of MIE field is restored to the value of current istatus register MPIE field, the value of the istatus register MPIE field is updated to 1, the Privilege Mode (Privilege Mode) of the processor is the value of the istatus register MPP field, and the Machine Sub-Mode (Machine Sub-Mode) of the processor is updated to the value of the istatus register MPS Sub-field.
Further, the specific implementation of interrupt nesting includes: after the program jumps into the interrupt service program, the software can force to rewrite the value of the mstatus register, and change the value of the MIE field to 1, which means that the interrupt is globally opened again, and from this moment, the processor can respond to the interrupt again; the interrupt controller of the processor core will ensure that only new interrupts of higher priority are allowed to be dispatched to the processor core; during interrupt nesting, software needs to take care to save the context to the memory stack or to restore the context from the memory stack (same as function nesting). During interrupt nesting, software also needs to take care to save or restore values of the mipc and istatus registers to or from the memory stack (same way as function nesting).
The invention also comprises an abnormality and interruption processing method based on the RISC-V architecture, wherein the abnormality and interruption processing method based on the RISC-V architecture comprises an interruption processing method.
Specifically, as shown in fig. 3, the first embodiment of the interrupt processing method includes the steps of:
step S10, when the kernel of the processor responds to the interrupt request, the current state of the processor and the return address of the interrupt processing program of the storage processor are updated, the base address of the interrupt vector of the processor is obtained, and the interrupt processing mode corresponding to the interrupt request is executed;
step S11, after the execution of the interrupt processing mode corresponding to the interrupt request is completed, the state of the interrupt processing and the current state of the processor are updated, the instruction address of the processor is restored from the return address of the interrupt processing program of the processor, and the interrupt processing mode corresponding to the interrupt request is exited.
Further, as shown in fig. 4, the first embodiment of the interrupt processing method includes the steps of:
step S20, when the kernel of the processor responds to the interrupt request, the current state of the processor and the return address of the storage processor are updated, the base address of the interrupt vector of the processor is obtained, and the interrupt processing mode corresponding to the interrupt request is started to be executed;
Step S21, when the interrupt processing mode corresponding to the interrupt request is executed, an exception occurs, at this time, the kernel of the processor immediately responds to the exception information, respectively updates the current state of the processor and the return address of the exception handling program of the storage processor, acquires the base address of the exception vector of the processor, and executes the corresponding exception processing mode;
step S22, after the exception handling mode is executed, updating the exception handling state and the current state of the processor, recovering the instruction address of the processor from the return address of the exception handler of the processor, exiting the exception handling mode, and returning to the interrupt handling mode corresponding to the interrupt request again for execution;
step S23, after the interrupt processing mode corresponding to the interrupt request is executed, the exception handling state and the current state of the processor are updated, the instruction address of the processor is recovered from the return address of the interrupt processing program of the processor, and the interrupt processing mode corresponding to the interrupt request is exited.
The invention also comprises an abnormality and interruption processing method based on the RISC-V architecture, wherein the abnormality and interruption processing method based on the RISC-V architecture comprises an abnormality processing method.
Specifically, as shown in fig. 5, the first embodiment of the exception handling method includes the steps of:
step S30, when the kernel of the processor responds to the abnormal request, the current state of the processor and the return address of the abnormal processing program of the storage processor are updated, the base address of the abnormal vector of the processor is obtained, and the abnormal processing mode corresponding to the abnormal request is executed;
step S31, after the exception handling mode corresponding to the exception request is executed, the state of the exception handling and the current state of the processor are updated, the instruction address of the processor is recovered from the return address of the exception handling program of the processor, and the exception handling mode corresponding to the exception request is exited.
Further, as shown in fig. 6, the second embodiment of the exception handling method includes the steps of:
step S40, when the kernel of the processor responds to the abnormal request, the current state of the processor and the return address of the abnormal processing program of the storage processor are updated, the base address of the abnormal vector of the processor is obtained, and the abnormal processing mode corresponding to the abnormal request is executed;
step S41, when the exception handling mode corresponding to the exception request is executed, an exception occurs again, and at this time, the interrupt controller of the core of the processor determines whether the processor is in the exception handling mode before according to the value of the state of the exception handling;
If yes, go to step S42;
if not, go to step S44;
step S42, when the kernel of the processor responds to the abnormal request again, the current state of the processor and the return address of the abnormal processing program of the storage processor are updated, the base address of the abnormal vector of the processor is obtained, and the abnormal processing mode corresponding to the abnormal request which occurs again is executed;
step S43, after executing the exception handling mode corresponding to the reoccurrence of the exception request, updating the exception handling state and the current state of the processor, recovering the instruction address of the processor from the return address of the exception handling program of the processor, exiting the exception handling mode corresponding to the reoccurrence of the exception request, and returning to the exception handling mode corresponding to the exception request again for execution;
step S44, after the exception handling mode corresponding to the exception request is executed, updates the exception handling state and the current state of the processor, restores the instruction address of the processor from the return address of the exception handler of the processor, and exits the exception handling mode corresponding to the exception request.
In a preferred embodiment, with the above technical solution of the method for nesting exceptions and interrupts based on the RISC-V architecture, as shown in fig. 7, a step1, a processor core responds to a Request of an Interrupt Request (Interrupt Request1), updates a mipc register, an istatus register and a submode register, jumps to a mivec register, and starts to execute an Interrupt handler corresponding to the Interrupt Request (Interrupt Request 1);
step2, the processor core generates an exception in the middle of executing the Interrupt processing program corresponding to the Interrupt Request (Interrupt Request1), at the moment, the processor core immediately responds to the exception, updates a mcp register, a mstatus register and a msubmode register, jumps to an mtvec register and executes the corresponding exception processing program;
step3, after the processor kernel executes the abnormal processing program, updating the mstatus register and the msubmode register, recovering the PC address from the mepc register, exiting the abnormal processing program, and returning to the Interrupt processing program corresponding to the Interrupt Request (Interrupt Request1) for execution;
after the Interrupt handler corresponding to the Interrupt Request (Interrupt Request1) is executed, step4 updates the mstatus register and the msubmode register, restores the PC address from the mipc register, and exits the Interrupt handler corresponding to the Interrupt Request (Interrupt Request 1).
Furthermore, in the flow of the abnormal nested interrupt, the state of the processor when the interrupt occurs is saved through the mipc register and the istatus register, and the values in the mcp register and the mstatus register are only changed when the exception occurs, without influencing the mipc register and the istatus register, so that the abnormal nested interrupt is ensured to be recoverable.
While the invention has been described with reference to a preferred embodiment, it will be understood by those skilled in the art that various changes in form and detail may be made without departing from the spirit and scope of the invention.
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| CN112905374A (en) * | 2021-02-08 | 2021-06-04 | 烽火通信科技股份有限公司 | Method and device for improving robustness of embedded software |
| CN114968370A (en) * | 2021-02-25 | 2022-08-30 | 华为技术有限公司 | An exception handling method and related device |
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| US5386563A (en) * | 1992-10-13 | 1995-01-31 | Advanced Risc Machines Limited | Register substitution during exception processing |
| CN108595256A (en) * | 2018-03-20 | 2018-09-28 | 武汉市聚芯微电子有限责任公司 | A method of software realization interrupt nesting is used based on RISC-V framework chips |
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