CN109922572A - A kind of μ LED current pattern pixel drive circuit system - Google Patents

Abstract

The invention provides a μLED current mode pixel driving circuit system, which includes: a reference current generating circuit, a pixel current driving unit, an 8-bit SRAM unit, a counter and a comparator. The pixel current driving unit includes a cascaded current mirror circuit and a switch control tube; the currents of the cascaded current mirror circuit and the reference current generating circuit are kept the same. The comparator compares the data stored in the 8-bit SRAM unit with the data of the counter, converts the 8-bit pixel grayscale signal into a PWM signal, and controls the switch control tube through the PWM signal, thereby realizing the PWM current to control the brightness of the μLED. The invention can accurately copy the constant current of the reference current generation circuit to the cascaded current mirror circuit, and control the on-off time of the switch control tube through the PWM signal generated by the comparator, thereby realizing the pulse modulation of the current and improving the traditional voltage The display brightness control difficulty and uneven display caused by the control circuit are increased, and better display effect and contrast ratio can be obtained.

Description

A μLED current mode pixel drive circuit system

technical field

The invention relates to the technical field of driving circuits, in particular to a μLED current mode pixel driving circuit system.

Background technique

LED drive power is a power converter that converts the power supply into a specific voltage and current to drive LED light. The output of LED drive power supply is mostly a constant current source that can change the voltage with the change of LED forward voltage drop value. There are two common driving modes, one is a constant voltage source for multiple constant current sources, and each constant current source supplies power to each LED individually. This combination method is flexible, when one LED fails, it will not affect the work of other LEDs.

The driving methods include constant current, voltage regulation, pulse driving, etc. The output current of the constant current drive circuit is constant, but the output DC voltage varies within a certain range with the load resistance value. The load resistance value is small, the output voltage is low, and the load resistance value is large, the output voltage is high. ; Constant current drive circuit to drive LED is ideal. Voltage-stabilized drive, when the parameters in the voltage-stabilizing circuit are determined, the output voltage is fixed, while the output current changes with the increase or decrease of the load. Pulse driven, dimming is required for many LED applications such as LED backlighting or architectural lighting dimming. Dimming can be achieved by adjusting the brightness and contrast of the LEDs. Lowering the device current may adjust the LED light emission, but operating the LED at less than rated current can have many undesirable consequences, such as chromatic aberration problems. An alternative to simple current regulation is to integrate a pulse-width modulation (PWM) controller in the LED driver. The PWM signal is not used to control the LED directly, but rather a switch, such as a MOSFET, to supply the required current to the LED. PWM controllers typically operate at a fixed frequency and adjust the pulse width to match the desired duty cycle. Most of the current LED chips use PWM to control the LED light emission, in order to ensure that people do not feel obvious flickering, the frequency of the PWM pulse must be greater than 100HZ. The main advantage of PWM control is that the dimming current through PWM is more accurate, and the color difference when the LED emits light is minimized.

Based on the above several driving methods, according to the characteristics of LED current and voltage, it is ideal to use constant current driving, which can avoid the current fluctuation caused by the change of the forward voltage of the LED, and the constant current makes the brightness of the LED more stable.

However, in the traditional LED constant current control method, the constant current used is usually directly connected to the LED, resulting in inevitable fluctuations or even large fluctuations in the current during the LED operation, which will lead to the display brightness of the display is not easy to control and there will be uneven problems .

SUMMARY OF THE INVENTION

In order to overcome the above problems, the present invention aims to provide a μLED current mode pixel driving circuit system, which can realize constant current of the driving circuit and precisely control the on-off of the driving circuit through a PWM signal.

In order to achieve the above object, the present invention provides a μLED current mode pixel driving circuit system, which includes: a reference current generating circuit, a pixel current driving unit, a counter, an 8-bit SRAM unit and a comparator;

A reference current generating circuit for generating a reference current;

The pixel current driving unit includes a cascaded current mirror circuit and a switch control tube; the cascaded current mirror circuit is used as a mirror branch of the reference current generation circuit, and the current of the reference current generation circuit remains the same; the reference current generation circuit is a constant flow circuit;

The comparator compares the data stored in the 8-bit SRAM unit with the signal data of the counter, and converts the 8-bit pixel grayscale information data into a PWM signal; the PWM signal controls the on-off time of the switch control tube.

Preferably, the cascaded current mirror circuit specifically includes: a zeroth MOS transistor, a first MOS transistor and a second MOS transistor connected in series, wherein the zeroth MOS transistor is connected to the power supply, the second MOS transistor is connected to the μLED, and the first MOS transistor is connected to the μLED. It is sandwiched between the zeroth MOS transistor and the second MOS transistor; the gate of the first MOS transistor is connected to the SRAM unit.

In some embodiments, the counter adopts a RAMP generator, and the PWM signal is output through a 1-bit SRAM output device; wherein,

One end of the 8-bit SRAM cell is connected with the comparator, and the other end is connected with the image signal end;

The RAMP generator is connected to the comparator;

The comparator receives and compares the frame signal from the 8-bit SRAM unit and the ramp signal of the RAMP generator; when the frame signal and the ramp signal are the same, send a 1-bit PWM signal to the 1-bit SRAM output device;

The 1bit SRAM output device is connected to the comparator, receives the 1bit PWM signal from the comparator and sends it to the gate terminal of the first MOS transistor;

After the gate terminal of the first MOS transistor receives the signal from the 1-bit SRAM, the first MOS transistor is turned on or off.

In some embodiments, the reference current generating circuit specifically includes: a third MOS transistor, a fourth MOS transistor and a fifth MOS transistor connected in series; wherein the fifth MOS transistor is connected to the power supply, the third MOS transistor is connected to the reference current, The fourth MOS transistor is grounded; the fourth MOS transistor is sandwiched between the third MOS transistor and the fifth MOS transistor; the gate terminal of the third MOS transistor is connected to the gate terminal of the second MOS transistor; the gate terminal of the fifth MOS transistor is connected to the gate terminal of the second MOS transistor. The gate terminal of the zeroth MOS transistor is connected.

In some embodiments, the zeroth MOS transistor, the first MOS transistor, the second MOS transistor, the fifth MOS transistor, the fourth MOS transistor, and the third MOS transistor are all of the same type of MOS Tube.

In some embodiments, the zeroth MOS transistor, the first MOS transistor, the second MOS transistor, the fifth MOS transistor, the fourth MOS transistor, and the third MOS transistor are all PMOS transistors.

In some embodiments, the third MOS transistor is further connected to a reference current source; one end of the reference current source is grounded, and the other end is connected to the gate terminal and the source terminal of the third MOS transistor.

In some embodiments, the gate terminal of the fifth MOS transistor is connected to the drain terminal of the fourth MOS transistor.

In some embodiments, the drain terminal of the zeroth MOS transistor is connected to a power supply, the source terminal of the zeroth MOS transistor is connected to the drain terminal of the first MOS transistor, and the source terminal of the first MOS transistor is connected to the The drain terminal of the second MOS transistor, and the source terminal of the second MOS transistor is connected to the μLED.

In some embodiments, the drain terminal of the fifth MOS transistor is connected to a power supply, the source terminal of the fifth MOS transistor is connected to the drain terminal of the fourth MOS transistor, and the drain terminal of the fourth MOS transistor is connected to the The source end of the third MOS transistor.

In some embodiments, the reference current generation circuit is located outside the pixel and the cascaded current mirror circuit is located within the pixel.

In some embodiments, the reference current generation circuit is one, the cascaded current mirror circuits are multiple, and the multiple cascaded current mirror circuits are connected to the μLED array.

The μLED current mode pixel driving circuit system of the present invention can accurately copy the constant current of the reference current generating circuit to the cascaded current mirror circuit, and control the on-off time of the switch control tube through the PWM signal generated by the comparator, thereby realizing The pulse modulation of the current improves the display brightness control difficulty and uneven display problems caused by the traditional voltage control circuit, and can obtain better display effect and contrast ratio.

Description of drawings

1 is a schematic structural diagram of a μLED current mode pixel driving circuit system according to an embodiment of the present invention

Detailed ways

In order to make the content of the present invention clearer and easier to understand, the content of the present invention will be further described below with reference to the accompanying drawings. Of course, the present invention is not limited to this specific embodiment, and general substitutions known to those skilled in the art are also covered within the protection scope of the present invention.

The μLED current mode pixel driving circuit system of the present invention includes: a reference current generating circuit, a pixel current driving unit, a counter, an 8-bit SRAM unit and a comparator. The reference current generating circuit is used for generating the reference current; the pixel current and the driving unit include a cascaded current mirror circuit and a switch control tube. The cascaded current mirror circuit is used as the mirror branch of the reference current generation circuit, and the current of the reference current generation current remains the same, and the current generation circuit is a constant current circuit; the comparator compares the data stored in the 8-bit SRAM unit with the signal of the counter The data is compared, and the 8-bit pixel grayscale information data is converted into a PWM signal; the PWM signal controls the on-off time of the switch control tube. The cascaded current mirror circuit can accurately copy the constant current of the reference current circuit, and control the on-off time of the switch control tube through the PWM signal generated by the comparator, so as to realize the PWM current to control the brightness of the μLED.

The present invention will be further described in detail below with reference to FIG. 1 and specific embodiments. It should be noted that, the accompanying drawings are in a very simplified form and use inaccurate scales, and are only used to facilitate and clearly achieve the purpose of assisting the description of the present embodiment.

Referring to Figure 1, along the dotted line in the figure, the reference current generation circuit (left side of Figure 1) and the cascaded current mirror circuit (right side of Figure 1). Specifically, the reference current generating circuit specifically includes: a third MOS transistor M3, a fourth MOS transistor M4 and a fifth MOS transistor M5 connected in series; the cascaded current mirror circuit specifically includes: a zeroth MOS transistor M0 connected in series with each other, a first MOS transistor M0 MOS transistor M1 and second MOS transistor M2 (switch control transistor). On both sides of the dotted line, the distribution of the reference current generation circuit and the cascaded current mirror circuit is symmetrical, that is, the fifth MOS transistor M5 corresponds to the zeroth MOS transistor M0, the third MOS transistor M3 corresponds to the second MOS transistor M2, and the fourth MOS transistor M5 corresponds to the second MOS transistor M2. The transistor M4 corresponds to the first MOS transistor M1, thereby forming a cascade circuit.

Here, the fifth MOS transistor M5 is connected to the power supply VDDP, the third MOS transistor M3 is connected to the reference current, and the fourth MOS transistor M4 is grounded; the fourth MOS transistor M4 is sandwiched between the third MOS transistor M3 and the fifth MOS transistor M5; The gate terminal of the three MOS transistor M3 is connected to the gate terminal of the second MOS transistor M2; the gate terminal of the fifth MOS transistor M5 is connected to the gate terminal of the zeroth MOS transistor M0. Here, the third MOS transistor M3 is also connected to a reference current source IREF; one end of the reference current source IREF is grounded, and the other end is connected to the gate terminal and the source terminal of the third MOS transistor M3. The gate terminal of the fifth MOS transistor M5 is connected to the drain terminal of the fourth MOS transistor M4. The drain terminal of the fifth MOS transistor M5 is connected to the power supply VDDP, the source terminal of the fifth MOS transistor M5 is connected to the drain terminal of the fourth MOS transistor M4, and the drain terminal of the fourth MOS transistor M4 is connected to the source terminal of the third MOS transistor M3.

Correspondingly, the zeroth MOS transistor M0 is connected to the power supply VDDP, the second MOS transistor M2 is connected to the μLED, and the first MOS transistor M1 is sandwiched between the zeroth MOS transistor M0 and the second MOS transistor M2; the gate of the first MOS transistor M1 Terminate the SRAM cell. The drain terminal of the zeroth MOS transistor M0 is connected to the power supply VDDP, the source terminal of the zeroth MOS transistor M0 is connected to the drain terminal of the first MOS transistor M1, the source terminal of the first MOS transistor M1 is connected to the drain terminal of the second MOS transistor M2, and the second MOS transistor M1 is connected to the drain terminal of the second MOS transistor M2. The source end of the MOS transistor M2 is connected to the μLED.

Here, the zeroth MOS transistor M0, the first MOS transistor M1, the second MOS transistor M2, the fifth MOS transistor M5, the fourth MOS transistor M4, and the third MOS transistor M3 are all MOS transistors of the same type, such as those shown in FIG. 1 . Show PMOS tube.

Next, please refer to FIG. 1 again, and specifically look at the 8-bit SRAM unit 201, the counter 202 and the comparator 203 in this embodiment. The 8-bit SRAM unit 201, the RAMP generator (counter 202), the comparator 203, and the 1-bit SRAM output One end of the 8-bit SRAM unit 201 is connected to the comparator 203, and the other end is connected to the image signal end.

The RAMP generator (counter 202) is connected to the comparator 203; the comparator 203 receives and compares the frame signal from the 8-bit SRAM unit 201 and the ramp signal of the RAMP generator (counter 202); when the frame signal and the ramp signal are the same, send 1 bit The PWM signal is sent to the 1-bit SRAM output device 204; the 1-bit SRAM output device 204 is connected to the comparator 203, receives the 1-bit PWM signal from the comparator 203 and sends it to the gate terminal of the first MOS transistor M1.

After the gate terminal of the first MOS transistor M1 receives the signal from the 1-bit SRAM, the first MOS transistor M1 is turned on or off.

As shown in FIG. 1 , in the relative positions of the reference current generation circuit and the cascaded current mirror circuit, the reference current generation circuit is located outside the pixel, and the cascaded current mirror circuit is located in the pixel.

In addition, in other embodiments of the present invention, there is one reference current generating circuit and multiple cascaded current mirror circuits, and the multiple cascaded current mirror circuits are connected to the μLED array, for example, each circuit is connected to a pixel.

To sum up, the present invention can accurately copy the constant current of the reference current generating circuit to the cascaded current mirror circuit, and control the on-off time of the switch control tube through the PWM signal generated by the comparator, thereby realizing the pulse modulation of the current. , improving the display brightness control difficulty and uneven display problems caused by the traditional voltage control circuit, and can obtain better display effect and contrast.

Although the present invention has been disclosed above with preferred embodiments, the embodiments are merely examples for the convenience of description, and are not intended to limit the present invention. Those skilled in the art can make With certain changes and modifications, the protection scope claimed by the present invention should be based on the claims.

Claims (12)

1. A μLED current mode pixel drive circuit system, characterized in that, comprising: a reference current generation circuit, a pixel current drive unit, a counter, an 8-bit SRAM unit and a comparator; A reference current generating circuit for generating a reference current; The pixel current driving unit includes a cascaded current mirror circuit and a switch control tube; the cascaded current mirror circuit is used as a mirror branch of the reference current generation circuit, and the current of the reference current generation circuit remains the same; the reference current generation circuit is a constant flow circuit; The comparator compares the data stored in the 8-bit SRAM unit with the signal data of the counter, and converts the 8-bit pixel grayscale information data into a PWM signal; the PWM signal controls the on-off time of the switch control tube. 2 . The μLED current mode pixel driving circuit system according to claim 1 , wherein the cascaded current mirror circuit specifically comprises: a zeroth MOS transistor, a first MOS transistor and a second MOS transistor connected in series, wherein The zeroth MOS tube is connected to the power supply, the second MOS tube is connected to the μLED, and the first MOS tube is sandwiched between the zeroth MOS tube and the second MOS tube; the gate terminal of the first MOS tube is connected to the SRAM cell. 3. The μLED current mode pixel drive circuit system according to claim 1, wherein the counter adopts a RAMP generator, and the PWM signal is output through a 1bit SRAM output device; wherein, One end of the 8-bit SRAM cell is connected with the comparator, and the other end is connected with the image signal end; The RAMP generator is connected to the comparator; The comparator receives and compares the frame signal from the 8-bit SRAM unit and the ramp signal of the RAMP generator; when the frame signal and the ramp signal are the same, send a 1-bit PWM signal to the 1-bit SRAM output device; The 1bit SRAM output device is connected to the comparator, receives the 1bit PWM signal from the comparator and sends it to the gate terminal of the first MOS transistor; After the gate terminal of the first MOS transistor receives the signal from the 1-bit SRAM, the first MOS transistor is turned on or off. 4 . The μLED current mode pixel driving circuit system according to claim 2 , wherein the reference current generating circuit specifically comprises: a third MOS transistor, a fourth MOS transistor and a fifth MOS transistor connected in series; wherein, The fifth MOS tube is connected to the power supply, the third MOS tube is connected to the reference current, and the fourth MOS tube is grounded; the fourth MOS tube is sandwiched between the third MOS tube and the fifth MOS tube; the gate end of the third MOS tube is connected to the second MOS tube The gate terminal of the MOS transistor is connected; the gate terminal of the fifth MOS transistor is connected to the gate terminal of the zeroth MOS transistor. 5 . The μLED current mode pixel driving circuit system according to claim 4 , wherein the zeroth MOS transistor, the first MOS transistor, the second MOS transistor, the fifth MOS transistor, the The four MOS transistors and the third MOS transistor are of the same type. 6 . The μLED current mode pixel driving circuit system according to claim 5 , wherein the zeroth MOS transistor, the first MOS transistor, the second MOS transistor, the fifth MOS transistor, the The four MOS transistors and the third MOS transistor are both PMOS transistors. 7 . The μLED current mode pixel driving circuit system according to claim 4 , wherein the third MOS transistor is further connected to a reference current source; one end of the reference current source is grounded, and the other end is connected to the third MOS transistor. 8 . The gate terminal and the source terminal of the MOS transistor are connected. 8 . The μLED current mode pixel driving circuit system according to claim 6 , wherein the gate terminal of the fifth MOS transistor is connected to the drain terminal of the fourth MOS transistor. 9 . 9 . The μLED current mode pixel driving circuit system according to claim 6 , wherein the drain terminal of the zeroth MOS transistor is connected to a power supply, and the source terminal of the zeroth MOS transistor is connected to the source terminal of the first MOS transistor. 10 . The drain terminal, the source terminal of the first MOS transistor is connected to the drain terminal of the second MOS transistor, and the source terminal of the second MOS transistor is connected to the μLED. 10 . The μLED current mode pixel driving circuit system according to claim 6 , wherein the drain terminal of the fifth MOS transistor is connected to a power supply, and the source terminal of the fifth MOS transistor is connected to the source terminal of the fourth MOS transistor. 11 . The drain terminal, the drain terminal of the fourth MOS transistor is connected to the source terminal of the third MOS transistor. 11 . The μLED current mode pixel driving circuit system of claim 1 , wherein the reference current generating circuit is located outside the pixel, and the cascaded current mirror circuit is located inside the pixel. 12 . 12 . The μLED current mode pixel driving circuit system according to claim 1 , wherein the reference current generation circuit is one, the cascaded current mirror circuits are multiple, and the cascaded current mirror circuits are multiple. 13 . Connect the μLED array.