CN109905015B - Reverse conducting IGBT driving method for three-level diode desaturation control - Google Patents

Abstract

The invention provides a reverse-conducting IGBT driving method with three-level diode desaturation control. A high-speed Hall sensor circuit is used to detect the load current, thereby judging the working mode of the reverse-conducting IGBT. Then for diode mode, FPGA is used to generate three-level control logic of ‑15, 15, 0V, and the three-level control logic is converted into gate voltage through the designed driving circuit to drive the reverse conduction IGBT; for dead zone and IGBT mode , using the traditional two-level drive. The invention has high speed and precision for judging the working mode of the reverse conduction IGBT, and low hardware cost. And the invention can solve the contradiction between the diode conduction loss and the dynamic loss, more effectively reduce the switching loss of the reverse conduction IGBT, and improve the driving safety.

Description

Reverse conduction IGBT driving method with three-level diode desaturation control

technical field

The invention relates to a reverse conduction IGBT driving technology, in particular to a reverse conduction IGBT driving method with three-level diode desaturation control.

Background technique

In recent years, IGBTs have gradually replaced thyristors due to their excellent comprehensive performance, and are widely used in many occasions: electric vehicles, light rail and other traction systems, power systems, home appliances and military weapons. The performance requirements of high power density, high voltage and strong current capacity have always driven the innovation of IGBTs, and various new IGBTs have emerged one after another. Among them, the reverse-conducting IGBT once became an international research hotspot due to its advantages of small structure size, high power density, low cost, small parasitic parameters and high reliability.

There are obvious differences with the structure of ordinary IGBT. The collector of the cell structure of the reverse conducting IGBT is no longer just the P+ region, but the P+ region and the N+ region that are crossed and mixed with each other. This structure is equivalent to the reverse in the ordinary IGBT structure. A diode is connected in parallel. When the collector-emitter of the IGBT is subjected to back pressure, its integrated anti-parallel diode conducts. Compared with ordinary IGBTs, the gate voltage of reverse-conducting IGBTs affects the static and dynamic losses of their integrated diodes, so diode modal control needs to be considered. When its diode freewheels, the gate is turned off to reduce the diode's on-voltage drop. Before the diode is turned off, the gate realizes desaturation control to reduce the reverse recovery loss of the diode, which is the key to the reverse-conducting IGBT drive technology. The two-level drive strategy cannot solve the contradiction between the dynamic loss and static loss of the diode, and the existing three-level drive cannot solve the problem of insufficient diode desaturation caused by the dead zone, resulting in the inability of the reverse conducting IGBT to fully exert its high efficiency during operation. The advantage of energy saving, so it is necessary to design a new three-level drive. However, there is currently no required three-level driver chip, which brings difficulties to the design of the driver circuit. Secondly, how to accurately detect the working mode of the RC-IGBT at high speed is the premise of the diode desaturation control. At present, there are two methods to judge the working mode of the reverse conducting IGBT: the direct method and the indirect method. The direct method is to detect the saturation tube voltage drop V _CE or the direction of the conduction current. Detecting the saturation tube voltage drop V _CE requires a diode with a very high reverse blocking voltage in high-voltage applications, and this diode requires a large creepage. The distance and reliability are not high, and many sensors are required to detect the current of the device, resulting in high cost. The indirect method is to indirectly infer the working mode of the reverse conduction IGBT by detecting the load current, but the detection speed of the traditional method is low and the accuracy is not high enough.

SUMMARY OF THE INVENTION

In order to overcome the above-mentioned two-level drive in the prior art that cannot solve the contradiction between the static and dynamic losses of the diode, and the shortcomings of slow recognition of the working state of the reverse conducting IGBT and insufficient precision, the present invention provides a three-level diode de-energizer. In the saturation-controlled reverse-conducting IGBT driving method, a high-speed Hall sensor is used to quickly and accurately detect the load current, and the working mode of the reverse-conducting IGBT is judged in real time, and the recognition speed and accuracy are significantly improved. Then, three-level gate voltages of -15, 15, and 0V are used to solve the contradiction between the dynamic and static losses of the integrated diode in the reverse conduction IGBT.

In order to realize the above-mentioned purpose of the invention, the present invention adopts the following technical solutions:

A reverse-conducting IGBT driving method for three-level diode desaturation control, characterized in that it comprises the following steps:

(1) The load current is detected according to the high-speed Hall sensor circuit, and the dead zone is set to generate the load current direction signal;

(2) According to the load current direction signal and the control signal input to the controller FPGA, determine the working mode of the upper and lower tubes of the bridge arm reverse conduction IGBT;

(3) According to the working mode of the reverse conduction IGBT, if it works in the IGBT and dead zone mode, the FPGA applies the control logic of the traditional IGBT, and if it works in the diode mode, it applies the three-level control logic;

(4) According to the control logic of the FPGA, a three-level drive circuit is used to convert the gate voltage to control the switch of the reverse conduction IGBT.

In step (1), the high-speed Hall sensor detection circuit is mainly composed of a high-speed Hall sensor, a signal amplification circuit and a hysteresis comparison circuit. Among them, the hysteresis comparison circuit adopts two high-speed comparators. When the output voltage U ₀ of the Hall sensor is rising, if U ₀ is greater than Vp+ , the output of the comparator 1 is 1; otherwise, the output is 0. If U ₀ If U 0 is greater than 0, the output of comparator 2 is 0, otherwise, the output is 1; when U ₀ is falling, if U ₀ is greater than Vp- , the output of comparator 1 is 1, otherwise, the output is 0, if U ₀ If it is greater than V _N ^- , the output of the comparator 2 is 0, otherwise, the output is 1; the logic signals 11, 10, 01 and 00 formed by the outputs of the comparators 1 and 2 constitute the load current direction signal. Among them, the dead zone is (0, Vp+ ) in the rising process of U ₀ and ( V _N - ,0) in the falling process of U ₀

In step (2), the way of judging the working mode of the reverse conducting IGBT by the load current direction signal is:

When the load current direction signal is 10, when the load current flows into the bridge arm, it is only possible that the upper tube is working in diode mode. Combined with the driving signal of the upper tube, if it is a rising edge, the upper tube must be working in diode freewheeling mode; When the load current direction signal is 01, when the load current flows out of the bridge arm, it is only possible that the lower tube works in the diode mode. Combined with the control signal of the lower tube, if it is a rising edge, the lower tube must work in the diode mode. When the load current direction signal is 11, or 00, the corresponding dead zone mode at this time;

In step (3), the three-level control logic is -15V, 15V and 0V. Taking the above tube as an example, the implementation method is:

When judging the upper tube as a diode, if the rising edge of the control signal comes, the output control logic is -15V; until the rising edge control signal of the lower tube comes, the timing t ₁ , the applied control logic is 15V. When the t1 _timing ends, the timing t2 , the application control logic is 0V , and the t2 _{timing ends} , the application control logic is -15V.

In step (4), the driving circuit is composed of the following circuit structure:

The three control pins of the FPGA are respectively connected to three high-speed optocouplers, level conversion chips, and then drive three MOS transistors Q ₁ , Q ₂ and Q ₃ , wherein Q ₁ is a P-type MOS, and Q ₂ and Q ₃ are N-type MOS. The gate-source of the MOS tube is connected to a large resistor to provide a parasitic capacitance discharge loop after power off. Q ₁ Q ₂ is then connected to the gate of the reverse conduction IGBT through the resistor R, and Q3 is connected to the gate through the resistor R and the reverse diode.

Compared with the closest prior art, the technical solution provided by the present invention has the following beneficial effects:

The invention can simplify the structure of the reverse conduction IGBT working mode identification circuit, and can detect the working mode of the reverse conduction IGBT accurately at high speed;

The invention adopts three-level driving, which can solve the contradiction between the static loss and dynamic loss of the diode, and fully solve the problem of insufficient desaturation of the diode.

Description of drawings

Fig. 1 is the drive circuit of the three-level diode desaturation control in the embodiment of the present invention;

Fig. 2 is a control flow chart of the three-level diode desaturation control drive in the embodiment of the present invention; Fig. 2(a) is a control flow chart of the three-level diode desaturation control drive in the embodiment of the present invention; Fig. 2(b) For the driving waveform and experimental circuit diagram;

FIG. 3 is a schematic diagram of the dead zone of the load current in the embodiment of the present invention.

Detailed ways

Taking the upper tube for driving the bridge arm of the reverse conducting IGBT as an example, the present invention will be further described in detail below with reference to the accompanying drawings.

1 is a drive circuit for three-level diode desaturation control in an embodiment of the present invention, which mainly includes an input PWM signal interface, an FPGA logic circuit, a load current detection circuit, a three-level drive circuit, and a reverse conducting IGBT bridge arm; the The input PWM signal interface is connected with the FPGA logic circuit; the FPGA logic circuit is connected with the input end of the three-level drive circuit; the output end of the three-level drive circuit is connected with the gate of the upper tube of the reverse conduction IGBT bridge arm connection; the input end of the load current detection circuit is connected to the midpoint M of the reverse conduction IGBT bridge arm; the output end of the load current detection circuit is connected to the FPGA logic circuit; the load current detection circuit includes a high-speed Hall sensor, signal amplification circuit and hysteresis comparison circuit; the input end of the high-speed Hall sensor is connected with the M point, and the output end of the high-speed Hall sensor is connected with the input end of the signal amplification circuit; the signal amplification The output end of the circuit is connected with the FPGA logic circuit. The three-level drive circuit includes three level generating circuits of 15V, 0V and 15V; the 15V level generating circuit consists of an optocoupler isolation circuit OP1, a driving chip U1, _a MOSFET gate resistor R1, _a P-type MOSFET and an IGBT Gate resistance R _{g ( off )} ; the -15V level generation circuit consists of optocoupler isolation circuit OP2, driver chip U ₂ (UCC27524), MOSFET gate resistance R ₂ , N-type MOSFET and IGBT gate resistance R _{g ( on )} ; the 0V level generating circuit consists of an optocoupler isolation circuit OP3, a driver chip _U3 , a MOSFET gate resistor _R3 , an N-type MOSFET and an IGBT gate resistor _{Rd ( off )} .

Fig. 2(a) is a control flow chart of the desaturation control driving of the three-level diode in the embodiment of the present invention; Fig. 2(b) is a driving waveform and an experimental circuit diagram. The three-level structure used in this paper is shown as VGE-1 in Figure 2(b). When the falling edge of the VT2 control signal of the lower tube comes, the upper tube acts as a freewheeling diode to keep the driving voltage of the upper tube at -15V. , in order to reduce the conduction voltage drop of the diode. When the rising edge of the lower tube control signal comes, the diode of the upper tube is about to be turned off. At this time, the upper tube gives the three-level desaturation pulse shown by VGE-1, first add 15V pulse, then add 0V as buffer, and finally set is -15V.

The specific implementation is as follows:

A reverse-conducting IGBT driving method for three-level diode desaturation control, characterized in that it comprises the following steps:

(1) The load current is detected according to the high-speed Hall sensor circuit, and the dead zone is set to generate the load current direction signal;

(2) According to the load current direction signal and the control signal input to the controller FPGA, determine the working mode of the upper and lower tubes of the bridge arm reverse conduction IGBT;

(3) According to the working mode of the reverse conduction IGBT, if it works in the IGBT and dead zone mode, the FPGA applies the control logic of the traditional IGBT, and if it works in the diode mode, it applies the three-level control logic;

(4) According to the control logic of the FPGA, a three-level drive circuit is used to convert the gate voltage to control the switch of the reverse conduction IGBT.

In step (1), the high-speed Hall sensor detection circuit is mainly composed of a high-speed Hall sensor, a signal amplification circuit and a hysteresis comparison circuit. Among them, the hysteresis comparison circuit adopts two high-speed comparators. When the output voltage U ₀ of the Hall sensor is rising, if U ₀ is greater than Vp+ , the output of the comparator 1 is 1; otherwise, the output is 0. If U ₀ If U 0 is greater than 0, the output of comparator 2 is 0, otherwise, the output is 1; when U ₀ is falling, if U ₀ is greater than Vp- , the output of comparator 1 is 1, otherwise, the output is 0, if U ₀ If it is greater than V _N ^- , the output of the comparator 2 is 0, otherwise, the output is 1; the logic signals 11, 10, 01 and 00 formed by the outputs of the comparators 1 and 2 constitute the load current direction signal. Among them, the dead zone is (0, Vp+ ) in the rising process of U ₀ and ( V _N - ,0) in the falling process of U ₀

In step (2), the way of judging the working mode of the reverse conducting IGBT by the load current direction signal is:

When the load current direction signal is 10, when the load current flows into the bridge arm, it is only possible that the upper tube is working in diode mode. Combined with the driving signal of the upper tube, if it is a rising edge, the upper tube must be working in diode freewheeling mode; When the load current direction signal is 01, when the load current flows out of the bridge arm, it is only possible that the lower tube works in the diode mode. Combined with the control signal of the lower tube, if it is a rising edge, the lower tube must work in the diode mode. When the load current direction signal is 11, or 00, the corresponding dead zone mode at this time;

In step (3), the three-level control logic is -15V, 15V and 0V. Taking the above tube as an example, the implementation method is:

When judging the upper tube as a diode, if the rising edge of the control signal comes, the output control logic is -15V; until the rising edge control signal of the lower tube comes, the timing t ₁ , the applied control logic is 15V. When the t1 _timing ends, the timing t2 , the application control logic is 0V , and the t2 _{timing ends} , the application control logic is -15V.

In step (4), the driving circuit is composed of the following circuit structure:

The three control pins of the FPGA are respectively connected to three high-speed optocouplers, level conversion chips, and then drive three MOS transistors Q ₁ , Q ₂ and Q ₃ , wherein Q ₁ is a P-type MOS, and Q ₂ and Q ₃ are N-type MOS. The gate-source of the MOS tube is connected to a large resistor to provide a parasitic capacitance discharge loop after power off. Q ₁ Q ₂ is then connected to the gate of the reverse conduction IGBT through the resistor R, and Q3 is connected to the gate through the resistor R and the reverse diode.

Fig. 3 is a schematic diagram of the dead zone of the load current in the embodiment of the invention. When the load current is small or even no-load, simply detecting the current direction through the Hall sensor will cause fluctuations and errors, resulting in frequent switching of modes. Affects the stable performance of the drive circuit, so it is necessary to set a dead zone for the judgment boundary. As shown in Figure 3. That is, the sampled voltage is compared with the two comparators. When it is greater than a certain value VP+, it is judged that the load current flows in, and when it is less than a certain value VN-, it is judged that the load current flows out. So there are three judgment areas, 11 indicates that the load current flows in; 00 indicates that the load current flows out; 01 or 10 indicates that the load current is in the dead zone, the current is small at this time, and the desaturation control is not meaningful, so this area The traditional PWM positive and negative level complementary control is used, that is, the upper and lower tubes work in the IGBT switch mode. The comparison value of comparator 1 from high to low is VP+, the comparison value when it changes from low to high is VP-=0, the comparison value when the output of comparator 2 changes from low to high is VN-, and the comparison value when it changes from high to low is The comparison value is VN+=0. Schematic diagram of dead zone for load current direction judgment. The current inflow is positive, and the dead zone is (0, Vp+ ) in the rising process of U ₀ and ( V _N - ,0) in the falling process of U ₀ .

Claims (4)

1. a reverse conduction IGBT driving method of three-level diode desaturation control, is characterized in that, comprises the steps: 1) Detect the load current, and set the dead zone to generate the load current direction signal; 2) According to the load current direction signal and the PWM signal input to the upper and lower tubes of the controller, determine the working mode of the upper and lower tubes of the reverse conducting IGBT bridge arm; 3) According to the working mode of the reverse conduction IGBT, if it works in the IGBT and dead zone mode, the controller applies the control logic of the traditional IGBT, and if it works in the diode mode, the three-level control logic of the controller is applied; 4) According to the three-level control logic of the controller, the three-level drive circuit outputs the three-level gate voltage to control the switch of the reverse conduction IGBT; Wherein, in step 1), a high-speed Hall sensor detection circuit is used to detect the load current; the high-speed Hall sensor detection circuit includes a high-speed Hall sensor, a signal amplification circuit and a hysteresis comparison circuit; the high-speed Hall sensor and the signal The signal amplifying circuit is connected with the hysteresis comparison circuit; wherein, the hysteresis comparison circuit adopts two high-speed comparators, and the two high-speed comparators are connected in parallel; in the process of the output voltage _U0 of the high-speed Hall sensor rising , if U ₀ is greater than the dead zone voltage upper limit Vp+ of the first high-speed comparator, the output of the first high-speed comparator is 1; otherwise, the output is 0; if U ₀ is greater than 0, the output of the second high-speed comparator is 0, otherwise, the output is 1; in the process of U ₀ falling, if U ₀ is greater than 0, the output of the first high-speed comparator is 1, otherwise, the output is 0, if U ₀ is greater than the dead zone of the second high-speed comparator voltage lower limit value V _N ^- , the output of the second high-speed comparator is 0, otherwise the output is 1; the logic signals 11, 10, 01 and 00 formed by the outputs of the first high-speed comparator and the second high-speed comparator, That is, the load current direction signal is formed; the dead zone is (0, Vp+) in the rising process of U ₀ and (V _N- , 0) in the falling process of U ₀ . 2. The reverse conduction IGBT driving method of three-level diode desaturation control according to claim 1, is characterized in that, in step 2), by load current direction signal and the PWM input to the upper and lower tubes of the controller The method of judging the working mode of the reverse-conducting IGBT is as follows: When the load current direction signal is 10, when the load current flows into the reverse conduction IGBT bridge arm, if it is a rising edge, the upper tube works in diode mode; when the load current direction signal is 01, the load current flows out of the reverse conduction IGBT bridge. When the arm is on, if it is a rising edge, the lower tube works in the diode mode; when the load current direction signal is 11 or 00, it corresponds to the dead zone mode. 3. The reverse conduction IGBT driving method of three-level diode desaturation control according to claim 1, is characterized in that, in step 3), three-level control logic is -15V, 15V and 0V, for upper tube, The specific control logic is: When it is judged that the upper tube is used as a diode, if the rising edge of the control signal of the upper tube comes, the output control logic is -15V; until the rising edge control signal of the lower tube comes, the timing t ₁ , the applied control logic is 15V; when t ₁ When the timing ends, the timing t ₂ , the application control logic is 0V, and when the t ₂ timing ends, the application control logic is -15V; for the lower tube, the specific control logic is: When judging that the lower tube is used as a diode, if the rising edge of the control signal of the lower tube comes, the output control logic is -15V; until the rising edge control signal of the upper tube comes, the timing t ₁ , the applied control logic is 15V; when t ₁ When the timing ends, the timing t ₂ , the application control logic is 0V, and when the t ₂ timing ends, the application control logic is -15V. 4 . The reverse-conducting IGBT driving method of three-level diode desaturation control according to claim 1 , wherein, in step 4), the three-level driving circuit comprises three High-speed optocoupler; the outputs of the three high-speed optocouplers are connected to the reverse conduction IGBT through the MOS tube.

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