CN109904110B

CN109904110B - Etching method and structure for forming vertical hole

Info

Publication number: CN109904110B
Application number: CN201711294826.3A
Authority: CN
Inventors: 何志宏; 林正忠; 林章申
Original assignee: SJ Semiconductor Jiangyin Corp
Current assignee: SJ Semiconductor Jiangyin Corp
Priority date: 2017-12-08
Filing date: 2017-12-08
Publication date: 2021-06-04
Anticipated expiration: 2037-12-08
Also published as: CN109904110A

Abstract

The present invention provides an etching method for forming vertical holes and a structure thereof. The method includes: providing a semiconductor substrate with an etching region for forming the vertical holes; and the laser etching step: performing laser etching on the semiconductor substrate to A first groove is formed in the etched area, and the first groove includes rough sidewalls and a bottom; the plasma etching step: plasma etching is performed on the sidewalls and the bottom of the first groove to form a second groove, At the same time, the rough structure of the sidewall and bottom of the first groove is removed, so that the second groove contains smooth sidewalls and bottom. In the present invention, the laser etching step and the plasma etching step are repeatedly performed, which shortens the process time, reduces the manufacturing cost, and at the same time can ensure that the inner surface of the obtained vertical hole is smooth; in addition, the width of the formed vertical through hole decreases in turn. Small structure, less damage to the surface of the device behind the vertical through hole, which can effectively improve the product yield.

Description

Etching method for forming vertical hole and structure thereof

Technical Field

The invention relates to the technical field of semiconductors, in particular to an etching method for forming a vertical hole and a structure thereof.

Background

With the development of semiconductor technology, the feature size of integrated circuits is continuously reduced, and the interconnection density of devices is continuously improved. The conventional two-dimensional package has not been able to meet the needs of the industry, and therefore Through Silicon Via (TSV) technology has been developed in the prior art, which has the advantages of short-distance interconnection, high-density integration and low cost, thereby gradually leading to the trend of package technology development.

Different from the traditional IC packaging bonding and the superposition technology using salient points, the through silicon via technology realizes the interconnection between chips by making vertical conduction between the chips and between the wafer, and the TSV can ensure that the stacking density of the chips in the three-dimensional direction is the maximum, the overall dimension is the minimum, and the chip speed and the performance of low power consumption are greatly improved.

Up to now, the hole etching process used for the back-end packaging of semiconductors is generally dry etching, which is divided into three types: physical, chemical, physicochemical. Physical etching is also called as sputter etching, and purely uses physical impact, anisotropic etching can be achieved, but selective etching cannot be performed and damage is easily caused to devices, for example, fig. 1 and fig. 2 show scanning electron microscope images of TSV holes formed by laser etching, wherein fig. 1 shows the top surface form of the TSV holes formed by laser etching under the scanning electron microscope, and fig. 2 shows the section form of the TSV holes in fig. 1.

The chemical etching utilizes chemical reaction between chemical active atomic groups in plasma and etched materials to realize the purpose of etching, and the etching effect is similar to that of wet etching due to the fact that the etching core is also chemical reaction (only the gas state of solution is not involved), so that the etching method has good selectivity, but has poor anisotropy, long processing time and high cost. Based on this, people compromise the two extreme processes to obtain a widely applied physical chemical etching technology, which has the advantages of good anisotropy and selectivity, but also has the problems of long processing time and high cost.

Another requirement for forming vias is that the walls of the vias to be formed are smooth and burr-free, and for this reason, a Bosch process for forming vias has been proposed that cycles alternately through etching steps and deposition steps until the desired etch depth is achieved, as shown in fig. 3 for a shell-type via formed using the Bosch process, where the sidewalls of the via are smooth, but require a longer process time and higher cost.

Therefore, it is necessary to research an etching method for forming a vertical hole, which can effectively shorten the process time for forming the vertical hole, reduce the process cost, and obtain a vertical hole with a smooth hole wall.

Disclosure of Invention

In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide an etching method for forming a vertical hole and a structure thereof, which are used to solve the problems of the prior art that the method for forming a vertical hole requires a long process time, a high manufacturing cost, or obtains a high roughness of the vertical hole wall, or easily damages the surface of the device after the vertical through hole when forming the vertical through hole.

To achieve the above and other related objects, the present invention provides an etching method for forming a vertical hole, the method at least comprising the steps of:

s1: providing a semiconductor substrate, wherein the semiconductor substrate is provided with an etching area for forming the vertical hole;

s2: laser etching step: presetting laser etching depth and laser etching width, and performing laser etching on the semiconductor substrate to form a first groove with first width and first depth in the etching area, wherein the first groove comprises a rough side wall and a rough bottom;

s3: plasma etching step: presetting a plasma etching depth and a plasma etching width, carrying out plasma etching on the side wall and the bottom of the first groove to form a second groove with a second width and a second depth, and simultaneously removing the rough structures on the side wall and the bottom of the first groove to enable the second groove to comprise a smooth side wall and a smooth bottom.

Preferably, the etching method further includes S4: and repeating the etching period consisting of the step S2 to the step S3 until the etching depth of the etching area reaches the target requirement, wherein the laser etching in each etching period is performed with the same center of circle.

Further, the etching cycle consisting of the steps S2 to S3 is repeatedly performed 1 time.

Further, when the second etching period is performed, the preset laser etching width is smaller than the second width formed in the first etching period.

Further, when the second etching period is performed, the preset laser etching width is equal to the preset laser etching width of the first etching period.

Preferably, between the steps S2 and S3, a cleaning step of the semiconductor substrate is further included to remove particles generated in the laser etching step.

Preferably, the semiconductor substrate is provided with a positioning mark, and the laser etching device automatically aligns to the etching region through the positioning mark when performing step S2.

Preferably, the semiconductor substrate includes at least one of the group consisting of silicon, silicon oxide, silicon nitride, and silicon oxynitride.

Preferably, the laser-etched laser source comprises at least one of the group consisting of a laser source of wavelength 473nm, a laser source of wavelength 532nm, a laser source of wavelength 556nm, a laser source of wavelength 635nm, a laser source of wavelength 671 nm.

Preferably, the plasma etching comprises at least one of the group consisting of Reactive Ion Etching (RIE) and high density plasma etching (HDP).

Further, the vertical hole includes one of the group consisting of a through hole and a blind hole.

In addition, the invention also provides a vertical hole structure manufactured by adopting the etching method for forming the vertical hole.

As described above, the etching method for forming a vertical hole and the structure thereof of the present invention have the following beneficial effects: the laser etching step is firstly carried out, then the plasma etching step is carried out, and the photoetching process is not required, so that the processing time of etching to form the vertical hole is integrally shortened, the manufacturing cost is reduced, and meanwhile, the smooth inner surface of the obtained vertical hole can be ensured, and the requirements of the subsequent process are met; in addition, during laser etching, the laser equipment is aligned with the etching area in a self-alignment mode, so that the process precision can be improved, and the process operation is simple and convenient; finally, after a plurality of etching cycles are repeatedly executed, the formed vertical through hole is of a structure with the width being reduced in sequence, the contact area of the structure and the metal layer M on the back of the device is small, and the plasma etching can quickly react, so that the damage to the surface of the device after the vertical through hole is small, and the product yield can be effectively improved.

Drawings

Fig. 1 shows a scanning electron microscope image of the top surface of a hole for forming a TSV hole by laser etching in the prior art.

Fig. 2 is a scanning electron microscope image of a cross section of the hole formed by the TSV hole formed by laser etching shown in fig. 1.

Fig. 3 shows a scanning electron micrograph of a side surface of a via hole in a shell type via hole formed by a Bosch process in the prior art.

Fig. 4 is a process flow chart showing a first embodiment of the etching method for forming a vertical hole according to the present invention.

Fig. 5-7 are schematic diagrams illustrating the formation stages of the etching method for forming a vertical hole according to the first embodiment of the present invention.

Fig. 8 is a process flow diagram illustrating a second embodiment of the etching method for forming a vertical hole according to the present invention.

Fig. 9-14 are schematic diagrams illustrating the formation stages of the etching method for forming a vertical hole according to the second embodiment of the present invention.

Fig. 15 is a schematic view showing the application of the etching method for forming a vertical hole according to the present invention in a CMOS image sensor.

Description of the element reference numerals

1 semiconductor substrate

11 etching area

2 first groove

W1 first width

D1 first depth

21 first groove side wall

22 first groove bottom

3 second groove

W2 second width

D2 second depth

31 second groove side wall

32 second groove bottom

4 vertical hole

5 third groove

W3 third Width

Third depth D3

51 third groove side wall

52 third groove bottom

6 fourth groove

W4 fourth Width

Fourth depth D4

61 fourth groove side wall

62 fourth groove bottom

7 circuit area

M metal layer

S11-S13

S21-S24

Detailed Description

The following description of the embodiments of the present invention is provided for illustrative purposes, and other advantages and effects of the present invention will become apparent to those skilled in the art from the present disclosure.

Please refer to fig. 4 to fig. 15. It should be understood that the structures, ratios, sizes, and the like shown in the drawings and described in the specification are only used for matching with the disclosure of the specification, so as to be understood and read by those skilled in the art, and are not used to limit the conditions under which the present invention can be implemented, so that the present invention has no technical significance, and any structural modification, ratio relationship change, or size adjustment should still fall within the scope of the present invention without affecting the efficacy and the achievable purpose of the present invention. In addition, the terms "upper", "lower", "left", "right", "middle" and "one" used in the present specification are for clarity of description, and are not intended to limit the scope of the present invention, and the relative relationship between the terms and the terms is not to be construed as a scope of the present invention.

The invention provides an etching method for forming a vertical hole, which at least comprises the following steps:

In order to understand the present invention, preferred embodiments will be listed in the following description in order to explain the technical solution proposed by the present invention.

Example one

The following describes an etching method for forming a vertical hole according to the present invention, with reference to the process flow shown in fig. 4 and the schematic diagrams of the forming stages shown in fig. 5 to 7 as a first embodiment, where the method includes the following steps:

as shown in fig. 4 and 5, step 1) S11 is performed first, and a semiconductor substrate 1 is provided, where the semiconductor substrate 1 has an etching region 11 for forming the vertical hole.

As an example, the semiconductor substrate 1 includes at least one of the group consisting of silicon, silicon oxide, silicon nitride, and silicon oxynitride. It is understood that the semiconductor substrate 1 may also comprise other materials, as long as the subsequent laser etching and plasma etching can effectively etch.

As shown in fig. 4 and 6, step 2) S12 is then performed, and the laser etching step: presetting a laser etching depth and a laser etching width, and performing laser etching on the semiconductor substrate 1 to form a first groove 2 with a first width W1 and a first depth D1 in the etching area 11, wherein the first groove 2 comprises a rough first groove side wall 21 and a first groove bottom 22.

As an example, the laser etched laser source includes at least one of the group consisting of a laser source of wavelength 473nm, a laser source of wavelength 532nm, a laser source of wavelength 556nm, a laser source of wavelength 635nm, a laser source of wavelength 671 nm.

Preferably, the semiconductor substrate 1 is provided with a positioning mark, and the laser etching device can automatically align to the etching area 1 through the positioning mark during the step, so that the process precision is improved, and the process operation is simple and convenient.

As shown in fig. 4 and 7, step 3) S13 is performed, and the plasma etching step: presetting a plasma etching depth and a plasma etching width, carrying out plasma etching on a first groove side wall 21 and a first groove bottom 22 of the first groove 2 to form a second groove 3 with a second width W2 and a second depth D2, and simultaneously removing the rough structures of the first groove side wall 21 and the first groove bottom 22 to enable the second groove 3 to comprise a smooth second groove side wall 31 and a smooth second groove bottom 32.

As an example, between step 12) and step 13), a cleaning step of the semiconductor substrate 1 is further included to remove particles generated in the laser etching step. The semiconductor substrate 1 may be cleaned with pure water, acetone, isopropyl alcohol, a weak base or a weak acid solution, or may be cleaned with other solutions having a cleaning function and not corroding the semiconductor substrate 1.

As an example, the plasma etching includes at least one of the group consisting of Reactive Ion Etching (RIE) and high density plasma etching (HDP).

After the step 13), the etching depth of the etching region 11 reaches the target requirement, so that the vertical hole 4 is formed. According to specific circumstances, the vertical hole 4 may be etched to be one of a group consisting of a through hole and a blind hole, when the blind hole needs to be manufactured, as shown in fig. 7, the vertical hole 4 does not penetrate through the etching region 11, and rough structures on the side wall 21 and the bottom 22 of the first groove in the laser etching step are removed through the plasma etching step, so as to form the vertical hole 4 with smooth side wall and bottom; when a through hole needs to be made, the vertical hole 4 penetrates the etching region 11. According to the etching method for forming the vertical hole, by using the anisotropic laser etching method, the first groove 2 with a certain depth can be quickly formed on the semiconductor substrate 1 due to the high speed rate of laser etching, then the rough structures generated on the side wall 21 and the bottom 22 of the first groove during the laser etching are removed by combining with plasma etching, the process time for etching the vertical hole is integrally shortened, the manufacturing cost is reduced, meanwhile, the smooth inner surface of the obtained vertical hole can be ensured, and the subsequent process requirements are met. In addition, during laser etching, the laser etching device is aligned with the etching area in a self-alignment mode, so that the process precision can be improved, and the process operation is simple and convenient.

Example two

Another etching method for forming a vertical hole according to the present invention is described below with reference to the process flow shown in fig. 8 and the schematic diagrams of the forming stages shown in fig. 9 to 14 as an embodiment two, where the method includes the following steps:

as shown in fig. 8 and 9, step 1) S21 is performed first, and a semiconductor substrate 1 is provided, where the semiconductor substrate 1 has an etching region 11 for forming the vertical hole.

As shown in fig. 8 and 10, step 2) S22 is then performed, and the laser etching step: presetting a laser etching depth and a laser etching width, and performing laser etching on the semiconductor substrate 1 to form a first groove 2 with a first width W1 and a first depth D1 in the etching area 11, wherein the first groove 2 comprises a rough first groove side wall 21 and a first groove bottom 22.

As shown in fig. 8 and 11, step 3) S23 is performed, and the plasma etching step: presetting a plasma etching depth and a plasma etching width, carrying out plasma etching on a first groove side wall 21 and a first groove bottom 22 of the first groove 2 to form a second groove 3 with a second width W2 and a second depth D2, and simultaneously removing the rough structures of the first groove side wall 21 and the first groove bottom 22 to enable the second groove 3 to comprise a smooth second groove side wall 31 and a smooth second groove bottom 32.

As shown in fig. 8, step 4) S24 is performed, and the etching period composed of step 2) to step 3) is repeatedly performed until the etching depth of the etching area 11 reaches the target requirement, where the laser etching in each etching period is performed with the same center.

For convenience of understanding, the following description will be made in detail by taking as an example that the etching period consisting of step 2) to step 3) is repeatedly performed 1 time.

As shown in fig. 8 and 12, step 2) S22 is performed, and the laser etching step: presetting a laser etching depth and a laser etching width, and performing laser etching on the semiconductor substrate 1 to form a third groove 5 with a first width W3 and a first depth D3 in the etching region 11, wherein the third groove 5 comprises a rough third groove side wall 51 and a third groove bottom 52.

As shown in fig. 12, when the etching cycle is performed, the laser etching width is preset to be smaller than the second width W2 of the second groove 3 formed in the previous etching cycle. As a preferable example, when the etching period is performed, the laser etching width is preset to be equal to a preset laser etching width of a previous etching period.

As shown in fig. 8 and 13, step 3) S23 is performed, and the plasma etching step: presetting a plasma etching depth and a plasma etching width, carrying out plasma etching on a third groove side wall 51 and a third groove bottom 52 of the third groove 5 to form a fourth groove 6 with a fourth width W4 and a fourth depth D4, and simultaneously removing rough structures of the third groove side wall 51 and the third groove bottom 52 to enable the fourth groove 6 to comprise a smooth fourth groove side wall 61 and a smooth fourth groove bottom 62.

As shown in fig. 13, by performing the above two etching cycles, the target requirement for the etching depth of the etching region 11 is achieved, so that a vertical blind via 4 is formed in the semiconductor substrate 1.

As shown in fig. 14, by performing the above-mentioned two etching cycles, the target requirement of penetrating the etching region 11 is achieved, so that a vertical via 4 is formed in the semiconductor substrate 1, and the vertical via 4 is in contact with the metal layer M. The vertical through holes 4 are in a concentric circle structure, the width of the part, far away from the metal layer M, of each vertical through hole 4 is larger, and the width of the part, close to the metal layer M, of each vertical through hole 4 is smaller. After a plurality of etching cycles are repeatedly executed, the formed vertical through holes are of a structure with the width sequentially reduced, the contact area of the structure and the metal layer M on the back of the device is small, and the plasma etching can quickly reflect that the etching area 11 is penetrated, so that the damage to the surface (the metal layer M) of the device behind the vertical through hole 4 is small, and the product yield can be effectively improved.

Through the above description, the etching method for forming the vertical hole provided by the invention is explained, and the number of etching cycles can be selected according to actual conditions in the using process. The method can be applied to all semiconductor device fields, for example, can be effectively applied to the manufacturing process of a CMOS image sensor, as shown in fig. 15, the method can be effectively applied to a circuit region 7 of the CMOS image sensor, and a vertical hole 4 intercommunicating with a metal layer M in the circuit region 7 can be formed by the method to form an interconnection structure of electrodes.

In summary, the present invention provides an etching method for forming a vertical hole and a structure thereof, wherein the method at least comprises the following steps: s1, providing a semiconductor substrate, wherein the semiconductor substrate is provided with an etching area for forming the vertical hole; s2, laser etching step: presetting laser etching depth and laser etching width, and performing laser etching on the semiconductor substrate to form a first groove with first width and first depth in the etching area, wherein the first groove comprises a rough side wall and a rough bottom; s3, plasma etching step: presetting a plasma etching depth and a plasma etching width, carrying out plasma etching on the side wall and the bottom of the first groove to form a second groove with a second width and a second depth, and simultaneously removing the rough structures on the side wall and the bottom of the first groove to enable the second groove to comprise a smooth side wall and a smooth bottom. According to the invention, the laser etching step is firstly carried out, then the plasma etching step is carried out, and the photoetching process is not required, so that the processing time of etching to form the vertical hole is integrally shortened, the manufacturing cost is reduced, and meanwhile, the smooth inner surface of the obtained vertical hole can be ensured, and the requirements of the subsequent process are met; in addition, during laser etching, the laser equipment is aligned with the etching area in a self-alignment mode, so that the process precision can be improved, and the process operation is simple and convenient; finally, after a plurality of etching cycles are repeatedly executed, the formed vertical through hole is of a structure with the width being reduced in sequence, the contact area of the structure and the metal layer M on the back of the device is small, and the plasma etching can quickly react, so that the damage to the surface of the device after the vertical through hole is small, and the product yield can be effectively improved. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.

The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.

Claims

1. an etching method for forming a vertical hole, wherein the method at least comprises the following steps:

S1: Provide a semiconductor substrate, the semiconductor substrate has an etching region for forming vertical holes;

S2: Laser etching step: preset laser etching depth and laser etching width, and perform laser etching on the semiconductor substrate to form a first groove with a first width and a first depth in the etching area , the first groove includes rough sidewalls and a bottom;

S3: Plasma etching step: presetting the plasma etching depth and plasma etching width, and performing plasma etching on the sidewall and bottom of the first groove to form a second width and a second depth the second groove, while removing the rough structure of the sidewall and bottom of the first groove, so that the second groove contains smooth sidewalls and bottom;

S4: Repeat the etching cycle consisting of steps S2 to S3 until the etching depth of the etching region reaches the target requirement, wherein the laser etching in each etching cycle is performed with The same circle center is etched, and when the next etching cycle is performed, the preset width of the laser etching is smaller than the second width formed in the previous etching cycle, so that the formed vertical The hole has a structure with a decreasing width in turn, the contact area between the structure and the metal layer behind the vertical hole is small, and the plasma etching can quickly respond to the etching area, and the damage to the metal layer is small.

2 . The etching method for forming a vertical hole according to claim 1 , wherein the etching cycle consisting of steps S2 to S3 is repeated once. 3 .

3 . The etching method for forming a vertical hole according to claim 2 , wherein when the second etching cycle is performed, the preset width of the laser etching is smaller than that of the first etching cycle. 4 . the second width formed.

4 . The etching method for forming vertical holes according to claim 3 , wherein when the second etching cycle is performed, the preset width of the laser etching is equal to the first etching cycle. 5 . The preset laser etch width of .

5 . The etching method for forming a vertical hole according to claim 1 , wherein between the step S2 and the step S3 , a cleaning step of the semiconductor substrate is further included in order to remove the laser etching step. 6 . particle.

6 . The etching method for forming a vertical hole according to claim 1 , wherein positioning marks are provided on the semiconductor substrate, and when step S2 is performed, the laser etching equipment automatically aligns the position marks through the positioning marks. 7 . the etched area.

7 . The etching method for forming a vertical hole according to claim 1 , wherein the semiconductor substrate comprises at least one selected from the group consisting of silicon, silicon oxide, silicon nitride, and silicon oxynitride. 8 .

8. The etching method for forming a vertical hole according to claim 1, wherein the laser source for the laser etching comprises a laser source with a wavelength of 473 nm, a laser source with a wavelength of 532 nm, a laser source with a wavelength of 556 nm, and a laser source with a wavelength of 556 nm. At least one of the group consisting of a 635nm laser source and a 671nm wavelength laser source.

9 . The etching method for forming vertical holes according to claim 1 , wherein the plasma etching comprises a group consisting of reactive ion etching (RIE) and high density plasma etching (HDP). 10 . at least one of the group.

10 . The etching method for forming a vertical hole according to claim 1 , wherein the vertical hole comprises one of the group consisting of a through hole and a blind hole. 11 .

11. A vertical hole structure fabricated by the etching method for forming a vertical hole according to any one of claims 1-10.