CN109904065B - Preparation methods of heterostructures - Google Patents
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- CN109904065B CN109904065B CN201910129433.XA CN201910129433A CN109904065B CN 109904065 B CN109904065 B CN 109904065B CN 201910129433 A CN201910129433 A CN 201910129433A CN 109904065 B CN109904065 B CN 109904065B
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Abstract
本发明提供一种异质结构的制备方法，包括如下步骤：提供第一衬底，具有离子注入面；自离子注入面进行离子注入，以形成缺陷层；提供第二衬底，具有键合面，将键合面与离子注入面进行键合，得到初始键合结构；基于局部加热的方式对初始键合结构进行加热处理，以沿缺陷层剥离部分第一衬底，以在第二衬底上形成一衬底薄膜，得到包括第二衬底及衬底薄膜的异质结构。本发明基于局部加热的方式实现最终异质结构的制备，局部加热退火工艺可以降低键合结构中的热应力，提高制备过程中异质键合结构的稳定性，从而降低异质键合结构在退火剥离过程中的整体热应力和翘曲，本发明制备的单晶功能薄膜可以用于制备高性能的声学、光学和电学器件及各类传感器件等。
The present invention provides a method for preparing a heterostructure, comprising the following steps: providing a first substrate with an ion implantation surface; performing ion implantation from the ion implantation surface to form a defect layer; and providing a second substrate with a bonding surface , the bonding surface and the ion implantation surface are bonded to obtain the initial bonding structure; the initial bonding structure is heated based on local heating, so as to peel off part of the first substrate along the defect layer, so that the second substrate can be A substrate film is formed thereon to obtain a heterostructure including a second substrate and the substrate film. The invention realizes the preparation of the final heterostructure based on the local heating method, and the local heating annealing process can reduce the thermal stress in the bonding structure, improve the stability of the heterobonding structure in the preparation process, thereby reducing the amount of the heterobond structure in the process of preparation. The overall thermal stress and warpage in the process of annealing and peeling, the single-crystal functional film prepared by the invention can be used for preparing high-performance acoustic, optical and electrical devices and various sensing devices.
Description
Technical Field
The invention belongs to the technical field of semiconductor material preparation, and particularly relates to a preparation method of a heterostructure.
Background
At present, the ion beam stripping technology is used for preparing a heterostructure, such as a heterogeneous integrated single crystal thin film substrate, and is a promising technical scheme. Compared with the traditional heteroepitaxy technology, the single crystal film prepared by the ion beam stripping method has better crystal quality. In addition, the method has no requirement for epitaxial matching with respect to bonded heterostructures such as a support substrate and a functional thin film, and thus, can realize production of a desired thin film on almost any substrate.
However, the biggest problem in the ion beam lift-off technology is the need of heat lift-off to the hetero-bonded structure, because the hetero-bonded materials have thermal expansion coefficient mismatch, the common annealing method can introduce huge thermal stress into the hetero-bonded structure and even cause the bonded structure to be cracked, and the conventional annealing technology has great limitation in the preparation of the hetero-structure by the ion beam lift-off.
Therefore, how to provide a method for fabricating a heterostructure is necessary to solve the above problems in the prior art.
Disclosure of Invention
In view of the above-mentioned shortcomings of the prior art, the present invention aims to provide a method for fabricating a heterostructure, which is used to solve the problems of stress introduction and even cracking of the bonded structure caused by heating in the ion beam stripping process in the prior art.
To achieve the above and other related objects, the present invention provides a method for fabricating a heterostructure, comprising the steps of:
1) providing a first substrate, wherein the first substrate is provided with an ion implantation surface;
2) performing ion implantation on the first substrate from the ion implantation surface to form a defect layer in the first substrate;
3) providing a second substrate, wherein the second substrate is provided with a bonding surface, and bonding the bonding surface and the ion implantation surface to obtain an initial bonding structure; and
4) and carrying out heating treatment on the initial bonding structure based on a local heating mode so as to peel off part of the first substrate along the defect layer, so that part of the first substrate is transferred onto the second substrate to form a substrate film on the second substrate, and obtaining the heterostructure comprising the second substrate and the substrate film.
As an alternative of the present invention, in step 4), the local heating includes at least one of heat conduction heating and radiation heating.
As an alternative of the present invention, in step 4), the local heating may be performed by at least one of scanning heating and stepping heating, wherein the local heating path includes any one of a circular path, a zigzag path, and a polar path.
As an alternative of the present invention, in step 4), the local heating is performed in units of scan region units, wherein, in the local heating, the heating time for performing the heating process on the initial bonding structure corresponding to each scan region unit is the same.
As an alternative of the invention, in step 4), the maximum size of the scanning area unit is between 0.5mm and 10 mm; the heating time corresponding to each scanning area unit is between 1s and 20 s.
As an alternative of the present invention, step 4) further includes the steps of: and cooling the unheated area during the local heating.
As an alternative of the present invention, the cooling process is performed by at least one of heat sink technology and active cooling.
As an alternative of the present invention, in step 1), the first substrate is selected from at least one of silicon, silicon oxide, sapphire, germanium, lithium niobate, lithium tantalate, silicon carbide, gallium nitride and aluminum nitride, and in step 3), the second substrate is selected from at least one of silicon, silicon oxide, sapphire, germanium, lithium niobate, lithium tantalate, silicon carbide, gallium nitride and aluminum nitride, and the first substrate is different from the second substrate.
As an alternative of the present invention, in step 4), the heating process includes a step of performing bulk heating after performing the local heating.
As an alternative of the present invention, the initial bonding structure includes a central region and an outer region located at a periphery of the central region, wherein the step of performing the heat treatment includes: and heating the outer area by adopting the local heating mode, and heating the central area by adopting the integral heating mode.
As described above, the method for manufacturing a heterostructure of the present invention has the following advantageous effects:
the invention provides a preparation method of a heterostructure, in the preparation of the heterostructure, the preparation of the final heterostructure is realized based on a local heating mode, a local heating annealing process can reduce the thermal stress in a bonding structure, and the stability of the heterostructure in the preparation process is improved, so that the overall thermal stress and warpage of the heterostructure in the annealing and stripping process are reduced, and in addition, the single crystal functional film prepared by the invention can be used for preparing high-performance acoustic, optical and electrical devices, various sensing devices and the like.
Drawings
FIG. 1 shows a flow chart of a heterostructure fabrication process of the present invention.
Fig. 2 shows a schematic structural view of providing a first substrate in the preparation of the heterostructure of the present invention.
Fig. 3 is a schematic structural diagram of ion implantation performed on a first substrate in the preparation of the heterostructure of the present invention.
Fig. 4 shows a schematic structure diagram of providing a second substrate in the preparation of the heterostructure of the present invention.
FIG. 5 is a diagram illustrating bonding of a first substrate and a second substrate to form an initial bonded structure for heterostructure fabrication in accordance with the present invention.
FIG. 6 is a schematic diagram illustrating the peeling of a portion of a first substrate during the fabrication of a heterostructure of the present invention.
FIG. 7 shows a schematic diagram of the heterostructure obtained in the preparation of the heterostructure of the present invention.
FIG. 8 is a schematic diagram of a local heating structure in the fabrication of a heterostructure according to the present invention.
Fig. 9 shows an example of a path for local heating in the fabrication of a heterostructure according to the present invention.
Fig. 10 shows another example of a path for local heating in the fabrication of a heterostructure according to the present invention.
FIG. 11 is a schematic diagram of local heating and simultaneous cooling in the preparation of the heterostructure of the present invention.
Fig. 12(a) shows a schematic diagram of shear stress in the fabrication of a prior art heterostructure.
Fig. 12(b) shows a schematic diagram of deformation in the preparation of a heterostructure of the prior art.
Fig. 13(a) shows a schematic shear stress diagram in the fabrication of a heterostructure based on local annealing according to the present invention.
Fig. 13(b) shows a schematic diagram of deformation in the fabrication of a heterostructure based on local annealing according to the present invention.
Description of the element reference numerals
100 first substrate
100a ion implantation surface
101 defective layer
102 film of substrate
103 stripping remainder
200 second substrate
200a bonding surface
300 initial bonding structure
301 heterostructure
400 scan area unit
500 cooling processing device
S1-S4 Steps 1) to 4)
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Please refer to fig. 1 to fig. 13 (b). It should be noted that the drawings provided in the present embodiment are only schematic and illustrate the basic idea of the present invention, and although the drawings only show the components related to the present invention and are not drawn according to the number, shape and size of the components in actual implementation, the form, quantity and proportion of the components in actual implementation may be changed arbitrarily, and the layout of the components may be more complicated.
The first embodiment is as follows:
as shown in fig. 1, the present invention provides a method for preparing a heterostructure, comprising the steps of:
1) providing a first substrate, wherein the first substrate is provided with an ion implantation surface;
2) performing ion implantation on the first substrate from the ion implantation surface to form a defect layer in the first substrate;
3) providing a second substrate, wherein the second substrate is provided with a bonding surface, and bonding the bonding surface and the ion implantation surface to obtain an initial bonding structure; and
4) and carrying out heating treatment on the initial bonding structure based on a local heating mode so as to peel off part of the first substrate along the defect layer, so that part of the first substrate is transferred onto the second substrate to form a substrate film on the second substrate, and obtaining the heterostructure comprising the second substrate and the substrate film.
The method for fabricating the heterostructure of the present invention will be described in detail with reference to the accompanying drawings.
First, as shown in S1 of fig. 1 and fig. 2, step 1) is performed to provide a first substrate 100, and the first substrate 100 has an ion implantation surface 100 a.
As an example, in step 1), the first substrate 100 is selected from at least one of silicon, silicon oxide, sapphire, germanium, lithium niobate, lithium tantalate, silicon carbide, gallium nitride, and aluminum nitride.
Specifically, the first substrate 100 is a wafer substrate required for forming a heterostructure, and in one example, the first substrate 100 includes a single crystal substrate, and the first substrate 100 may be a piezoelectric material, and in one example, the first substrate 100 may be selected from one of silicon, silicon oxide, sapphire, germanium, lithium niobate, lithium tantalate, silicon carbide, gallium nitride, and aluminum nitride, or a stacked structure of at least two of the above materials, and may be other substrates known to those skilled in the art that can form a heterostructure.
Next, as shown in S2 in fig. 1 and fig. 3, step 2) is performed to perform ion implantation from the ion implantation surface 100a into the first substrate 100, so as to form a defect layer 101 in the first substrate 100.
Specifically, in one example, the ion implantation is performed by any one of hydrogen ion implantation, helium ion implantation, and hydrogen-helium ion co-implantation. The ion implantation is performed, so that a defect layer 101 may be formed at a preset depth of the first substrate 100, so as to realize material peeling at the defect layer, where the preset depth is a distance between the defect layer 101 formed after the ion implantation and the ion implantation surface 100a of the first substrate 100, and is set according to a film heterostructure actually required to be prepared, and when the ions are implanted from the ion implantation surface, the energy of the ion implantation is sufficient to make the implanted ions reach the preset depth, and the defect layer is formed at the preset depth.
In addition, the ion implantation may be performed by a single hydrogen ion implantation or a single helium ion implantation, or by a co-implantation of two ions, and when the two ion co-implantation methods are employed, the implantation sequence of the two ions may be adjusted according to actual requirements, that is, the implantation of the hydrogen ion may be performed before the implantation of the helium ion, after the implantation of the helium ion, or simultaneously with the implantation of the helium ion.
In one example, a single type of ion implantation is performed at the ion implantation surface 100a, and the implanted ions are hydrogen (H) ions, which can be achieved by utilizing the principle that the hydrogen ions can damage the crystal lattice deep in the lift-off (i.e., the defect layer 101) in the subsequent lift-off of the first substrate 100. I.e. during ion implantationIn the process of ion implantation, ions enter into atomic gaps to form micro defects, an implantation defect layer formed by ion implantation is mostly a nano-scale cavity defect, a material still has strong mechanical strength at the interface, the micro defects are aggregated and combined in the subsequent treatment process to form a platform-type defect, and the depth of the implantation defect layer is determined by the energy of the ion implantation, and whether the defect density required by separation can be formed is determined by the dose of the ion implantation, so that the proper ion implantation dose and the proper ion implantation energy are selected in the ion implantation process. In one example, the first substrate 100 is a lithium tantalate substrate, the energy of the ion implantation of hydrogen ions is 20keV to 180keV, and the implantation dose of the ion implantation of hydrogen ions is 5 × 1016cm-2～1×1017cm-2The injection temperature is room temperature.
In another example, co-implantation of two types of ions is performed at the ion implantation surface, the implanted ions being hydrogen ions and helium ions, wherein, in one mode, the hydrogen ions are used to form defects as described above, the defects being gaussian distributed within the defect layer; the helium ions belong to inert elements, can be captured by the platform defects formed by the hydrogen ions, and expand and combine the platform defects through physical action to finally form cracks capable of separating the wafer substrate, so that the partial wafer substrate is promoted to be stripped from the position with the maximum defect concentration. And co-implanting hydrogen ions and helium ions on the implantation surface, wherein the helium ions can be captured by the defects formed by the hydrogen ions and then enter the atomic gap and exert pressure, which is equivalent to exerting an additional acting force in the defects generated by the hydrogen ions, so that part of the wafer substrate can be effectively promoted to be stripped under the condition of low ion implantation dosage, the total ion implantation dosage can be effectively reduced, the preparation period is further shortened, and the production cost is saved.
In an alternative example, the helium ion implantation is performed in order to make the implanted helium ions easily trapped by the defects formed by the hydrogen ions, or the implanted hydrogen ions easily trapped by the defects formed by the helium ionsThe depth of the implantation is the same as or similar to the depth of the hydrogen ion implantation, i.e. the range (Rp) of the helium ions is ensured to be near the range of the hydrogen ion implantation. In the example, the energy of the co-implantation of the hydrogen ions and the helium ions is 10 keV-100 keV, and the ion beam current of the co-implantation of the hydrogen ions and the helium ions is 1 muA-100 mA; the implantation dosage of the hydrogen ion and the helium ion co-implantation is 2 × 1016cm-2～10×1016cm-2And the temperature of the hydrogen ions and the helium ions is room temperature.
Next, as shown in S3 in fig. 1 and fig. 4-5, step 3) is performed to provide a second substrate 200, where the second substrate 200 has a bonding surface 200a, and the bonding surface 200a is bonded to the ion implantation surface 100a to obtain an initial bonding structure 300.
As an example, the second substrate 200 is selected from at least one of silicon, silicon oxide, sapphire, germanium, lithium niobate, lithium tantalate, silicon carbide, gallium nitride, and aluminum nitride, and the first substrate 100 is different from the second substrate 200
Specifically, in this step, a second substrate bonded to the first substrate 100 is provided, and the second substrate 200 may be one of the material layers, or may be a stacked structure of two or more of the material layers, or may be any substrate known to those skilled in the art, for example, in an alternative example, the second substrate 200 is selected to be a silicon substrate, and the first substrate 100 is selected to be a lithium niobate substrate.
In addition, any surface of the second substrate 200 is selected as the bonding surface, which may be an upper surface or a lower surface thereof, in this example, the upper surface of the second substrate 200 is selected as the bonding surface 200a, and in addition, in an alternative example, the bonding manner to obtain the initial bonding structure 300 includes normal temperature bonding, for example, Ultra-high vacuum bonding (Ultra-high vacuum bonding), firstly removing the oxide films on the surfaces of the first substrate and the second substrate in an ultrahigh vacuum environment, enabling the first bonding surface and the second bonding surface after clean polishing to be in close enough contact, by intermolecular forces (van der waals forces or hydrogen bonding) between the interfaces of adjacent materials, the distance between two surface atoms is further reduced, thereby forming a covalent bond directly at the interface to achieve the bonding of the first substrate 100 and the second substrate 200. .
Finally, as shown in S4 in fig. 1 and fig. 6-11, step 4) is performed to perform a heating process on the initial bonded structure 300 based on a local heating manner to peel off a portion of the first substrate 100 along the defect layer 101, so that a portion of the first substrate 100 is transferred onto the second substrate 200 to form a substrate film 102 on the second substrate 200, thereby obtaining a heterostructure 300 including the second substrate 200 and the substrate film 102.
Specifically, the first substrate 100 is peeled off along the defect layer 101 in this step, wherein the present invention is based on a local heating method, i.e. a heating method of the initial bonding structure during peeling is not a completely conventional method of heating the entire initial bonding structure, but a method of heating a part of the initial bonding structure gradually, for example, heating the initial bonding structure 300 from the surface of the first substrate 100 on the side opposite to the ion implantation surface 100a, the local heating method is different from heating the entire surface at the same time, but heating a part of the surface, and gradually moving the heat source to peel off the first substrate, wherein the magnitude and distribution of the thermal stress are related to the geometric dimension of the heating structure, and the smaller the magnitude is the thermal stress, thus, localized heating can shrink the heating structure compared to conventional wafer level annealing, thereby reducing thermal stress, and the present invention utilizes localized heating to limit thermal stress and strip material at implanted defect layers. In addition, after the substrate film 102 is transferred to the second substrate 200, the remaining first substrate, i.e. the peeling residue 103, can be recycled after being processed, for example, as the first substrate 100 in fig. 2.
As an example, in step 4), the local heating includes at least one of heat conduction heating and radiation heating.
Specifically, in an example, the local heating may be performed by thermal conduction, preferably by contact thermal conduction, such as using a thermally conductive metal rod, such as a copper metal rod, to contact the initial bonding substrate 300 to transfer heat to the initial bonding structure, where the metal rod serves as a heating head for local heating; the local heating may also be performed by means of thermal radiation, such as by means of infrared radiation.
As an example, in step 4), the local heating may be performed by at least one of scanning heating and stepping heating.
As an example, the path of the local heating includes any one of a circular path, a zigzag path, and a polar path.
Specifically, the local heating may be performed by continuous scanning or may be performed in an intermittent step-by-step manner, so that the uniformity of heating of the entire structure can be maintained. In the local heating in the above manner, the heating of the initial bonding structure can be realized by a heating head, wherein the heating head can scan along a circular line, as shown in fig. 9, or move along a zigzag line, or scan along a serpentine line, as shown in fig. 10, or scan along a polar line, or scan along a serpentine line, or scan along a polar line, as shown in an example
As an example, in step 4), the local heating is performed in units of scanning area units 400, wherein the heating time for performing the heating process on the initial bonding structure corresponding to each scanning area unit 400 is the same during the local heating.
As an example, in step 4), the maximum size of the scanning area unit 400 is between 0.5mm and 10 mm.
As an example, the heating time for each of the scan region units 400 is between 1s and 20 s.
Specifically, in an example, the local heating is performed in units of scanning area units 400, where the scanning area unit 400 refers to an area corresponding to the initial bonding structure, and in an example, the initial bonding structure 300 is heated from a surface of the first substrate 100 on a side opposite to the ion implantation surface 100a, and the scanning area unit refers to one area unit on the surface, as shown in fig. 8, where in an example, the scanning area unit 400 also corresponds to a portion where a heating head contacts the initial bonding structure, and the heating head moves, i.e., the scanning area unit moves, so as to achieve heating of a required heating area, and in an example, the scanning area units move while calculating by overlapping thermal field distributions, i.e., simulating and calculating a thermal field of each scanning area unit, and performing superposition calculation of the thermal fields to obtain the thermal fields at the positions so as to control the movement of the scanning area units, and further facilitate to maintain better heating uniformity of a large area, wherein the distance between the centers of the adjacent scanning area units is less than 1/2 which is the maximum size of the scanning area units, wherein the maximum size of the scanning area units refers to the maximum value of a connecting line between any two points at the edge of the scanning area units. In one example, the maximum size of the scanning area unit 400 is between 0.5mm and 10mm, preferably between 1mm and 5 mm.
As an example, the step 4) further includes the steps of: and carrying out cooling treatment on an unheated area during the local heating so as to reduce the heat conduction of the local heating to the unheated area.
As an example, the cooling process may be performed by at least one of heat sink technology and active cooling.
Specifically, since the material itself has thermal conductivity, the local heating may also cause the temperature of the unheated portion to rise, thereby increasing the thermal stress, which is not beneficial for the effective implementation of reducing the thermal stress by the local heating. The above cooling can be performed by using a heat sink technology, for example, a heat sink or a heat dissipation block can be used, and the metal block with good heat conduction, such as a copper block, is equivalent to passive cooling, and certainly, the heat can be conducted away by using an active cooling mode, where the active cooling mode refers to a mode that a person skilled in the art can understand that a certain energy is provided to a structure to be cooled so as to conduct away the heat, and for example, a continuous cold source or an electric refrigeration mode is used. For example, the unheated area may be actively cooled by blowing air to the unheated area or by a cooling device. In this example, since the temperature maintaining module such as the heat sink is provided, the temperature rise range can be limited, the temperature stability of the whole structure can be maintained, and the ultrafast pulse method is not required to be used to avoid temperature overshoot like laser heating, so that the local heating time can be increased to increase the production efficiency, and the cost of pulse control can be reduced.
In addition, in an example, the device that includes the heat sink technology or the device of initiative cooling is handled in the cooling, and above-mentioned cooling is handled and is decorated and can be set up any one side of initial bonded structure 300, also can set up in the both sides of initial bonded structure, and above-mentioned device can be in with the heating head setting of local heating the homonymy or the xenonymy of initial bonded structure, wherein, above-mentioned device with the interval between the heating head can be between 0.5cm-1.5cm, guarantees to carry out the stability in the local heating process, in addition, in an example, above-mentioned cooling processing apparatus can also surround the mode setting of the heating head of local heating, and for example, when the device of cooling was handled and selects as the radiating block, the radiating block is located the periphery of the heating head of local heating in the annular, further is favorable to thermal even conduction.
Wherein, the ion beam stripping process of the functional material is an energy accumulation process, if the annealing temperature is low, the annealing time needs to be prolonged to achieve the stripping effect; if the annealing temperature is high, the functional material can be peeled off in a short time. It is considered that the surface peeling time T of the functional material has such a relationship with the annealing temperature T that: t ═ ln (T) ═ const, this relationship demonstrates that increasing the annealing temperature can exponentially reduce the required annealing time, thereby reducing the process time for thin film fabrication and increasing process efficiency. In the method of the present invention, since the local heating can reduce the thermal stress, the initial bonding structure can be heated to a higher temperature while maintaining the structural integrity, thereby further reducing the time for accumulating the local heating pulse and reducing the annealing time, i.e. when the local heating is performed in units of scan region units, the accumulated time for heating each scan region unit can be reduced.
Specifically, in an example, the heating time corresponding to each scanning area unit 400 is between 1s and 20s, and further may be between 5s and 15s, which may be 8s, 10s, or 12 s.
As an example, the step 4) may further include performing the entire heating after performing the local heating.
As an example, the initial bonding structure includes a central region and an outer region located at a periphery of the central region, wherein the step of performing the heat treatment includes: and heating the outer area by adopting the local heating mode, and heating the central area by adopting the integral heating mode.
Example two:
in addition, the present invention further provides an embodiment two, and the difference between the embodiment two and the embodiment one is that, in the step 4), the step of performing the heating process includes a step of performing bulk heating after performing the local heating, that is, the step of simultaneously performing the peeling of a portion of the first substrate in a bulk heating manner, that is, an optimization method combining local heating annealing and bulk heating annealing is used to peel a portion of the first substrate along the defect layer, so that a portion of the first substrate is transferred onto the second substrate to form a substrate thin film on the second substrate, and a heterostructure including the second substrate and the substrate thin film is obtained, thereby considering the problems of production efficiency and cost, and the other steps can refer to the embodiment one, in one example, the size of an area which is not subjected to heating is reduced by a local heating process first, in an optional example, annealing and peeling the edge of the bonding structure by using a local annealing method and annealing the edge of the bonding structure to a wafer inner ring step by step to gradually reduce the bonding size, namely, locally heating the outer region; subsequently, when the size of the bonded structure is reduced to be able to undergo the bulk annealing process, the remaining non-peeled area is peel-transferred using the bulk annealing technique. In one example, the surface of the initial bonding structure opposite to the ion implantation surface of the first substrate may be divided into a central region and an outer region, in one example, the central region is circular, and the outer region is circular.
To further illustrate the advantageous effects of the present invention, as shown in fig. 12-13, the difference between the conventional bulk annealing and the localized heat annealing can be analyzed by using a finite element simulation method, wherein the bonding structure model used is a normal temperature bonding structure of 4 inches of lithium niobate and silicon, fig. 12(a) and 12(b) are respectively shown as a shear force distribution and a deformation diagram of the conventional heat annealing, fig. 13(a) and 13(b) are respectively shown as a shear force distribution and a deformation diagram of the heat annealing of the present invention, specifically, in general, the annealing temperature required for the surface peeling of lithium niobate is about 230 ℃, and the 4-inch bonding structure is cracked at about 140 ℃ because the shear force is too large, and by analyzing, it is assumed that the bonding structure is not cracked at 200 ℃, and the two annealing structures are qualitatively compared by using the magnitudes of the deformation and the shear force, in fig. 12, a heat source with a temperature of 230 ℃ is used for contact heating, and in the conventional integral heating annealing, it can be seen that the shear stress is mainly distributed at the edge of the bonding structure, the maximum value of the extracted shear stress is as high as 0.85GPa, the bonding structure is greatly deformed due to the thermal stress, and the maximum deformation amount of the extracted central point is 5.03 mm; in fig. 13, a heat source of 230 ℃ with a size of 1mm is used for local annealing, and the surrounding area is kept at normal temperature by using techniques such as heat sink, so that the shear stress is mainly distributed around the heating area, the maximum value of the extracted shear stress is only 0.12GPa, and the maximum deformation amount extracted at this time is only 0.06 mm.
In addition, in an example, by means of simulation calculation, a maximum temperature critical value for local heating can be obtained by evaluating how large the annealing temperature is to make the shear stress or deformation in local heating annealing reach the same level as that of the conventional bulk heating technology, and in the above example, the heating temperature for local heating in step 4) is less than 630 ℃, and when the annealing temperature is as high as 630 ℃, the maximum value of the shear stress is 0.81GPa and the extreme value of the deformation is 0.45 mm. The heating temperature for the local heating is selected to be less than 630 ℃, for example, 500 ℃ or 230 ℃, so as to further ensure that the shear stress or deformation in the local heating annealing is less than that in the conventional integral heating.
In summary, the present invention provides a method for manufacturing a heterostructure, including the following steps: 1) providing a first substrate, wherein the first substrate is provided with an ion implantation surface; 2) performing ion implantation on the first substrate from the ion implantation surface to form a defect layer in the first substrate; 3) providing a second substrate, wherein the second substrate is provided with a bonding surface, and bonding the bonding surface and the ion implantation surface to obtain an initial bonding structure; and 4) carrying out heating treatment on the initial bonding structure based on a local heating mode so as to peel off part of the first substrate along the defect layer, so that part of the first substrate is transferred to the second substrate, and a substrate film is formed on the second substrate, so that the heterostructure comprising the second substrate and the substrate film is obtained. According to the scheme, the preparation of the final heterostructure is realized based on a local heating mode in the preparation method, the local heating annealing process can reduce the thermal stress in the bonding structure, and the stability of the heterostructure in the preparation process is improved, so that the overall thermal stress and warpage of the heterostructure in the annealing and stripping process are reduced, and in addition, the single crystal functional film prepared by the method can be used for preparing high-performance acoustic, optical and electrical devices, various sensing devices and the like. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
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| CN112201581A (en) * | 2020-09-18 | 2021-01-08 | 中国科学院苏州纳米技术与纳米仿生研究所 | A kind of ternary compound semiconductor material and preparation method thereof |
| CN112271249B (en) * | 2020-10-23 | 2023-09-15 | 中北大学 | Low-temperature wafer bonding and thin film processing methods for silicon-based/ferroelectric single crystal materials |
| CN112382563A (en) * | 2020-11-13 | 2021-02-19 | 济南晶正电子科技有限公司 | Ion implantation thin film wafer separation method, single crystal thin film, and electronic component |
| CN112670183A (en) * | 2020-12-14 | 2021-04-16 | 珠海光库科技股份有限公司 | Repairing method of bonded and stripped lithium niobate wafer and lithium niobate wafer |
| WO2022143084A1 (en) * | 2020-12-29 | 2022-07-07 | 隆基绿能科技股份有限公司 | Slice preparation method for ultra-thin silicon wafer, ultra-thin silicon wafer and solar cell |
| CN113437021B (en) * | 2021-07-28 | 2022-06-03 | 广东省科学院半导体研究所 | Preparation method of heterojunction of thin film material and thin film prepared by preparation method |
| CN114448372A (en) * | 2021-12-10 | 2022-05-06 | 上海新硅聚合半导体有限公司 | A kind of preparation method and filter of heterogeneous thin film substrate |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1199507A (en) * | 1996-08-27 | 1998-11-18 | 精工爱普生株式会社 | Lifting method, transfer method of thin film device, and thin film device, thin film integrated circuit device, and liquid crystal display device manufactured using the method |
| US6486008B1 (en) * | 2000-02-25 | 2002-11-26 | John Wolf International, Inc. | Manufacturing method of a thin film on a substrate |
| JP2004140266A (en) * | 2002-10-18 | 2004-05-13 | Ishikawajima Harima Heavy Ind Co Ltd | Thin film layer wafer manufacturing method and thin film layer wafer |
| WO2007072632A1 (en) * | 2005-12-20 | 2007-06-28 | Shin-Etsu Chemical Co., Ltd. | Soi substrate and method for manufacturing soi substrate |
| CN105006446A (en) * | 2015-06-25 | 2015-10-28 | 武汉大学 | Method based on femtosecond laser technology for peeling GaN film and sapphire substrate |
| CN106711027A (en) * | 2017-02-13 | 2017-05-24 | 中国科学院上海微系统与信息技术研究所 | Wafer bonding method and preparation method for foreign substrate |
Family Cites Families (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CA2220600C (en) * | 1996-11-15 | 2002-02-12 | Canon Kabushiki Kaisha | Method of manufacturing semiconductor article |
| SG65697A1 (en) * | 1996-11-15 | 1999-06-22 | Canon Kk | Process for producing semiconductor article |
| SG160300A1 (en) * | 2008-10-03 | 2010-04-29 | Semiconductor Energy Lab | Method for manufacturing soi substrate |
| US7927975B2 (en) * | 2009-02-04 | 2011-04-19 | Micron Technology, Inc. | Semiconductor material manufacture |
| CN102754185B (en) * | 2009-12-11 | 2015-06-03 | 夏普株式会社 | Method for manufacturing semiconductor device, and semiconductor device |
| US8476147B2 (en) * | 2010-02-03 | 2013-07-02 | Semiconductor Energy Laboratory Co., Ltd. | SOI substrate and manufacturing method thereof |
| WO2014065018A1 (en) * | 2012-10-23 | 2014-05-01 | 富士電機株式会社 | Semiconductor device manufacturing method |
| CN105428302A (en) * | 2014-09-17 | 2016-03-23 | 中国科学院上海微系统与信息技术研究所 | Method of preparing material-over-insulator by utilizing low-temperature peeling technology |
| TW201807805A (en) * | 2016-08-31 | 2018-03-01 | 瀋陽矽基科技有限公司 | Method to fabricate thin film on substrate by forming a thin film layer which is the region of original substrate receiving ion implantation, and a layer of Remnant Substrate without ion implantation, and heating up the bonding structure body, then applying laser irradiation, etc. |
| CN108493334B (en) * | 2018-03-15 | 2020-06-30 | 中国科学院上海微系统与信息技术研究所 | A kind of preparation method of thin film heterostructure |
| CN108336219A (en) * | 2018-03-15 | 2018-07-27 | 中国科学院上海微系统与信息技术研究所 | A kind of preparation method of thin film heteroj structure |
-
2019
- 2019-02-21 CN CN201910129433.XA patent/CN109904065B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1199507A (en) * | 1996-08-27 | 1998-11-18 | 精工爱普生株式会社 | Lifting method, transfer method of thin film device, and thin film device, thin film integrated circuit device, and liquid crystal display device manufactured using the method |
| US6486008B1 (en) * | 2000-02-25 | 2002-11-26 | John Wolf International, Inc. | Manufacturing method of a thin film on a substrate |
| JP2004140266A (en) * | 2002-10-18 | 2004-05-13 | Ishikawajima Harima Heavy Ind Co Ltd | Thin film layer wafer manufacturing method and thin film layer wafer |
| WO2007072632A1 (en) * | 2005-12-20 | 2007-06-28 | Shin-Etsu Chemical Co., Ltd. | Soi substrate and method for manufacturing soi substrate |
| CN105006446A (en) * | 2015-06-25 | 2015-10-28 | 武汉大学 | Method based on femtosecond laser technology for peeling GaN film and sapphire substrate |
| CN106711027A (en) * | 2017-02-13 | 2017-05-24 | 中国科学院上海微系统与信息技术研究所 | Wafer bonding method and preparation method for foreign substrate |
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