CN109887916B - Bidirectional gate electrode of nonvolatile three-dimensional semiconductor memory and preparation method thereof - Google Patents

Abstract

The invention discloses a bidirectional gate electrode of a nonvolatile three-dimensional semiconductor memory and a preparation method thereof, wherein the bidirectional gate electrode comprises: the array of m rows and n columns of downward gate electrode units is positioned at the lower part and is in stepped distribution, and the array of m rows and n columns of upward gate electrode units is positioned at the upper part and is in stepped distribution, and each downward gate electrode unit and each upward gate electrode unit are in a columnar structure; the upper surfaces of the downward gate electrode units in the same column are connected with the same control grid layer, and the lower surfaces of the downward gate electrode units in the same column are connected with the same lower word line; the lower surfaces of the upper gate electrode units in the same column are connected with the same control grid layer, and the upper surfaces of the upper gate electrode units in the same column are connected with the same upper word line; according to the bidirectional gate electrode structure, the control gate layer and the gate electrode stacked in the super high layer are divided into the upper part and the lower part, so that the depth of a hole to be etched is reduced, and the process difficulty of super deep hole etching is reduced; meanwhile, the area of the chip is reduced, and the heat dissipation effect of the nonvolatile three-dimensional semiconductor memory is enhanced.

Description

Bidirectional gate electrode of nonvolatile three-dimensional semiconductor memory and preparation method thereof

technical field

The invention belongs to the technical field of microelectronic devices, and more particularly, relates to a bidirectional gate electrode of a nonvolatile three-dimensional semiconductor memory and a preparation method thereof.

Background technique

In order to meet the development of efficient and inexpensive microelectronics industry, semiconductor memories need to have higher integration density. High density is very important to reduce the cost of semiconductor products. For traditional two-dimensional and planar semiconductor memories, their integration density mainly depends on the unit area occupied by a single memory device, and the integration degree is very dependent on the quality of the mask process. However, even if expensive process equipment is continuously used to improve the mask process accuracy, the improvement of integration density is still very limited, especially with the development of Moore's Law, below the 22nm process node, planar semiconductor memory faces various size effects and heat dissipation and other issues.

As an alternative to overcoming this two-dimensional limit, three-dimensional semiconductor memories have been proposed. The three-dimensional semiconductor memory can obtain high-reliability device performance by using a process with lower manufacturing cost. In three-dimensional NAND (not and, not and) type memory, BiCS (Bit Cost Scalable) is considered as a three-dimensional non-volatile memory technology that can reduce the area of each bit unit. This technology is achieved through the design of vias and studs and was first presented at the 2007 VLSI Technology Abstracts Annual Meeting. After the non-volatile semiconductor memory adopts BiCS technology, not only the memory has a three-dimensional structure, but also the reduction of data storage bits is proportional to the number of stacked layers of the shelf. However, as the number of stacked layers continues to rise, there are still many problems to be solved in device design.

The existing problem is mainly reflected in how to make the storage unit compatible with the driving circuit. In the memory of BiCS, although the memory cell array is designed as a three-dimensional structure, the design of the peripheral circuit still maintains the traditional two-dimensional structure design. Therefore, in the three-dimensional NAND memory with BiCS, it is necessary to design a stepped control gate layer to connect A gate electrode and a stacked memory cell are then prepared, and a gate electrode structure connecting the gate layer and the word line is prepared. As the number of stacked layers continues to increase, the stepped gate layer will consume a lot of area, and the existing improved vertical gate electrodes will face more severe ultra-deep hole etching and filling when the number of stacked layers continues to increase to a certain extent question. In addition, during the reading and writing process of the vertical gate structure, the crosstalk problem of the memory cell is relatively serious, and the crosstalk problem is more significant with the increase of the number of memory layers and cell density, so the existing gate electrodes are not suitable for ultra-high voltage High-level stacked 3D NAND memory.

SUMMARY OF THE INVENTION

In view of the defects of the prior art, the purpose of the present invention is to provide a bidirectional gate electrode of a non-volatile three-dimensional semiconductor memory and a preparation method thereof, aiming at solving the area consumption that occurs when the number of stacked layers in the prior art is increased to a certain number scatter, ultra-deep via etch and fill, and thermal crosstalk issues.

In order to achieve the above object, one aspect of the present invention provides a method for preparing a bidirectional gate electrode of a nonvolatile three-dimensional semiconductor memory, comprising:

(1) prepare an array of downward gate electrode cells;

(1.1) Through the electrochemical template process, a single-pass porous alumina template is formed on the substrate on which the word line and bit line have been prepared;

(1.2) by depositing a conductive material, a downward gate electrode unit is formed between the pore walls of the porous alumina template;

(1.3) Remove the porous alumina template to form an array of m rows and n columns of downward gate electrode units distributed in steps from short to high, and the m downward gate electrode units on the same word line have the same height; n is the word The number of lines, m is the number of holes of the porous alumina template corresponding to the same word line, m, n are positive integers, i=1, 2,  , n-1;

(2) The first control gate layer is prepared and connected with the shortest downward gate electrode unit;

(2.1) On the downward gate electrode unit array, an insulating layer is formed by depositing insulating material until the highest downward gate electrode unit is covered, and the upper surface of the insulating layer is flattened by CMP;

(2.2) at the position above the insulating layer and aligned with the first word line, photolithography and etching the insulating layer until the first column downward gate electrode unit is exposed;

(2.3) On the upper surface of the first column downward gate electrode unit, by depositing the same conductive material as the metal electrode column, a downward gate electrode parallel to the surface of the substrate and with the first column downward is formed The first control gate layer of the cell connection;

(3) preparing the downward gate electrode of the non-volatile three-dimensional semiconductor memory;

After sequentially forming the second layer, the third layer, . . . the i-th layer until the n-th control gate layer connected to the corresponding downward gate electrode unit, the m rows and n columns of downward gate electrode unit arrays form the Downward gate electrode of non-volatile three-dimensional semiconductor memory;

(4) preparing an upward gate electrode cell array of a non-volatile three-dimensional semiconductor memory;

(4.1) on the nth control gate layer, successively depositing insulating material and the conductive material to form the insulating layer and the longest control gate layer of the upward gate electrode;

(4.2) On the longest control gate layer, alternately depositing insulating layers and sacrificial layers to form (n-1) groups of stacked structures consisting of sacrificial layers and insulating layers;

(4.3) above the insulating layer and aligned from the right edge of the n-th control gate layer to the right edge of the (n-1)-th control gate layer, perform etching until encountering the conductive material, Aligning the position from the right edge of the control gate layer of the (n-i)th layer to the right edge of the control gate layer of the (n-i-1)th layer, etching is performed until the insulating material is encountered, and a step is formed on the stacked structure;

(4.4) forming an insulating layer after depositing the insulating material on the step until covering the highest step, and using CMP to flatten the upper surface of the insulating layer;

(4.5) replacing the sacrificial layer by filling the same conductive material as the control gate layer to form the control gate layer of the upper gate electrode;

(4.6) At the position above the insulating layer and aligned with the word line, the insulating layer is etched using a self-alignment technique until the conductive material is encountered to form a top port located at the same level from short to high M rows and n columns of holes in a stepped distribution;

(4.7) using the conductive material to fill the holes to form an upward gate electrode unit array of m rows and n columns with the upper ports located on the same horizontal plane and distributed in steps from short to high;

(5) preparing the upward gate electrode of the non-volatile three-dimensional semiconductor memory;

After using the self-alignment technology to set the word line pattern above the upward gate electrode unit array, sputtering deposition of the conductive material, and forming the upper word line connected with the corresponding upward gate electrode unit, the upward gate electrode unit array is formed. The upward gate electrode of the nonvolatile three-dimensional semiconductor memory.

Another aspect of the present invention provides a bidirectional gate electrode of a non-volatile three-dimensional semiconductor memory, comprising a lower gate electrode cell array of m rows and n columns in a staircase distribution at a lower part and m rows in a staircase distribution at an upper part n-column upward gate electrode unit array, each downward gate electrode unit and upward gate electrode unit are columnar structures; the upper surface of the downward gate electrode unit of the same column is connected to the same control gate layer, and the lower surface is connected to the same lower word line; The lower surface of the upper gate electrode unit in the same column is connected with the same control gate layer, and the upper surface is connected with the same upper word line.

Through the above technical solutions conceived by the present invention, compared with the prior art, the following beneficial effects can be achieved:

The bidirectional gate electrode structure of the present invention reduces the depth of the hole to be etched by dividing the control gate layer and the gate electrode of the ultra-high-rise stack into upper and lower parts, thereby reducing the technological difficulty of ultra-deep hole etching; The bidirectional gate electrode structure of the invention reduces the number of word lines connected to the gate electrode unit in a single plane, reduces the chip area, and at the same time enhances the heat dissipation effect of the non-volatile three-dimensional semiconductor memory.

Description of drawings

1 is a schematic structural diagram of a nonvolatile three-dimensional semiconductor memory with bidirectional gate electrodes provided by an embodiment of the present invention;

2(a) is a top view of the structure of a nonvolatile three-dimensional semiconductor memory with bidirectional gate electrodes provided by an embodiment of the present invention;

2(b) is a cross-sectional view of a substrate of a nonvolatile three-dimensional semiconductor memory with bidirectional gate electrodes provided by an embodiment of the present invention;

3-24 are schematic cross-sectional views during the execution of the method for fabricating a bidirectional gate electrode provided by an embodiment of the present invention.

Detailed ways

In order to make the objectives, technical solutions and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention, but not to limit the present invention.

As shown in FIG. 1 and FIG. 2( a ), an embodiment of the present invention provides a bidirectional gate electrode of a non-volatile three-dimensional semiconductor memory, including a lower gate electrode unit array with m rows and n columns in a stepped distribution at the lower part and the upper gate electrode unit array of m rows and n columns in a stepped distribution, each downward gate electrode unit and upward gate electrode unit are columnar structures; the upper surface of the downward gate electrode unit in the same column is connected to the same control gate layer , the lower surface is connected to the same lower word line (LWL); the lower surface of the upper gate electrode unit in the same column is connected to the same control gate layer, and the upper surface is connected to the same upper word line (HWL).

Wherein, the material of the metal electrode column includes one or more conductor or semiconductor materials, such as doped polysilicon, tungsten, copper, aluminum, tantalum, titanium, cobalt, titanium nitride or their alloys.

The embodiment of the present invention also provides a method for preparing a bidirectional gate electrode as described above. In order to clearly and systematically describe the method in this embodiment, FIG. 2(b)-FIG. The cross-sectional schematic diagram of , combined with the specific manufacturing process, the above-mentioned bidirectional gate electrode can be prepared by the following method:

(1) prepare an array of downward gate electrode cells;

Specifically, step (1) includes:

(1.1) Through the electrochemical template process, a single-pass porous alumina template is formed on the substrate on which the word line and bit line have been prepared;

Specifically, the cross-section of the substrate where the word lines and bit lines are prepared is shown in Figure 2(b), the word lines are LWL0, LWL1, and LWL2, and the mark 100 is the substrate. The schematic cross-sectional view after performing step (1.1) is shown in Figure 3 As shown, marker 200 is a porous alumina template.

(1.2) Metal electrode columns are formed between the pore walls of the porous alumina template 200 by depositing metal materials;

Specifically, the substrate 100 and the porous alumina template 200 are placed in a metal solution, the solution has built-in graphite as an anode, and the word line LWL0-2 is used as a cathode to connect different constant current sources. The size and deposition time are adjusted to adjust the height of the deposited metal electrode pillars to form metal electrode pillars 110b, 111b, 112b as shown in FIG. 5, and the metal electrode pillars are downward gate electrode units.

The material of the metal electrode column includes one or more conductor or semiconductor materials, such as doped polysilicon, tungsten, copper, aluminum, tantalum, titanium, cobalt, titanium nitride or alloys thereof.

(1.3) The porous alumina template (200) is removed by etching to form an array of m rows and n columns of downward gate electrode units distributed in steps from short to high, and the height of m downward gate electrode units on the same word line are the same; n is the number of word lines, m is the number of pores of the porous alumina template corresponding to the same word line, m and n are both positive integers, i=1, 2, ..., n-1;

Specifically, an appropriate acidic solution is selected to completely etch and remove the porous alumina template 200. The schematic cross-sectional view after this step is performed is shown in FIG. 5. It can be seen from the figure that the heights of the downward gate electrode units on the same word line LWL are the same, 3-column downward gate electrode cells are distributed in steps from short to high

(2) The first control gate layer is prepared and connected with the shortest downward gate electrode unit;

Specifically, step (2) includes:

(2.1) On the downward gate electrode unit array, an insulating layer is formed by depositing insulating material until the highest downward gate electrode unit is covered, and the upper surface of the insulating layer is flattened by CMP;

Specifically, chemical vapor deposition or magnetron sputtering is used to deposit an insulating layer on the above-mentioned short-to-high bidirectional gate electrode array until the highest gate electrode column is covered, and then the upper surface of the upper insulating layer is planarized by CMP; A schematic cross-sectional view after performing this step is shown in FIG. 6 , and the reference numeral 300 is an insulating layer.

(2.2) at a position above the insulating layer and aligned with the first lower word line LWL0, photolithography and etching the insulating layer (300) until the first column downward gate electrode unit is exposed;

Specifically, spin-coating photoresist on the surface of the flattened insulating layer 300, partially exposing the top of the first lower word line LWL0 through alignment and masking processes until the photoresist above the first word line is denatured, developed, and then etched The insulating layer above the first lower word line LWL0 is exposed until the upper surface of the lower gate electrode unit 110b of the first column is exposed; the cross-sectional schematic diagram after performing this step is shown in FIG. 7 , and the mark 400 is photoresist.

(2.3) On the upper surface of the first column downward gate electrode unit, by depositing the same conductive material as the metal electrode column, a downward gate electrode parallel to the surface of the substrate and with the first column downward is formed The first control gate layer of the cell connection;

Specifically, a cross-sectional view after performing this step is shown in FIG. 8 , and the reference numeral 110a is the first control gate layer.

(3) preparing the downward gate electrode of the non-volatile three-dimensional semiconductor memory;

Specifically, the above steps are repeated, the insulating layer is deposited for the second time and the upper surface is polished, and the cross-sectional view is shown in FIG. 9; photolithography and etching are performed from LWL0 to LWL1 until the second column downward gate electrode unit 111b is exposed, The schematic cross-section is shown in FIG. 10; the metal is deposited to prepare the second control gate layer 111a, and the cross-sectional schematic is shown in FIG. 11;

The insulating layer is deposited for the third time and the upper surface is polished. The schematic cross-sectional view is shown in Figure 12; the direct etching from LWL0 to LWL2 until the third column downward gate electrode unit 112b is exposed, the schematic cross-sectional view is shown in Figure 13; The third layer of control gate layer 112a is prepared by using the above-mentioned metal, and a schematic cross-sectional view is shown in FIG. 14 .

(4) Fabrication of an upward gate electrode cell array for a non-easy three-dimensional semiconductor memory

Specifically, step (4) includes:

(4.1) on the nth control gate layer, successively depositing insulating material and the conductive material to form the insulating layer and the longest control gate layer of the upward gate electrode;

(4.2) on the longest control gate layer, alternately depositing insulating layers and sacrificial layers to form a stacked structure consisting of the sacrificial layers and the insulating layer (300);

Specifically, an insulating material is deposited over the third control gate layer 112a to form an insulating layer of a certain thickness, and then a conductive material is deposited to form a control gate layer 113a, and an insulating layer and sacrificial layers 114c and 115c are alternately deposited on 113a, as shown in Fig. 15 shows the stacking structure.

(4.3) Above the insulating layer and aligning from the right edge of 11(i-1)a to the right edge of 11ia, perform etching until the conductive material is encountered, aligning from the right edge of 11(i-2)a To the right edge position of 11(i-1)a, etching is performed until the insulating material is encountered, and a step is formed on the stacked structure;

Specifically, above the uppermost insulating layer and aligned from the right edge of 111a to the right edge of 112a, etching is performed until the conductive material is encountered, and the formed cross-sectional structure is shown in FIG. 16, and then above the uppermost insulating layer and Align the position from the right edge of 110a to the right edge of 111a, and perform etching until the insulating material is encountered to form a step structure as shown in FIG. 17 .

(4.4) an insulating layer is deposited on the steps until the highest step is covered, and an insulating layer is formed, and the upper surface of the insulating layer is flattened by CMP;

Specifically, the cross-sectional structure after performing this step is shown in FIG. 18 .

(4.5) replacing the sacrificial layer by filling the same conductive material as the control gate layer to form the control gate layer of the upper gate electrode;

Specifically, after the sacrificial layer is completely etched by chemical gas etching, evaporation, sputtering or chemical vapor deposition is used to fill the same conductive material as the gate electrode, and after performing this step, the control gate layer as shown in FIG. 19 is formed 113a, 114a, 115a.

(4.6) At the position above the insulating layer and aligned with the word line, the insulating layer is etched using a self-alignment technique until the conductive material is encountered to form a top port located at the same level from short to high M rows and n columns of holes in a stepped distribution;

Specifically, a photoresist 400 is spin-coated on the surface of the flattened insulating layer 300, and the tops of LWL0, LWL1, and LWL2 are partially exposed through alignment and masking processes until the photoresist is denatured and developed at the exposure point, as shown in FIG. 20 . Then, the insulating layer above LWL0, LWL1, and LWL2 is etched until the conductive material is encountered to form holes 115d, 114d, 113d with the upper ports located on the same horizontal plane and distributed in steps from short to high, as shown in FIG. 21 .

(4.7) The holes are filled with the same conductive material as the control gate layer to form an upward gate electrode unit array of m rows and n columns with the upper ports located on the same horizontal plane and distributed in steps from short to high;

Specifically, after this step is performed, the upward gate electrode cell arrays 115b, 114b, and 113b as shown in FIG. 22 are formed.

(5) preparing the upward gate electrode of the non-volatile three-dimensional semiconductor memory;

Use self-alignment technology to cover the word line pattern above the upward gate electrode unit array, sputter deposition of the same metal electrode material as the gate electrode, and peel off to form upper word lines HWL3-HWL5 connected to the corresponding upward gate electrode units. The gate electrode cell array forms an upward gate electrode of the nonvolatile three-dimensional semiconductor memory.

Those skilled in the art can easily understand that the above are only preferred embodiments of the present invention, and are not intended to limit the present invention. Any modifications, equivalent replacements and improvements made within the spirit and principles of the present invention, etc., All should be included within the protection scope of the present invention.

Claims (2)

1. a bidirectional gate electrode preparation method of a non-volatile three-dimensional semiconductor memory, is characterized in that, comprises the following steps: comprising: (1) Prepare an array of downward gate electrode cells; (1.1) Through an electrochemical template process, a single-pass porous alumina template (200) is formed on the substrate (100) where the wordlines and bitlines have been prepared; (1.2) forming a downward gate electrode unit between the pore walls of the porous alumina template (200) by depositing a conductive material; (1.3) Remove the porous alumina template (200) to form m rows and n columns of downward gate electrode cell arrays (110b-11ib) distributed in steps from short to high, and m downward gates on the same word line The electrode units have the same height; n is the number of word lines, m is the number of pores of the porous alumina template corresponding to the same word line, m, n are both positive integers, i=1, 2,...,n- 1; (2) Prepare the first control gate layer and connect it with the shortest downward gate electrode unit; (2.1) On the downward gate electrode unit array, an insulating layer (300) is formed by depositing an insulating material until the highest downward gate electrode unit is covered, and the upper surface of the insulating layer (300) is flattened by CMP; (2.2) at the position above the insulating layer (300) and aligned with the first word line WL0, photolithography and etching the insulating layer (300) until the first column downward gate electrode unit is exposed; (2.3) On the upper surface of the downward gate electrode unit of the first column, by depositing the same conductive material as the downward gate electrode unit, a downward gate electrode parallel to the surface of the substrate and parallel to the first column downward gate electrode is formed the first control gate layer 110a for cell connection; (3) Preparation of the downward gate electrode of the non-volatile three-dimensional semiconductor memory; After sequentially forming the second layer, the third layer, . . . the i-th layer until the n-th control gate layer (111a-11ia) connected to the corresponding downward gate electrode units, the m rows and n columns of the downward gate electrode units an array forms a downward gate electrode of the non-volatile three-dimensional semiconductor memory; (4) Prepare an upward gate electrode cell array of a non-volatile three-dimensional semiconductor memory; (4.1) On the nth control gate layer, successively depositing an insulating material and the conductive material to form an insulating layer and a control gate layer with the longest upper gate electrode; (4.2) On the longest control gate layer, alternately depositing insulating layers and sacrificial layers to form (n-1) groups of stacked structures consisting of sacrificial layers and insulating layers; (4.3) above the insulating layer and aligned from the right edge of the n-th control gate layer to the right edge of the (n-1)-th control gate layer, perform etching until encountering the conductive material, Aligning the position from the right edge of the (n-i)th control gate layer to the right edge of the (n-i-1)th control gate layer, performing etching until encountering an insulating material, and forming a step on the stacked structure; (4.4) depositing the insulating material on the steps until it covers the highest step to form an insulating layer, and using CMP to flatten the upper surface of the insulating layer; (4.5) replacing the sacrificial layer by filling the same conductive material as the control gate layer to form a control gate layer for the upward gate electrode; (4.6) At the position above the insulating layer and aligned with the word line, the insulating layer is etched by self-alignment technology until it encounters the conductive material to form a short-to-high upper port located at the same level. M rows and n columns of holes in a stepped distribution; (4.7) Filling the holes with the conductive material to form an upward gate electrode unit array of m rows and n columns with the upper ports located on the same horizontal plane and distributed in steps from short to high; (5) Prepare the upward gate electrode of the non-volatile three-dimensional semiconductor memory; After using the self-alignment technique to set the word line pattern on the upper gate electrode unit array, sputtering deposition of the conductive material, and forming the upper word line connected with the corresponding upward gate electrode unit, the upward gate electrode unit array is formed. The upward gate electrode of the nonvolatile three-dimensional semiconductor memory. 2. A bidirectional gate electrode of a non-volatile three-dimensional semiconductor memory prepared by the method of claim 1, comprising an m-row and n-column downward gate electrode cell array located in the lower part and a lower gate electrode cell array located in the upper part. A staircase-distributed array of upward gate electrode units with m rows and n columns, each downward gate electrode unit and upward gate electrode unit are columnar structures; the upper surface of the downward gate electrode unit in the same column is connected to the same control gate layer, and the lower surface is connected to the same control gate layer. The lower word line is connected; the lower surface of the upper gate electrode unit in the same column is connected with the same control gate layer, and the upper surface is connected with the same upper word line.

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