CN109884517B - Chip to be tested and test system - Google Patents
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- CN109884517B CN109884517B CN201910217467.4A CN201910217467A CN109884517B CN 109884517 B CN109884517 B CN 109884517B CN 201910217467 A CN201910217467 A CN 201910217467A CN 109884517 B CN109884517 B CN 109884517B
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Abstract
本发明公开了一种待测芯片及测试系统，其中该待测芯片包括待测功能管脚、测试专用管脚、数据读取寄存器及数据写入寄存器；其中，数据读取寄存器与待测功能管脚一一对应连接，用于读取连接的待测功能管脚的信号状态，数据写入寄存器与测试专用管脚一一对应连接，用于将信号状态写入连接的测试专用管脚，任一个数据写入寄存器在同一时刻最多与一个数据读取寄存器连接，以供示波器由对应测试专用管脚读取与该测试专用引脚连接的待测功能管脚的信号状态。本申请仅需对待测功能管脚的信号状态进行读取即可实现信号测量，不会对待测功能管脚的信号进行引出，因此不存在因对待测功能管脚的信号进行引出导致信号分叉因而影响信号质量的问题。
The invention discloses a chip to be tested and a test system, wherein the chip to be tested includes function pins to be tested, dedicated pins for testing, a data read register and a data write register; wherein, the data read register and the function to be tested The pins are connected in a one-to-one correspondence, which is used to read the signal state of the connected functional pins to be tested. The data write register is connected to the dedicated test pins one by one, and is used to write the signal state into the connected dedicated pins for testing. Any data write register can be connected to at most one data read register at the same time, so that the oscilloscope can read the signal state of the function pin under test connected to the test dedicated pin from the corresponding test dedicated pin. This application only needs to read the signal state of the functional pin to be tested to realize signal measurement, and the signal of the functional pin to be tested will not be extracted. Therefore, there is no signal bifurcation caused by the extraction of the signal of the functional pin to be tested. Therefore, the problem of signal quality is affected.
Description
Technical Field
The invention relates to the technical field of chip testing, in particular to a chip to be tested and a testing system.
Background
In the debugging stage of the server, in order to verify the system function of the server and locate the cause of the fault, it is often necessary to test the waveform of digital signals, and these digital signals are generally led out from the service chip of the server.
The current methods for testing digital signal waveforms mainly include two methods: the first method is that an oscilloscope probe is manually adopted to contact exposed conductor parts (measuring points) such as via holes, bonding pads, pins and the like corresponding to digital signals to be detected on a board card of a chip to be detected (the chip to be detected is the chip to be detected which needs to realize signal measurement), and waveform measurement of the digital signals is carried out, the method is difficult to operate, the board card can be damaged if the operation is improper, and not all the digital signals necessarily have proper exposed measuring points; the second method is that all or part of digital signals possibly measured by a chip to be measured are connected to corresponding connectors in a certain mode during design, and then the connectors are connected with an oscilloscope to realize waveform measurement of the digital signals.
In summary, the technical solution for implementing the measurement of the corresponding signal of the chip to be measured in the prior art has the problem that the signal quality is affected due to the signal branching caused by the signal extraction.
Disclosure of Invention
The invention aims to provide a chip to be tested and a test system, which can solve the problem that signal quality is influenced by signal bifurcation caused by signal extraction in the technical scheme for realizing signal measurement corresponding to the chip to be tested in the prior art.
In order to achieve the above purpose, the invention provides the following technical scheme:
a chip to be tested comprises a functional pin to be tested, a special test pin, a data reading register and a data writing register; the data reading registers are connected with the functional pins to be tested in a one-to-one corresponding mode and used for reading the signal states of the connected functional pins to be tested, the data writing registers are connected with the special test pins in a one-to-one corresponding mode and used for writing the signal states into the connected special test pins, and any one of the data writing registers is connected with at most one of the data reading registers at the same time so that an oscilloscope can read the signal states of the functional pins to be tested, which are connected with the special test pins to be tested, from the corresponding special test pins.
Preferably, the data reading device further comprises a switch matrix, the switch matrix comprises a plurality of switches which are disconnected by default, and any one of the data reading registers and any one of the data writing registers are connected through one switch in the switch matrix; the switch matrix is used for controlling the corresponding switch to be closed when receiving the test control signal so as to connect the corresponding data writing register and the data reading register; and the number of the special test pins is less than that of the functional pins to be tested.
Preferably, the test control system further comprises a one-hot code detector, connected to the switch matrix, and configured to detect whether the test control signal is a signal that connects a data reading register and at most one data writing register connected to the switch by controlling the corresponding switch to be closed, if so, determine that the test control signal is valid, and if not, determine that the test control signal is invalid, and control all switches in the switch matrix to be turned off.
Preferably, the system also comprises a signal conversion module and a switch control register; the signal conversion module is used for receiving the test control signal and converting the test control signal into a signal of a preset type, and the switch control register is respectively connected with the signal conversion module, the switch matrix and the one-hot code detector and used for providing the test control signal for the one-hot code detector and controlling a corresponding switch in the switch matrix by using the test control signal.
Preferably, the number of the test dedicated pins is the same as that of the signal input ends of the oscilloscopes, and the test dedicated pins are connected to the signal input ends of the oscilloscopes in a one-to-one correspondence manner.
A test system comprises a board card to be tested and an oscilloscope, wherein the board card to be tested comprises a chip to be tested, and the oscilloscope is connected with the board card to be tested and used for reading the signal state of a functional pin to be tested in the chip to be tested.
Preferably, the board card to be tested further includes a test connector, the test system further includes a test board card, the test board card includes a coaxial cable connector, the chip to be tested is connected to the test connector, the test connector is connected to the test board card, and the test board card is connected to the oscilloscope through the coaxial cable connector.
Preferably, the test system further comprises a control terminal, the board card to be tested further comprises a signal connector, and the signal connector is connected with the chip to be tested and used for receiving the test control signal sent by the control terminal and transmitting the test control signal to the chip to be tested.
The invention provides a chip to be tested and a test system, wherein the chip to be tested comprises a functional pin to be tested, a special test pin, a data reading register and a data writing register; the data reading registers are connected with the functional pins to be tested in a one-to-one corresponding mode and used for reading the signal states of the connected functional pins to be tested, the data writing registers are connected with the special test pins in a one-to-one corresponding mode and used for writing the signal states into the connected special test pins, and any one of the data writing registers is connected with at most one of the data reading registers at the same time so that an oscilloscope can read the signal states of the functional pins to be tested, which are connected with the special test pins to be tested, from the corresponding special test pins. The technical scheme disclosed by the invention is that a data reading register which is connected in a one-to-one corresponding way is arranged for a functional pin to be tested which needs to carry out signal measurement in a chip to be tested, and a data writing register and a special test pin which is connected in a one-to-one corresponding way are arranged for the functional pin to be tested, therefore, for any one data reading register and any one data writing register which are connected, the data reading register reads a signal state from the corresponding functional pin to be tested, the data writing register acquires the signal state and writes the signal state into the special test pin, so that an oscilloscope acquires the signal state from the special test pin to realize signal measurement, therefore, the application only needs to read the signal state of the functional pin to be tested, namely, the signal measurement can be realized by the oscilloscope through the data writing register and the special test pin, therefore, the problem that signal quality is influenced due to signal bifurcation caused by leading out the signal of the functional pin to be tested does not exist.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
Fig. 1 is a schematic diagram of a first structure of a chip to be tested according to an embodiment of the present invention;
fig. 2 is a schematic diagram of a second structure of a chip to be tested according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of a test system according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The embodiment of the invention provides a chip to be tested, which can comprise a functional pin to be tested, a special test pin, a data reading register and a data writing register; the data read registers are connected with the functional pins to be tested in a one-to-one corresponding mode and used for reading the signal states of the connected functional pins to be tested, the data write registers are connected with the special test pins in a one-to-one corresponding mode and used for writing the signal states into the connected special test pins, and any one of the data write registers is connected with at most one data read register at the same time so that the oscilloscope can read the signal states of the functional pins to be tested, which are connected with the special test pins, through the corresponding special test pins.
It should be noted that the number of the functional pins to be tested and the number of the dedicated test pins may be multiple, and if the number of the functional pins to be tested is N and the number of the dedicated test pins is M, the schematic structural diagram of the chip to be tested in this embodiment may be as shown in fig. 1. The chip to be tested can be a service chip in the server or other service chips, the signal state can be a digital signal state or other signal states, and the signal state can be a level value of the signal; the functional pin to be tested is a pin whose signal needs to be measured, the special test pin is a pin for testing, from which the oscilloscope can obtain the signal, the data reading register can read the signal state of the connected functional pin to be tested, the data writing register can write the signal state into the special test pin connected with the data reading register, and the implementation principle of reading the functional pin to be tested by the data reading register and writing the signal state into the special test pin by the data writing register is consistent with that of the corresponding technical scheme in the prior art, and is not described herein again.
When signal measurement needs to be carried out on a chip to be measured, any data reading register and any data writing register can be connected at a certain moment, and at the moment, the signal states of the data reading register and the data writing register which are connected with each other can be transmitted. The data reading register only reads the signal state of the signal of the to-be-tested functional pin connected with the data reading register, and the signal is not led out, so that signal bifurcation is not caused.
The technical scheme disclosed by the invention is that a data reading register which is connected in a one-to-one corresponding way is arranged for a functional pin to be tested which needs to carry out signal measurement in a chip to be tested, and a data writing register and a special test pin which is connected in a one-to-one corresponding way are arranged for the functional pin to be tested, therefore, for any one data reading register and any one data writing register which are connected, the data reading register reads a signal state from the corresponding functional pin to be tested, the data writing register acquires the signal state and writes the signal state into the special test pin, so that an oscilloscope acquires the signal state from the special test pin to realize signal measurement, therefore, the application only needs to read the signal state of the functional pin to be tested, namely, the signal measurement can be realized by the oscilloscope through the data writing register and the special test pin, therefore, the problem that signal quality is influenced due to signal bifurcation caused by leading out the signal of the functional pin to be tested does not exist.
The chip to be tested provided by the embodiment of the invention can also comprise a switch matrix, wherein the switch matrix comprises a plurality of switches which are disconnected by default, and any data reading register and any data writing register are connected through one switch in the switch matrix; the switch matrix is used for controlling the corresponding switch to be closed when receiving the test control signal so as to connect the corresponding data writing register and the data reading register; the number of the special test pins is less than that of the functional pins to be tested.
In order to reduce the design cost of the board card and save the space of the board card, in this embodiment, the number of the test dedicated pins may be set to be smaller than the number of the functional pins to be tested, and in order to implement the connection test of the data reading register and the data writing register on the basis, a switch matrix is set in this embodiment, the switch matrix includes a plurality of switches, each switch is respectively connected with one data reading register and one data writing register, and each switch is in an off state, therefore, when the signal measurement of a certain functional pin to be tested needs to be implemented, the data reading register connected with the functional pin to be tested may be connected with a certain data writing register, so that the data writing register transmits the signal state read by the data reading register to the oscilloscope through the connected test dedicated pins, for example, when the data reading register 2 is connected to the data writing register 3 through the closed switch, the level of the test dedicated pin corresponding to the data write register 3 is consistent with the level of the functional pin to be tested corresponding to the data read register 2, which means that the two pins are connected together, thereby realizing signal measurement based on the two connected pins.
The chip to be tested provided by the embodiment of the invention can also comprise a one-hot code detector, wherein the one-hot code detector is connected with the switch matrix and used for detecting whether the test control signal is a signal which enables a data reading register connected with the switch to be connected with at most one data writing register by controlling the closing of the corresponding switch, if so, the test control signal is determined to be valid, and if not, the test control signal is determined to be invalid and all switches in the switch matrix are controlled to be disconnected.
It should be noted that, at most, one data write register can only be connected to one data read register at a certain time in the signal measurement process, and therefore, if one data write register is simultaneously connected to a plurality of data read registers, the level output by the data write register corresponding to the test dedicated pin cannot be consistent with a certain connected functional pin to be tested, and thus, the signal measurement of the functional pin to be tested cannot be realized. Therefore, in order to ensure the validity of signal measurement, a unique code detector is arranged in this embodiment, the unique code detector acquires a test control signal, and determines whether the test control signal is valid by judging whether the test control signal is a signal that makes a data reading register connected to the switch be connected to at most one data writing register by controlling the closing of a corresponding switch, if the test control signal is valid, the unique code detector does not control the switch in the switch matrix, and the switch matrix controls the switch included in the switch matrix based on the test control signal, and if the test control signal is invalid, all switches in the switch matrix are controlled to be disconnected, and the switch matrix cannot control the switch included in the switch matrix based on the test control signal.
The chip to be tested provided by the embodiment of the invention can also comprise a signal conversion module and a switch control register; the switch control register is respectively connected with the signal conversion module, the switch matrix and the one-hot code detector and is used for providing the test control signal for the one-hot code detector and controlling a corresponding switch in the switch matrix by using the test control signal.
It should be noted that, because the chip to be tested needs to set the on or off of the switch in the switch matrix through the external test control signal, the chip to be tested can process the external test control signal into a signal of a type capable of being transmitted and identified inside the chip to be tested, so as to ensure that the test control signal smoothly realizes the corresponding test control function; if the external test control signal is a UART (Universal Asynchronous Receiver/Transmitter) signal, the test control signal is transmitted to the chip to be tested through the serial port connector, the signal conversion module converts the test control signal into a GPIO (General Purpose Input/Output) signal and then connects the GPIO signal to the switch control register, and the switch control register is connected to the switch matrix and the one-hot code detector, respectively.
According to the chip to be tested provided by the embodiment of the invention, the number of the pins special for testing can be the same as that of the signal input ends of the oscilloscope, and the pins special for testing are connected to the signal input ends of the oscilloscope in a one-to-one correspondence manner.
It should be noted that the dedicated pins to be tested are pins that need to be connected to the oscilloscope to implement signal measurement, so in this embodiment, the number of the dedicated test pins may be set to be the same as the number of the signal input ends of the oscilloscope, and the dedicated test pins are connected to the signal input ends of the oscilloscope in a one-to-one correspondence manner. Specifically, since the number of the signal input terminals of the oscilloscope in the prior art is 4, in this embodiment, the number of the test dedicated pins may be preferably 4, and when the chip to be tested includes the signal conversion module, the switch control register, the one-hot code detector, and the N data reading registers, the schematic structural diagram of the chip to be tested may be as shown in fig. 2, where the connection relationship of the pins is not indicated.
It can be seen from the foregoing embodiments that, in the technical solution disclosed in the present application, in response to the requirement of signal measurement, the test dedicated pins are configured in terms of chip design, the number of the configuration test dedicated pins is less than the number of the functional pins to be tested, and the data read registers connected to the functional pins to be tested in a one-to-one correspondence and the data write registers connected to the test dedicated pins in a one-to-one correspondence are configured, so that the corresponding connection relationship between the test dedicated pins and the other functional pins to be tested is flexibly configured by inputting the test control signal to the switch matrix respectively connected to the data read registers and the data write registers. Therefore, signals of the functional pins to be tested are only required to be read, signal leading-out cannot occur, the problem of signal branching is avoided, only the special test pins can be led out to the oscilloscope to achieve signal measurement, and the special test pin testing device has the advantages of being high in coverage rate of the special test pins, not increasing too many board card designs, being convenient to test and operate and the like.
The embodiment of the invention also provides a test system which can comprise a board card to be tested and an oscilloscope, wherein the board card to be tested comprises any one of the chips to be tested, and the oscilloscope is connected with the board card to be tested and used for reading the signal state of the corresponding functional pin to be tested in the chip to be tested.
The board card to be tested is connected with the oscilloscope, so that the oscilloscope can read the signal state of the functional pin to be tested corresponding to the chip to be tested of the board card to be tested, and corresponding signal measurement is realized.
In the test system provided by the embodiment of the invention, the board card to be tested can further comprise a test connector, the test system further comprises a test board card, the test board card comprises a coaxial cable connector, the chip to be tested is connected with the test connector, the test connector is connected with the test board card, and the test board card is connected with the oscilloscope through the coaxial cable connector.
The test connector, the test board card and the coaxial cable connector are the same as corresponding concepts in the prior art, and in the connection of the test system, the coaxial cable connector can be directly placed on the board card to be tested, so that the special test interface can be directly connected with the oscilloscope through the coaxial cable connector, but the coaxial cable connector belongs to a connector with a larger occupied space, so that too much board card space to be tested is occupied, the board card to be tested is produced in batches, and the test board card is produced in a small quantity.
In the test system provided by the embodiment of the invention, the test system further comprises a control terminal, and the board card to be tested further comprises a signal connector, wherein the signal connector is connected with the chip to be tested and is used for receiving the test control signal sent by the control terminal and transmitting the test control signal to the chip to be tested.
It should be noted that the test control signal may be directly input to the board card to be tested by the worker, and in order not to limit the position of the worker, a control terminal that can be held by the worker may be provided in this embodiment, and the connection between the control terminal and the signal connector may be a wireless connection, so that the worker can send the test control signal only through the control terminal; in addition, the signal connector can be connected with the control terminal in a wired mode, so that the signal reliability is guaranteed, and the protection scope of the invention is also included.
The structural schematic diagram of the test system provided in this embodiment may be as shown in fig. 3, where the service chip is a chip to be tested, and the service board card is a board card to be tested; specifically, the signal connector is respectively connected with the control terminal and the service chip, and the service chip sets the matching relation between the special test pin and the service function pin by receiving a test control signal of the control terminal; connecting a special test pin of the service chip to a test connector, wherein the test connector can be connected to a test board card through a cable or directly; the signal of the special test pin is converted to the coaxial cable connector on the test board card, and the oscilloscope is connected with the coaxial cable connector of the test board card through the coaxial cable to realize signal measurement; when the signals of other service function pins need to be tested, the control terminal inputs a test control signal to change the matching relation between the special test pin and the service function pin. Therefore, the function of measuring any digital signal of the service chip is realized.
It should be noted that for the description of the relevant part in the test system provided in the embodiment of the present invention, reference is made to the detailed description of the corresponding part in the chip to be tested provided in the embodiment of the present invention, and details are not repeated herein. In addition, parts of the technical solutions provided in the embodiments of the present invention that are consistent with the implementation principles of the corresponding technical solutions in the prior art are not described in detail, so as to avoid redundant description.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (5)
1. A chip to be tested is characterized by comprising a functional pin to be tested, a special test pin, a data reading register and a data writing register; the data reading registers are connected with the functional pins to be tested in a one-to-one corresponding mode and used for reading the signal states of the connected functional pins to be tested, the data writing registers are connected with the special test pins in a one-to-one corresponding mode and used for writing the signal states into the connected special test pins, and any one of the data writing registers is connected with at most one data reading register at the same time so that an oscilloscope can read the signal states of the functional pins to be tested, which are connected with the special test pins to be tested, from the corresponding special test pins;
the chip to be tested also comprises a switch matrix, the switch matrix comprises a plurality of switches which are disconnected by default, and any one of the data reading registers and any one of the data writing registers are connected through one switch in the switch matrix; the switch matrix is used for controlling the corresponding switch to be closed when receiving the test control signal so as to connect the corresponding data writing register and the data reading register; the number of the special test pins is less than that of the functional pins to be tested;
the chip to be tested also comprises a one-hot code detector which is connected with the switch matrix and used for detecting whether the test control signal is a signal which enables a data reading register connected with the switch to be connected with at most one data writing register by controlling the closing of a corresponding switch, if so, the test control signal is determined to be valid, if not, the test control signal is determined to be invalid, and all switches in the switch matrix are controlled to be disconnected;
the chip to be tested also comprises a signal conversion module and a switch control register; the signal conversion module is used for receiving the test control signal and converting the test control signal into a signal of a preset type, and the switch control register is respectively connected with the signal conversion module, the switch matrix and the one-hot code detector and used for providing the test control signal for the one-hot code detector and controlling a corresponding switch in the switch matrix by using the test control signal.
2. The chip to be tested according to claim 1, wherein the number of the test dedicated pins is the same as the number of the signal input ends of the oscilloscope, and the test dedicated pins are connected to the signal input ends of the oscilloscope in a one-to-one correspondence manner.
3. A test system is characterized by comprising a board card to be tested and an oscilloscope, wherein the board card to be tested comprises a chip to be tested according to any one of claims 1 to 2, and the oscilloscope is connected with the board card to be tested and used for reading the signal state of a corresponding functional pin to be tested in the chip to be tested.
4. The system of claim 3, wherein the board to be tested further comprises a test connector, the test system further comprises a test board, the test board comprises a coaxial cable connector, the chip to be tested is connected with the test connector, the test connector is connected with the test board card, and the test board card is connected with the oscilloscope through the coaxial cable connector.
5. The system according to claim 4, wherein the test system further comprises a control terminal, and the board card to be tested further comprises a signal connector, and the signal connector is connected to the chip to be tested, and is configured to receive the test control signal sent by the control terminal and transmit the test control signal to the chip to be tested.
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| CN111880976B (en) * | 2020-07-14 | 2024-03-15 | 深圳市同泰怡信息技术有限公司 | RS232 communication serial port testing method and device |
| CN113049946B (en) * | 2021-03-24 | 2022-11-25 | 山东英信计算机技术有限公司 | Board card test system |
| CN114441922B (en) * | 2022-04-02 | 2022-06-14 | 深圳市赛元微电子有限公司 | Semiconductor device testing device |
| CN115389911B (en) * | 2022-08-25 | 2023-04-14 | 北京物芯科技有限责任公司 | Chip scheduler fault judgment method, device, electronic equipment and storage medium |
Citations (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2005026966A1 (en) * | 2003-09-08 | 2005-03-24 | Fujitsu Limited | Register file and its storage element |
| CN101044485A (en) * | 2003-06-18 | 2007-09-26 | 安布里克股份有限公司 | Integrated circuit development system |
| CN102200955A (en) * | 2011-04-26 | 2011-09-28 | 中兴通讯股份有限公司 | Method and device for supporting field programmable gate arrays (FPGA) to download data |
| CN102486939A (en) * | 2010-12-06 | 2012-06-06 | 普天信息技术研究院有限公司 | Joint test action group test method and device for memory |
| CN103744009A (en) * | 2013-12-17 | 2014-04-23 | 记忆科技(深圳)有限公司 | Serial transmission chip test method, serial transmission chip test system and integrated chip |
| CN104536867A (en) * | 2015-01-22 | 2015-04-22 | 浪潮(北京)电子信息产业有限公司 | System and method for debugging multiple field-programmable gate arrays |
| CN105515908A (en) * | 2015-12-10 | 2016-04-20 | 中国航空工业集团公司西安航空计算技术研究所 | AFDX photoelectric conversion time delay test method |
| CN105572573A (en) * | 2014-10-30 | 2016-05-11 | 国际商业机器公司 | Scan chain for memory timing test, scan chain construction method and corresponding device |
| CN106556793A (en) * | 2016-11-09 | 2017-04-05 | 上海东软载波微电子有限公司 | Chip test system and method for testing |
| CN107229584A (en) * | 2017-06-01 | 2017-10-03 | 西南电子技术研究所（中国电子科技集团公司第十研究所） | Aviation electronics simulation test platform I/O management systems |
| CN108388516A (en) * | 2018-03-14 | 2018-08-10 | 上海微小卫星工程中心 | The special verifying test system and method for reconfigurable FPGA software |
| CN109031091A (en) * | 2018-07-16 | 2018-12-18 | 深圳市广和通无线股份有限公司 | Interface test method, test macro and test fixture |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| PE20090965A1 (en) * | 2007-10-12 | 2009-07-13 | Bigtec Private Ltd | MICRO CHIP |
| CN102915287A (en) * | 2011-08-02 | 2013-02-06 | 鸿富锦精密工业（深圳）有限公司 | Read-write control circuit |
-
2019
- 2019-03-21 CN CN201910217467.4A patent/CN109884517B/en active Active
Patent Citations (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101044485A (en) * | 2003-06-18 | 2007-09-26 | 安布里克股份有限公司 | Integrated circuit development system |
| WO2005026966A1 (en) * | 2003-09-08 | 2005-03-24 | Fujitsu Limited | Register file and its storage element |
| CN102486939A (en) * | 2010-12-06 | 2012-06-06 | 普天信息技术研究院有限公司 | Joint test action group test method and device for memory |
| CN102200955A (en) * | 2011-04-26 | 2011-09-28 | 中兴通讯股份有限公司 | Method and device for supporting field programmable gate arrays (FPGA) to download data |
| CN103744009A (en) * | 2013-12-17 | 2014-04-23 | 记忆科技(深圳)有限公司 | Serial transmission chip test method, serial transmission chip test system and integrated chip |
| CN105572573A (en) * | 2014-10-30 | 2016-05-11 | 国际商业机器公司 | Scan chain for memory timing test, scan chain construction method and corresponding device |
| CN104536867A (en) * | 2015-01-22 | 2015-04-22 | 浪潮(北京)电子信息产业有限公司 | System and method for debugging multiple field-programmable gate arrays |
| CN105515908A (en) * | 2015-12-10 | 2016-04-20 | 中国航空工业集团公司西安航空计算技术研究所 | AFDX photoelectric conversion time delay test method |
| CN106556793A (en) * | 2016-11-09 | 2017-04-05 | 上海东软载波微电子有限公司 | Chip test system and method for testing |
| CN107229584A (en) * | 2017-06-01 | 2017-10-03 | 西南电子技术研究所（中国电子科技集团公司第十研究所） | Aviation electronics simulation test platform I/O management systems |
| CN108388516A (en) * | 2018-03-14 | 2018-08-10 | 上海微小卫星工程中心 | The special verifying test system and method for reconfigurable FPGA software |
| CN109031091A (en) * | 2018-07-16 | 2018-12-18 | 深圳市广和通无线股份有限公司 | Interface test method, test macro and test fixture |
Non-Patent Citations (2)
| Title |
|---|
| A 32 Kbs on-chip memory with high port-multiplicity (5 reads and 2 writes) for effective implementation of shared memory systems;T. Tsang等;《Proceedings IEEE Computer Society Workshop on VLSI"98 System Level Design (Cat. No.98EX158)》;19980416;全文 * |
| SoC软硬件协同技术的FPGA芯片测试新方法;李平等;《电子科技大学学报》;20090930;第38卷(第5期);全文 * |
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