CN109873010A - STT-MRAM memory - Google Patents
STT-MRAM memory Download PDFInfo
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- CN109873010A CN109873010A CN201711261714.8A CN201711261714A CN109873010A CN 109873010 A CN109873010 A CN 109873010A CN 201711261714 A CN201711261714 A CN 201711261714A CN 109873010 A CN109873010 A CN 109873010A
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Abstract
This application provides a kind of STT-MRAM memories.The STT-MRAM memory includes multiple storage units, each storage unit include setting on substrate and be electrically connected to each other MTJ of bit member and derailing switch, one electrode of each derailing switch interconnects to form gate bar, STT-MRAM memory further include: at least one metal layer in parallel, on the surface for the separate substrate that a gate bar is arranged in each parallel connection metal layer.In the memory, metal layer in parallel is set in gate bar, the resistance of entire gate bar is reduced in such a way that gate bar is in parallel with metal layer in parallel, and then alleviate RC delays effect, so that STT-MRAM memory storage speed with higher；Also, in the STT-MRAM memory, due to not needing that gate bar is connected in parallel by Dummy bit, so ensure that STT-MRAM memory storage density with higher.
Description
Technical field
This application involves STT-MRAM memory areas, in particular to a kind of STT-MRAM memory.
Background technique
STT-MRAM memory includes the storage unit of multiple matrix arrangements, each storage unit include MTJ of bit member and
The derailing switch being electrically connected with MTJ of bit member, general derailing switch are CMOS.
Currently, a wordline is formed by the way of the polysilicon gate interconnection layout in CMOS in STT-MRAM memory,
Usual polysilicon gate is longer (length of 1,000 bit lines), causes biggish (RC delay), leads to STT-MRAM memory
Storage speed it is slower.
It, will be by polysilicon gate in the prior art usually every a certain number of storage units in order to alleviate the above problem
Pole is connected to metal, and using resistance is reduced with parallel connection of metals to improve storage speed, still, this scheme is needed using virtual
Bit (Dummy bit) links together the grid of different row or column, then the virtual bit is connect with metal, virtual bit
Member can occupy certain area, so that the density of the storage unit in STT-MRAM memory is smaller, such as every 8,16 and 32
A storage unit is connected in the STT-MRAM memory of metal, the area that can be lost be respectively 12.5%, 6.25% with
3.125%, so that the storage density of STT-MRAM memory is smaller.
Summary of the invention
The main purpose of the application is to provide a kind of STT-MRAM memory, to solve STT-MRAM in the prior art
Memory cannot have the problem of faster storage speed and biggish storage density simultaneously.
To achieve the goals above, this application provides a kind of STT-MRAM memory, which includes
Multiple storage units, each said memory cells include setting on substrate and be electrically connected to each other MTJ of bit member and derailing switch, respectively
One electrode of above-mentioned derailing switch interconnects to form gate bar, above-mentioned STT-MRAM memory further include: at least one metal in parallel
Layer, each above-mentioned metal layer in parallel are arranged on the surface far from above-mentioned substrate of an above-mentioned gate bar.
Further, above-mentioned STT-MRAM memory further includes multiple above-mentioned metal layers in parallel, and each above-mentioned in parallel golden
Belong to layer to be arranged in correspondingly on the surface of above-mentioned gate bar.
Further, the material of above-mentioned metal layer in parallel is selected from one of copper, tungsten, aluminium, silver, cobalt and titanium or a variety of.
Further, the thickness of above-mentioned metal layer in parallel is between 40~60nm.
Further, above-mentioned derailing switch is CMOS, and above-mentioned CMOS includes grid, and above-mentioned grid includes being arranged in above-mentioned lining
The grid oxide layer, polysilicon layer and metal silicide layer of setting are sequentially stacked on bottom and along the direction far from above-mentioned substrate, wherein
Each above-mentioned grid oxide layer is arranged on above-mentioned substrate, and each above-mentioned CMOS further includes side wall, and above-mentioned grid is arranged in above-mentioned side wall
On side wall.
Further, above-mentioned STT-MRAM memory further include: the separate above-mentioned of above-mentioned grid is arranged in the first dielectric layer
On the surface of substrate and on the above-mentioned substrate of above-mentioned grid two sides, multiple first through hole are offered in said first dielectric layer,
Each above-mentioned first through hole is connect with each above-mentioned metal silicide layer, and above-mentioned parallel connection metal layer is arranged in above-mentioned first through hole.
Further, multiple second through-holes and multiple third through-holes are offered in said first dielectric layer, above-mentioned second is logical
Hole is connect with the source region of above-mentioned CMOS correspondingly, and above-mentioned third through-hole is connect with the drain region of above-mentioned CMOS correspondingly,
Above-mentioned STT-MRAM memory further include: source layer is arranged in each above-mentioned second through-hole；Drain electrode layer, setting is each above-mentioned the
In three through-holes.
Further, above-mentioned STT-MRAM memory further include: the first diffusion barrier layer is arranged in each above-mentioned first through hole
Hole wall on, it is above-mentioned parallel connection metal layer be arranged on above-mentioned first diffusion barrier layer.
Further, above-mentioned STT-MRAM memory further include: the second diffusion barrier layer is arranged in each above-mentioned first through hole
On the surface of the said first dielectric layer of two sides and on the surface far from above-mentioned substrate of above-mentioned metal layer in parallel.
Further, above-mentioned STT-MRAM memory further include: the second dielectric layer is arranged in above-mentioned second diffusion barrier layer
The surface far from above-mentioned grid on, and said first dielectric layer, above-mentioned second diffusion barrier layer and said second dielectric layer
In offer multiple second through-holes and multiple third through-holes, above-mentioned second through-hole connects with the source region of above-mentioned CMOS correspondingly
It connects, above-mentioned third through-hole is connect with the drain region of above-mentioned CMOS correspondingly, and above-mentioned STT-MRAM memory further includes source layer
With drain electrode layer, above-mentioned source layer is arranged in above-mentioned second through-hole, and above-mentioned drain electrode layer is arranged in above-mentioned third through-hole.
Further, above-mentioned side wall is additionally arranged in the partial sidewall of above-mentioned first through hole, it is above-mentioned parallel connection metal layer it is remote
The part of the surface far from above-mentioned substrate on surface and above-mentioned side wall from above-mentioned metal silicide layer is in the same plane, above-mentioned
Second diffusion barrier layer is additionally arranged on the surface far from above-mentioned substrate of above-mentioned side wall.
Further, above-mentioned STT-MRAM memory further include: above-mentioned source layer is arranged at least one source electrode line layer
On surface far from above-mentioned substrate；At least one bit line layer is arranged on the surface far from above-mentioned substrate of above-mentioned drain electrode layer, on
MTJ of bit member is stated to be arranged on the surface far from above-mentioned substrate of an above-mentioned bit line layer.
Further, above-mentioned STT-MRAM memory includes multiple stacked above-mentioned source electrode line layers of setting and multiple stacked settings
Above-mentioned bit line layer, and the first insulating layer, two adjacent above-mentioned bit lines are provided between two adjacent above-mentioned source electrode line layers
Second insulating layer is provided between layer.
Further, the material of above-mentioned first diffusion barrier layer is selected from one of Ti, Ta, TiN and TaN or a variety of.
Further, the material of above-mentioned second diffusion barrier layer selects silicon-nitrogen compound and/or silicon nitrogen oxygenate.
Using the technical solution of the application, metal layer in parallel is set in gate bar, by by gate bar and metal in parallel
Layer mode in parallel reduces the resistance of entire gate bar, and then alleviates RC delays effect, so that STT-MRAM is stored
Device storage speed with higher；Also, in the STT-MRAM memory, due to not needing grid through Dummy bit
Item is connected in parallel, so ensure that STT-MRAM memory storage density with higher.
Detailed description of the invention
The accompanying drawings constituting a part of this application is used to provide further understanding of the present application, and the application's shows
Meaning property embodiment and its explanation are not constituted an undue limitation on the present application for explaining the application.In the accompanying drawings:
Fig. 1 shows the schematic diagram for forming part CMOS structure in a kind of embodiment of the application on the surface of a substrate；
Fig. 2 shows the structural representations after formation source layer in the construction shown in fig. 1, drain electrode layer and metal layer in parallel
Figure；
Fig. 3 shows the knot that the STT-MRAM memory formed after source electrode line layer and bit line layer is arranged in the structure of Fig. 2
Structure schematic diagram；
Fig. 4 is shown, and the first dielectric material is arranged in the structure of Fig. 1 and opens up in another embodiment of the application
Structural schematic diagram after one through-hole；
Fig. 5, which is shown, is arranged the first diffusion barrier material and the structure after metal material in parallel in structure shown in Fig. 4
Schematic diagram；
After Fig. 6 shows planarization structure shown in fig. 5 and the second diffusion barrier material and the second dielectric material is arranged
Structural schematic diagram；
Fig. 7 shows the structural schematic diagram of the STT-MRAM memory formed on the basis of the structure of Fig. 6；
Fig. 8 shows the schematic diagram for forming part CMOS structure in the another embodiment of the application on the surface of a substrate；
Fig. 9 is shown, and the first dielectric material and hard mask material are arranged in the structure of Fig. 8 and opens up the structure after groove
Schematic diagram；
Figure 10 shows the structure in Fig. 9 and opens up first through hole and metal silicide materials and the first diffusion barrier is arranged
Structural schematic diagram after material；
Figure 11 is shown, and metal material in parallel is arranged in the first through hole of Figure 10 and the second diffusion resistance is arranged after planarizing
The structural schematic diagram that obstructing material is formed；And
Figure 12 shows the structural schematic diagram of the STT-MRAM memory formed on the basis of the structure of Figure 11.
Wherein, the above drawings include the following reference numerals:
1, substrate；2, source region；3, drain region；4, grid oxide layer；5, polysilicon layer；6, metal silicide layer；7, side wall；8, first
Diffusion barrier layer；9, metal layer in parallel；10, the first dielectric layer；11, the second diffusion barrier layer；12, the second dielectric layer；13, source electrode
Layer；14, drain electrode layer；15, source electrode line layer；16, the first insulating layer；17, bit line layer；18, second insulating layer；19, MTJ of bit member；20,
Hard mask material；100, first through hole；06, metal silicide materials；08, the first diffusion barrier material；09, metal material in parallel
Material；010, the first dielectric material；011, the second diffusion barrier material；012, the second dielectric material.
Specific embodiment
It is noted that following detailed description is all illustrative, it is intended to provide further instruction to the application.Unless another
It indicates, all technical and scientific terms used herein has usual with the application person of an ordinary skill in the technical field
The identical meanings of understanding.
It should be noted that term used herein above is merely to describe specific embodiment, and be not intended to restricted root
According to the illustrative embodiments of the application.As used herein, unless the context clearly indicates otherwise, otherwise singular
Also it is intended to include plural form, additionally, it should be understood that, when in the present specification using term "comprising" and/or " packet
Include " when, indicate existing characteristics, step, operation, device, component and/or their combination.
It should be understood that when element (such as layer, film, region or substrate) is described as at another element "upper", this yuan
Part can be directly on another element, or intermediary element also may be present.Moreover, in specification and following claims
In, when description has element " connected " to another element, which " can be directly connected to " to another element, or pass through third
Element " electrical connection " is to another element.
As background technique is introduced, in the prior art in order to reduce RC delays effect, generally use virtual
Bit (Dummy bit) links together the grid of different row or column, then the virtual bit is connect with metal, virtual bit
Member can occupy certain area, so that the density of the storage unit in STT-MRAM memory is smaller, in order to solve skill as above
Art problem, present applicant proposes a kind of STT-MRAM memories.
In a kind of typical embodiment of the application, a kind of reservoir is provided, it, should as shown in Fig. 3, Fig. 6 and Figure 10
STT-MRAM memory includes multiple storage units, and each said memory cells include being arranged on substrate 1 and being electrically connected to each other
MTJ of bit member 19 and derailing switch, an electrode of each above-mentioned derailing switch interconnect to form gate bar, i.e., each derailing switch includes multiple
Electrode, and a corresponding electrode interconnects to form gate bar in multiple switch device, above-mentioned STT-MRAM memory further includes at least
One metal layer 9 in parallel, each above-mentioned metal layer 9 in parallel are arranged on the surface far from above-mentioned substrate 1 of an above-mentioned gate bar.
It should be noted that above-mentioned derailing switch can be any derailing switch in the prior art, for example, MOS, CMOS or
Person BJT.For MOS and CMOS, gate bar is the gate connected in parallel formation of multiple switch device, for BJT, gate bar
It is the base stage parallel connection formation of multiple switch device.
In the STT-MRAM memory, metal layer in parallel is set on the surface of the separate substrate of gate bar, by by grid
Pole item reduces the resistance of entire gate bar with the mode of metal layer parallel connection in parallel, and then alleviates RC delays effect, makes
Obtain STT-MRAM memory storage speed with higher；Also, in the STT-MRAM memory, due to not needing to pass through
Gate bar is connected in parallel by Dummy bit, so ensure that STT-MRAM memory storage density with higher.
In a kind of embodiment of the application, as shown in Fig. 3, Fig. 6 and Figure 10, above-mentioned STT-MRAM memory further includes multiple
Above-mentioned parallel connection metal layer 9, and each above-mentioned metal layer 9 in parallel is arranged on the surface of above-mentioned gate bar correspondingly.In this way
RC delays effect can further be alleviated, so that STT-MRAM memory storage speed with higher.
In order to obtain higher storage speed, in a kind of embodiment of the application, the material of above-mentioned parallel connection metal layer 9 is selected from
One of copper, tungsten, aluminium, silver, cobalt and titanium are a variety of.
In order to further ensure the memory has lower resistance value, in a kind of embodiment of the application, above-mentioned parallel connection
The thickness of metal layer is between 40~60nm.
Certainly, the material of the metal layer in parallel of the application is not limited to above-mentioned material, can also be other available
Metal material, those skilled in the art can select suitable material to form above-mentioned metal layer in parallel according to the actual situation.
In another embodiment of the application, as shown in figure 3, above-mentioned grid includes being arranged on above-mentioned substrate 1 and along remote
Direction from above-mentioned substrate 1 is sequentially stacked the grid oxide layer 4, polysilicon layer 5 and metal silicide layer 6 of setting, wherein each above-mentioned
On above-mentioned substrate 1, above-mentioned parallel connection metal layer 9 is arranged on the surface of above-mentioned metal silicide layer 6 for the setting of grid oxide layer 4, and
Each above-mentioned CMOS further includes side wall 7, and above-mentioned side wall 7 is arranged on the side wall of above-mentioned grid.Metal silicide layer can be further
Improve the electric conductivity of grid.
Certainly, the grid in the application is not limited to above-mentioned structure, can also be other structures, those skilled in the art
Member can select the grid of suitable construction according to the actual situation.
Also, above-mentioned side wall can be the materials such as silica, certainly, however it is not limited to which silica can also be it
His available material, those skilled in the art can select suitable material according to the actual situation.In addition, the CMOS in the application
In can not also include the application side wall, can not also include the metal silicide layer in the application.
In addition, the polysilicon layer in the application can be other material layers with good electric conductivity, however it is not limited to this
The polysilicon layer of application, such as can also be poly-SiGe etc..
Metal silicide layer in the application is the alloy made of metal material and polysilicon.Metal material preferably melts
The relatively high metal material of point, such as tungsten, titanium, cobalt and/or nickel.Grid including metal silicide layer is not only preferable conductive special
Property, but also there is preferable high temperature resistance.Also, because metal silicide layer is located at the surface of grid, from channel region compared with
Far, it can be further ensured that CMOS has lesser critical conduction voltage.
In the another embodiment of the application, as shown in Fig. 3, Fig. 6 and Figure 10, above-mentioned STT-MRAM memory further includes
One dielectric layer 10, the first dielectric layer 10 is arranged on the surface far from above-mentioned substrate 1 of above-mentioned grid and above-mentioned grid two sides
Above-mentioned substrate 1 on, offer multiple first through hole in said first dielectric layer 10, each above-mentioned first through hole and each above-mentioned metal
Silicide layer 6 connects, and above-mentioned parallel connection metal layer 9 is arranged in above-mentioned first through hole.
In another embodiment of the application, multiple second through-holes and multiple thirds are offered in said first dielectric layer 10
Through-hole, above-mentioned second through-hole are connect with the source region 2 of above-mentioned CMOS correspondingly, above-mentioned third through-hole correspondingly with it is above-mentioned
The drain region 3 of CMOS connects, as shown in figure 3, above-mentioned STT-MRAM memory further includes source layer 13 and drain electrode layer 14, source layer 13
It is arranged in each above-mentioned second through-hole；Drain electrode layer 14 is arranged in each above-mentioned third through-hole.
The material of source layer 13 and drain electrode layer 14 in the application can form source electrode selected from any in the prior art
The metal material of layer and drain electrode layer, those skilled in the art can select suitable material according to the actual situation.
Substrate in the application can be substrate including any semiconductor devices, such as sapphire, silicon substrate etc..It is serving as a contrast
Multiple structures can be formed in bottom in advance, each knot such as p-well and field oxide can be pre-formed with by taking NMOS as an example, in substrate
The specific location relationship of structure belongs to the prior art, and details are not described herein again.
The metal in metal layer in parallel is spread out from two sides and lower section in order to prevent, influences the electrical property of CMOS, this
In a kind of embodiment of application, as shown in Fig. 6 and Figure 10, above-mentioned STT-MRAM memory further includes the first diffusion barrier layer 8, the
One diffusion barrier layer 8 is arranged on the hole wall of each above-mentioned first through hole, and above-mentioned parallel connection metal layer 9 setting is in above-mentioned first diffusion resistance
In barrier 8.
The material of above-mentioned first diffusion barrier layer can be any workable conductive barrier metal in the prior art
Diffusion volume material, those skilled in the art can select suitable material according to the actual situation.
In order to further ensure the first diffusion barrier layer has preferably the ability for preventing metal from spreading, and simultaneously further
Guarantee it with preferable electric conductivity, in a kind of embodiment of the application, the material of above-mentioned first diffusion barrier layer 8 is selected from
One of Ti, Ta, TiN and TaN or a variety of.
In another embodiment of the application, as shown in Fig. 6 and Figure 10, above-mentioned STT-MRAM memory further includes the second expansion
Barrier layer 11 is dissipated, the second diffusion barrier layer 11 is arranged on the surface of the said first dielectric layer 10 of each above-mentioned first through hole two sides
And on the surface far from above-mentioned substrate 1 of above-mentioned metal layer 9 in parallel.Metal layer in parallel can be prevented to be diffused into from top in this way
Other positions, and then CMOS is further ensured with good electrical property, to ensure that the STT-MRAM memory has
Preferable electrical property.
In order to further ensure the second diffusion barrier layer has preferably the ability for preventing metal from spreading, and simultaneously further
Guarantee it with preferable insulation performance, in a kind of embodiment of the application, the material of above-mentioned second diffusion barrier layer 11 selects silicon
Nitrogen compound and/or silicon nitrogen oxygenate.
Certainly, the second diffusion barrier layer of the application is not limited to above-mentioned material, can also be it is in the prior art its
His any available material, those skilled in the art can select suitable material to form the second diffusion barrier according to the actual situation
Layer.
In another embodiment of the application, as shown in Fig. 6 and Figure 10, above-mentioned STT-MRAM memory further includes second Jie
Electric layer 12, the second dielectric layer 12 are arranged on the surface far from above-mentioned grid of above-mentioned second diffusion barrier layer 11, and above-mentioned the
Offered in one dielectric layer 10, above-mentioned second diffusion barrier layer 11 and said second dielectric layer 12 multiple second through-holes with it is multiple
Third through-hole, above-mentioned second through-hole are connect with the source region 2 of above-mentioned CMOS correspondingly, above-mentioned third through-hole correspondingly with
The drain region 3 of above-mentioned CMOS connects, and above-mentioned STT-MRAM memory further includes source layer 13 and drain electrode layer 14, and above-mentioned source layer 13 is set
It sets in above-mentioned second through-hole, above-mentioned drain electrode layer 14 is arranged in above-mentioned third through-hole.
The material of the first dielectric layer of the application and the material of the second dielectric layer can be independently selected from the prior art
Any material that can be used as dielectric layer, those skilled in the art can choose the first dielectric that suitable material forms the application
Layer and the second dielectric layer, such as selected from silica and/or can be silicon nitride.
As shown in Figure 10, in the another embodiment of the application, above-mentioned side wall 7 is additionally arranged at the part of above-mentioned first through hole
On side wall, the separate above-mentioned substrate 1 on the surface and above-mentioned side wall 7 far from above-mentioned metal silicide layer 6 of above-mentioned parallel connection metal layer 9
Part of the surface in the same plane, above-mentioned second diffusion barrier layer 11 be additionally arranged at above-mentioned side wall 7 far from above-mentioned substrate 1
Surface on.
In another embodiment of the application, as shown in Fig. 3, Fig. 6 and Figure 10, above-mentioned STT-MRAM memory further includes
The separate above-mentioned lining of above-mentioned source layer 13 is arranged at least one source electrode line layer 15 and at least one bit line layer 17, source electrode line layer 15
On the surface at bottom 1；Bit line layer 17 is arranged on the surface far from above-mentioned substrate 1 of above-mentioned drain electrode layer 14, and above-mentioned MTJ of bit member 19 is set
It sets on the surface far from above-mentioned substrate 1 of an above-mentioned bit line layer 17.
In the another embodiment of the application, as shown in Fig. 3, Fig. 6 and Figure 10, above-mentioned STT-MRAM memory includes multiple
The above-mentioned bit line layer 17 of stacked setting above-mentioned source electrode line layer 15 and multiple stacked settings, and two adjacent above-mentioned source electrode line layers 15
Between be provided with the first insulating layer 16, to completely cut off two adjacent source electrode line layers, set between the above-mentioned bit line layer 17 of adjacent two
It is equipped with second insulating layer 18, to completely cut off two adjacent bit line layers.
STT-MRAM memory in the application can choose any feasible technique production, and those skilled in the art can be with
Suitable manufacture craft is selected according to the actual situation, will make the application's by taking three kinds of specific production methods as an example below
STT-MRAM memory.
The first manufacture craft includes:
Firstly, making structure shown in FIG. 1, the production method of specific each structure can use in the prior art
Manufacture craft in CMOS, is not described in more detail here.
Secondly, forming structure shown in Fig. 2.
First dielectric material is set on the exposed surface of Fig. 1, specific setting method can according to actual material and
It is fixed, for silica, it can choose thermal oxidation method or chemical vapour deposition technique etc..
First through hole, the second through-hole and third through-hole are opened up in the first dielectric material, being formed has the first of through-hole
Then dielectric layer 10 deposited metal and planarizes in these through-holes, forms metal layer in parallel 9 as shown in Figure 2, source layer 13
And drain electrode layer 14.
The mode of above-mentioned aperture can use any feasible mode in the prior art, and those skilled in the art can root
Suitable mode is selected according to actual conditions (such as material and/or structure size), such as dry etching and/or wet etching,
It can be RIE etching method etc. in dry etching.The method of above-mentioned metal deposit can use in the prior art any feasible
Mode, those skilled in the art (such as actual material) can select suitable mode, such as physics according to the actual situation
Be vapor-deposited (PVD) or chemical vapor deposition (CVD) etc..
The technique of planarization is typically chosen chemical mechanical polishing method, is certainly not limited to this method, those skilled in the art
Suitable method can be selected to be planarized according to the actual situation.
Finally, in the surface of above-mentioned Fig. 2 structure setting source electrode line layer, bit line layer, MTJ of bit member, the first insulating layer and the
Two insulating layers form structure shown in Fig. 3.
Specific method can be using setting metal interconnection layer in the prior art and the method for MTJ of bit member, herein
No longer elaborate.
In addition, it is above-mentioned before setting source electrode line layer, bit line layer, MTJ of bit member, the first insulating layer and second insulating layer,
It can also be in setting diffusion resistance on the surface of the first dielectric layer and the separate substrate of source layer, drain electrode layer and metal layer in parallel
Barrier, the diffusion of the diffusion barrier layer barrier metal guarantee that STT-MRAM memory has preferable electrical property.
Second of manufacture craft include:
The first step makes structure shown in FIG. 1, and the production method of specific each structure can use in the prior art
Manufacture craft in CMOS, is not described in more detail here.
Second step forms structure shown in Fig. 4.
First dielectric material 010 is set on the exposed surface of Fig. 1, and specific setting method can be according to actual material
Depending on, for silica, it can choose thermal oxidation method or chemical vapour deposition technique etc..
First through hole 100 is opened up in the first dielectric material 010, the mode of above-mentioned aperture can use in the prior art
Any feasible mode, those skilled in the art (such as material and/or structure size) can select properly according to the actual situation
Mode, such as dry etching and/or wet etching.
Third step forms structure shown in fig. 5.
The first diffusion barrier material 08 and metal material 09 in parallel are set gradually in first through hole.
The setting method of above-mentioned metal material in parallel and the setting method of the first diffusion barrier material can be selected from ground
Any feasible mode in the prior art is selected, those skilled in the art can according to the actual situation (such as actual material)
Select suitable mode, such as physical vapour deposition (PVD) (PVD) or chemical vapor deposition (CVD) etc..
4th step forms structure shown in fig. 6.
Structure shown in fig. 5 is planarized.Form the first diffusion barrier layer 8 as shown in FIG. 6 and metal layer in parallel
9。
The second diffusion barrier material 011 and the second dielectric material 012 are set gradually on the surface of planarization, form Fig. 6
Shown in structure.
The technique of planarization is typically chosen chemical mechanical polishing method, is certainly not limited to this method, those skilled in the art
Suitable method can be selected to be planarized according to the actual situation.
For the setting method of the second diffusion barrier material 011 and the second dielectric material 012, those skilled in the art can be with
Suitable method, such as physics gas are selected in all methods of (such as actual material) in the prior art according to the actual situation
Mutually deposition (PVD) or chemical vapor deposition (CVD) etc..Also, the second diffusion barrier material 011 and the second dielectric material 012
Setting method can be identical, be also possible to different.
5th step forms structure shown in Fig. 7.
In the first dielectric material 010 of above-mentioned Fig. 6 structure, the second diffusion barrier material 011 and the second dielectric material 012
In open up the second through-hole and third through-hole, the first dielectric layer 10, the second diffusion barrier layer 11 and second formed in Fig. 7 is situated between
Electric layer 12.
Deposited metal is set in above-mentioned second through-hole and third through-hole and is planarized, source electrode as shown in Figure 7 is formed
Layer 13 and drain electrode layer 14.
In the surface of above-mentioned planarization setting source electrode line layer, bit line layer, MTJ of bit member, the first insulating layer and the second insulation
Layer, forms structure shown in Fig. 7.
The method of setting metal material, the method that dielectric material is set, setting diffusion barrier in above-mentioned manufacture craft
The method of the method for material, the method for aperture and planarization can be using feasible method in the prior art, this field skill
Art personnel can select suitable method according to the actual situation, just no longer elaborate herein.
The third manufacture craft includes:
The first step makes structure shown in Fig. 8, and the production method of specific each structure can use in the prior art
Manufacture craft in CMOS, is not described in more detail here.Wherein, it is a difference in that metal silicide materials 06 are direct with Fig. 1
It is correspondingly formed last metal silicide layer.
Second step forms structure shown in Fig. 9.
The first dielectric material 010 and hard mask material 20, specific setting method are set gradually on the exposed surface of Fig. 1
It can be depending on actual material.
Groove is opened up in hard mask material 20 and the first dielectric material 010, forms structure shown in Fig. 9.
Third step forms structure shown in Fig. 10.
Continue etch Fig. 8 structure, by immediately below groove the first dielectric material 010, metal silicide materials 06 and
Partial polysilicon layer 5 etches removal.
It is set gradually in first through hole and the second diffusion barrier material 011.Structure as shown in Figure 10 is formed, the structure
In metal silicide materials formed metal silicide layer 6.
4th step forms structure shown in Figure 11.
Metal material in parallel is set in the first through hole 100 in structure shown in Fig. 10, and is planarized, is formed in Figure 11
The first diffusion barrier layer 8 and metal layer 9 in parallel.
Also, the second diffusion barrier material 011 is set on the surface of planarization, forms structure shown in Figure 11.
5th step forms structure shown in Figure 12.
Second dielectric material is set in above-mentioned second diffusion barrier material 011, also, in the first dielectric material, second
The second through-hole and third through-hole are opened up in diffusion barrier material and the second dielectric material.
Deposited metal is set in above-mentioned second through-hole and third through-hole and is planarized, source electrode as shown in figure 12 is formed
Layer 13 and drain electrode layer 14.
In the surface of above-mentioned planarization setting source electrode line layer, bit line layer, MTJ of bit member, the first insulating layer and the second insulation
Layer forms structure shown in Figure 12.
The method of setting metal material, the method that dielectric material is set, setting diffusion barrier in above-mentioned manufacture craft
The method of the method for material, the method for aperture and planarization can be using feasible method in the prior art, this field skill
Art personnel can select suitable method according to the actual situation, just no longer elaborate herein.
It can be seen from the above description that the application the above embodiments realize following technical effect:
In the STT-MRAM memory of the application, metal layer in parallel is set in gate bar, by by gate bar with it is in parallel
The mode of metal layer parallel connection reduces the resistance of entire gate bar, and then alleviates RC delays effect, so that STT-MRAM
Memory storage speed with higher；Also, in the STT-MRAM memory, due to do not need by Dummy bit by
Gate bar is connected in parallel, so ensure that STT-MRAM memory storage density with higher.
The foregoing is merely preferred embodiment of the present application, are not intended to limit this application, for the skill of this field
For art personnel, various changes and changes are possible in this application.Within the spirit and principles of this application, made any to repair
Change, equivalent replacement, improvement etc., should be included within the scope of protection of this application.
Claims (15)
1. a kind of STT-MRAM memory, the STT-MRAM memory includes multiple storage units, each storage unit packet
It includes MTJ of bit that is being arranged on substrate (1) and being electrically connected to each other first (19) and derailing switch, an electrode of each derailing switch is mutual
Connection forms gate bar, which is characterized in that the STT-MRAM memory further include:
The separate lining of the gate bar is arranged at least one metal layer (9) in parallel, each metal layer (9) in parallel
On the surface at bottom (1).
2. STT-MRAM memory according to claim 1, which is characterized in that the STT-MRAM memory further includes more
A metal layer (9) in parallel, and the surface of the gate bar is arranged in each metal layer (9) in parallel correspondingly
On.
3. STT-MRAM memory according to claim 1, which is characterized in that the material choosing of the parallel connection metal layer (9)
From one of copper, tungsten, aluminium, silver, cobalt and titanium or a variety of.
4. STT-MRAM memory according to claim 1, which is characterized in that the thickness of the parallel connection metal layer (9) exists
Between 40~60nm.
5. STT-MRAM memory according to claim 1, which is characterized in that the derailing switch is CMOS, and described
CMOS includes grid, and the grid includes being arranged on the substrate (1) and being sequentially stacked along the direction far from the substrate (1)
Grid oxide layer (4), polysilicon layer (5) and the metal silicide layer (6) of setting, wherein each grid oxide layer (4) is arranged described
On substrate (1), and each CMOS further includes side wall (7), and the side wall (7) is arranged on the side wall of the grid.
6. STT-MRAM memory according to claim 5, which is characterized in that the STT-MRAM memory further include:
On the surface far from the substrate (1) of the grid and grid two sides are arranged in first dielectric layer (10)
On the substrate (1), multiple first through hole, each first through hole and each gold are offered in first dielectric layer (10)
Belong to silicide layer (6) connection, the parallel connection metal layer (9) is arranged in the first through hole.
7. STT-MRAM memory according to claim 6, which is characterized in that offered in first dielectric layer (10)
Multiple second through-holes and multiple third through-holes, second through-hole is connect with the source region of the CMOS (2) correspondingly, described
Third through-hole is connect with the drain region of the CMOS (3) correspondingly, the STT-MRAM memory further include:
Source layer (13) is arranged in each second through-hole；And
Drain electrode layer (14) is arranged in each third through-hole.
8. STT-MRAM memory according to claim 6, which is characterized in that the STT-MRAM memory further include:
First diffusion barrier layer (8) is arranged on the hole wall of each first through hole, and the parallel connection metal layer (9) is arranged in institute
It states on the first diffusion barrier layer (8).
9. STT-MRAM memory according to claim 8, which is characterized in that the STT-MRAM memory further include:
Second diffusion barrier layer (11), be arranged on the surface of first dielectric layer (10) of each first through hole two sides with
And on the surface far from the substrate (1) of the metal layer (9) in parallel.
10. STT-MRAM memory according to claim 9, which is characterized in that the STT-MRAM memory further include:
Second dielectric layer (12) is arranged on the surface far from the grid of second diffusion barrier layer (11), and described
It is logical that multiple second are offered in first dielectric layer (10), second diffusion barrier layer (11) and second dielectric layer (12)
Hole and multiple third through-holes, second through-hole are connect with the source region of the CMOS (2) correspondingly, the third through-hole one
One accordingly connect with the drain region of the CMOS (3), and the STT-MRAM memory further includes source layer (13) and drain electrode layer
(14), the source layer (13) is arranged in second through-hole, and the drain electrode layer (14) is arranged in the third through-hole.
11. STT-MRAM memory according to claim 10, which is characterized in that the side wall (7) is additionally arranged at described
In the partial sidewall of first through hole, the surface and the side far from the metal silicide layer (6) of the parallel connection metal layer (9)
In the same plane, second diffusion barrier layer (11) is additionally arranged at the part of the surface far from the substrate (1) of wall (7)
On the surface far from the substrate (1) of the side wall (7).
12. the STT-MRAM memory according to claim 7 or 10, which is characterized in that the STT-MRAM memory is also
Include:
At least one source electrode line layer (15) is arranged on the surface far from the substrate (1) of the source layer (13)；And
At least one bit line layer (17) is arranged on the surface far from the substrate (1) of the drain electrode layer (14), the MTJ
Bit (19) setting is on the surface far from the substrate (1) of a bit line layer (17).
13. STT-MRAM memory according to claim 12, which is characterized in that the STT-MRAM memory includes more
The bit line layer (17) of a stacked setting the source electrode line layer (15) and multiple stacked settings, and two adjacent source electrodes
It is provided between line layer (15) the first insulating layer (16), is provided with second insulating layer between the bit line layer (17) of adjacent two
(18)。
14. STT-MRAM memory according to claim 8, which is characterized in that the material of first diffusion barrier layer (8)
Material is selected from one of Ti, Ta, TiN and TaN or a variety of.
15. STT-MRAM memory according to claim 9, which is characterized in that second diffusion barrier layer (11)
Material selects silicon-nitrogen compound and/or silicon nitrogen oxygenate.
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| CN201711261714.8A CN109873010A (en) | 2017-12-04 | 2017-12-04 | STT-MRAM memory |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201711261714.8A CN109873010A (en) | 2017-12-04 | 2017-12-04 | STT-MRAM memory |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112349311A (en) * | 2019-08-08 | 2021-02-09 | 中电海康集团有限公司 | Memory and read-write method thereof |
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