Detailed description of the invention
Figure 1A is the schematic diagram that a kind of display panel is shown according to the section Example of present disclosure.
Figure 1B is the schematic diagram that another display panel is shown according to the section Example of present disclosure.
Fig. 2 is the signal sequence schematic diagram that a kind of pixel is shown according to the section Example of present disclosure.
Fig. 3 is that each crystal in the display panel of Figure 1A is shown within first period according to the section Example of present disclosure
The status diagram of pipe.
Fig. 4 is that each crystal in the display panel of Figure 1A is shown within the second phase according to the section Example of present disclosure
The status diagram of pipe.
Fig. 5 A is to exemplify the schematic diagram of another display panel according to the implementation of the other parts of present disclosure.
Fig. 5 B is to exemplify the schematic diagram of another display panel according to the implementation of the other parts of present disclosure.
Fig. 6 is to implement to exemplify the signal sequence signal of another display panel according to the other parts of present disclosure
Figure.
Fig. 7 A, Fig. 7 B are to exemplify another display panel and its signal sequence according to the implementation of the other parts of present disclosure
Schematic diagram.
Wherein, the reference numerals are as follows:
100: display panel
PI1, PI2, PI3: pixel
120: compensation circuit
140: write circuit
160: driving circuit
OLED: light-emitting component
TC1, TC2, TC3, TC4: compensation transistor
T1, T2, T3, T4: transistor
C1: capacitor
S1 [N], S1 [1], S1 [2], S1 [K]: scanning signal
EM [N], EM1 [N], EM2 [N], EM [G]: LED control signal
Vcomp [n]: thermal compensation signal
Vdata [m]: data-signal
Vref: reference voltage level
OVDD: system high voltage level
OVSS: system low-voltage level
P1, P2, Poff, Pon: period
Specific embodiment
It is hereafter to elaborate for embodiment cooperation attached drawing, but described specific embodiment is only to explain this public affairs
It opens, is not used to limit the disclosure, and the description of structure operation is non-to limit its sequence executed, it is any by element again group
The structure of conjunction, the produced device with impartial technical effect, is all the range that present disclosure is covered.
Please refer to Figure 1A.Figure 1A is the signal that a kind of display panel 100 is shown according to the section Example of present disclosure
Figure.In some embodiments, display panel 100 can be active organic LED display panel (Active Matrix
Organic Light Emitting Display, AMOLED).It may include that pixel is complete aobvious to form in display panel 100
Show picture, is illustrated in Figure 1A in order to illustrate upper one of pixel conduct that succinctly only shows.
As shown in Figure 1A, display panel 100 includes compensation circuit 120 and pixel PI1.Pixel PI1 includes write circuit
140, driving circuit 160, capacitor C1 and light-emitting component OLED.Compensation circuit 120 includes compensation transistor TC1, TC2 and TC3.It writes
Entering circuit 140 includes transistor T1.Driving circuit 160 includes transistor T2 and T3.Capacitor C1 includes first end and second end.
In structure, the first end of 120 coupling capacitance C1 of compensation circuit.The second end of 140 coupling capacitance C1 of write circuit.It drives
The second end and light-emitting component OLED of dynamic 160 coupling capacitance C1 of circuit.Specifically, the first end coupling of compensation transistor TC1
System high voltage level OVDD.Compensate the first end of the second end coupling compensation transistor TC2 of transistor TC1.Compensate transistor
The second end of TC2 and the control terminal of compensation transistor TC2 are coupled together at the first end of capacitor C1.Compensate the of transistor TC3
One end is also coupled to the first end of capacitor C1.
The second end of the second end coupling capacitance C1 of transistor T1.The first end coupling system high-voltage level of transistor T2
OVDD.The second end of the control terminal coupling capacitance C1 of transistor T2.The first end of the second end coupling transistors T3 of transistor T2.
The first end of the second end coupling light-emitting component OLED of transistor T3.The second end coupling system low-voltage electricity of light-emitting component OLED
Flat OVSS.
In operation, compensation circuit 120 is to be reset to reference voltage for the first end of capacitor C1 according to scanning signal S1 [N]
Level Vref, and system high voltage level OVDD is received to export thermal compensation signal Vcomp [n] according to LED control signal EM [N]
To the first end of capacitor C1.Write circuit 140 is to be selectively connected according to scanning signal S1 [N] with outputting data signals
The second end of Vdata [m] to capacitor C1.Driving circuit 160 is to selectively turn on according to LED control signal EM [N] with root
According to the voltage level of the second end of capacitor C1 with output driving current I1 to light-emitting component OLED.
Specifically, the control terminal of compensation transistor TC1 is to receive LED control signal EM [N], and according to luminous control
Signal EM [N] processed, which selectively turns on, to be received system high voltage level OVDD with the first end of self compensation transistor TC1 and passes through
The second end of compensation transistor TC1 is exported to the first end of compensation transistor TC2.Compensation transistor TC2 is received to basis
System high voltage level OVDD generate thermal compensation signal Vcomp [n], and by thermal compensation signal Vcomp [n] self compensation transistor TC2
Second end export to the first end of capacitor C1.
The first end of transistor TC3 is compensated to receive reference voltage level Vref.The control terminal for compensating transistor TC3 is used
To receive scanning signal S1 [N], and selectively turned on according to scanning signal S1 [N] so that compensating the second of transistor TC3
End is reset to reference voltage level Vref.
The first end of transistor T1 in write circuit 140 is to receive data-signal Vdata [m].The control of transistor T1
End processed is selectively turned on to receive scanning signal S1 [N], and according to scanning signal S1 [N] to pass through the second of transistor T1
Hold outputting data signals Vdata [m] to the second end of capacitor C1.
The first end of transistor T2 in driving circuit 160 is to receive system high voltage level OVDD.Transistor T2 is used
To be selectively turned on according to the voltage level of the control terminal of transistor T2, to pass through the second end output driving electricity of transistor T2
Flow I1.The first end of transistor T3 is to receive driving current I1 from the second end of transistor T2.The control terminal of transistor T3 is used
To receive LED control signal EM [N], and selectively turned on according to LED control signal EM [N] by the of transistor T3
Two end output driving current I1 to light-emitting component OLED.
Please refer to Figure 1B.Figure 1B is to show showing for another display panel 100 according to the section Example of present disclosure
It is intended to.As shown in Figure 1B, in other parts embodiment, two or more pixel PI1, PI2, PI3's in display panel 100
The first end of capacitor C1 is mutually coupled, to receive identical thermal compensation signal Vcomp [n].Pixel PI2 and PI3 can be by Figure 1A
Shown pixel PI1 implementation, operating method is as described above, does not repeat then at this.
In other words, two or more pixel PI1, PI2, PI3 share the same compensation circuit 120.In this way, pass through benefit
The one-to-many shared framework of circuit 120 is repaid, layout area can be reduced.Although in addition, shown in Figure 1B three pixel PI1, PI2,
PI3, but its quantity only for convenience of description for the sake of example, not to limit present disclosure.This field has usual knowledge
The pixel quantity that the same compensation circuit 120 is shared in display panel 100 can be arranged in person according to actual demand.
Please refer to Fig. 2.When Fig. 2 is the signal for showing a kind of display panel 100 according to the section Example of present disclosure
Sequence schematic diagram.As shown in Fig. 2, scanning signal S1 [N] is in low voltage level in first period P1.In second phase P2, scanning letter
Number S1 [N] is in high-voltage level.In addition, LED control signal EM [N] is located at shutdown voltage level in first period P1.?
Two period P2, LED control signal EM [N] switch to luminous voltage level by shutdown voltage level.In other words, in section Example
In, the time span that LED control signal EM [N] is located at shutdown voltage level is greater than or equal to the time span of first period P1.
For ease of illustration for the sake of, the concrete operations of each element will arrange in pairs or groups attached in following paragraphs in display panel 100
Figure is illustrated.Please also refer to Fig. 2 and Fig. 3.Fig. 3 is to be shown according to the section Example of present disclosure in first period P1
The status diagram of each transistor in the display panel 100 of interior Figure 1A.As shown in figure 3, in some embodiments, first period P1
Correspond to the resetting and address period of display panel 100.
In first period P1, to compensate transistor TC1, TC2 positioned at the LED control signal EM [N] of shutdown voltage level
It is turned off with transistor T3.Make to compensate transistor TC3 and transistor T2 conducting positioned at the scanning signal S1 [N] of low voltage level.
Specifically, in first period P1, compensation transistor TC3 is connected according to scanning signal S1 [N] with by the first end weight of capacitor C1
Set reference voltage level Vref.Transistor T2 is connected according to scanning signal S1 [N] to export extremely data-signal Vdata [m]
The second end of capacitor C1.In other words, in first period P1, the first end of capacitor C1 is located at reference voltage level Vref, capacitor C1
Second end be located at the voltage level of data-signal Vdata [m].
Then, please also refer to Fig. 2 and Fig. 4.Fig. 4 is to be shown according to the section Example of present disclosure in the second phase
In P2 in the display panel 100 of Figure 1A each transistor status diagram.As shown in figure 4, in some embodiments, the second phase
P2 corresponds to the luminous period of display panel 100.
In second phase P2, make to compensate transistor TC3 and transistor T2 positioned at the scanning signal S1 [N] of high-voltage level
Shutdown.Make to compensate transistor TC1, TC2 and transistor T3 conducting positioned at the LED control signal EM [N] of luminous voltage level.
Specifically, compensation transistor TC1, TC2 is connected according to LED control signal EM [N], and according to system height in second phase P2
Voltage level OVDD generates thermal compensation signal Vcomp [n].Wherein, since the control terminal and second end of compensation transistor TC2 couple,
Therefore the voltage level of the thermal compensation signal Vcomp [n] generated is that system high voltage level OVDD subtracts facing for compensation transistor TC2
Boundary's voltage.
Since the voltage level of the first end of capacitor C1 is to be changed into thermal compensation signal by reference voltage level Vref at this time
The voltage level of Vcomp [n], therefore the voltage level of the second end of capacitor C1 is the voltage electricity by data-signal Vdata [m]
Flat, the voltage level for being changed into data-signal Vdata [m] is subtracted again plus the voltage level of thermal compensation signal Vcomp [n] with reference to electricity
Voltage level Vref.
In other words, the voltage level of the control terminal of transistor T2 at this time are as follows:
Wherein VDATABe for the voltage level of data-signal Vdata [m],It is the critical voltage to compensate transistor TC2.
In addition, transistor T3 is connected according to LED control signal EM [N] in second phase P2.Therefore, according to transistor T2
The driving current I1 that is exported of voltage level of control terminal be shown below:
Wherein, K is for conductive parameters (Conduction Parameter).VSG is the first end and control for transistor T2
Pressure difference between end processed.It is for the critical voltage of transistor T2.
Since compensation transistor TC2 is identical with the size of transistor T2, and it is configured at proximity, therefore electrically approximate phase
Together.Also that is, the critical voltage of compensation transistor TC2 is similar to the critical voltage of transistor T2.
In this way, make driving current I1 critical by transistor ageing by thermal compensation signal Vcomp [n]
The influence that voltage changes.Further, since data-signal Vdata [m] write-in and compensation critical voltage difference be to carry out respectively,
Therefore resolution ratio and compensation time are independent of each other, and can be suitable for height in the write-in for completing data-signal Vdata [m] in the short time
The display panel of resolution ratio can carry out high-frequency operation.
Further, since the data line that the first end of transistor T1 connects maintains the voltage electricity of data-signal Vdata [m]
It is flat, and the voltage level difference between the control terminal and data line of transistor T2 maintains
It therefore, can be by adjusting the electric leakage between control terminal and data line of the reference voltage level Vref to reduce transistor T2
Stream.In this way, which voltage level of the control terminal of transistor T2 in light emitting phase can be maintained, the control of transistor T2 is avoided
Cramping between end and data line is larger and occurs the phenomenon that flashing (Flicker) at low frequency operation (Idle mode).
Please refer to Fig. 5 A.Fig. 5 A is to exemplify another display panel 100 according to the implementation of the other parts of present disclosure
Schematic diagram.It with similar element in the embodiment of Figure 1A is indicated with identical component symbol in Fig. 5 A illustrated embodiment,
It is operated in previous paragraph expositor, is repeated no more in this.It is compared with Figure 1A illustrated embodiment, in some embodiments, such as
Shown in Fig. 5 A, the compensation circuit 120 in display panel 100 is also comprising compensation transistor TC4.
In structure, it is similar to compensation transistor TC2, the of the first end coupling compensation transistor TC1 of compensation transistor TC4
Two ends, and the control terminal for compensating transistor TC4 is mutually coupled in compensation transistor TC2's with the second end for compensating transistor TC4
Second end.In operation, compensation transistor TC4 is to the received system high voltage electricity of second end according to self compensation transistor TC1
Flat OVDD generates thermal compensation signal Vcomp [n].
Specifically, the size of compensation transistor TC4 is identical with compensation transistor TC2.In this way, pass through compensation crystal
Pipe TC4 and TC2 parallel connection compensates, and can make charging rate faster, and can faster draw the first end of capacitor C1 to compensation
The voltage level of signal Vcomp [n].
Please refer to Fig. 5 B.Fig. 5 B is to exemplify another display panel 100 according to the implementation of the other parts of present disclosure
Schematic diagram.It with similar element in the embodiment of Figure 1A is indicated with identical component symbol in Fig. 5 B illustrated embodiment,
It is operated in previous paragraph expositor, is repeated no more in this.It is compared with Figure 1A illustrated embodiment, in some embodiments, such as
Shown in Fig. 5 B, display panel 100 also includes transistor T4.
In structure, the control terminal of the first end coupling transistors T4 of transistor T4.The second end coupling of transistor T4 shines
The first end of element OLED.In operation, the first end of transistor T4 is to receive scanning signal S1 [N].Transistor T4 is to root
It is selectively turned on according to scanning signal S1 [N], to be reset to the anode of light-emitting component OLED by the second end of transistor T4
Low voltage level.In this way, the voltage level of the anode of light-emitting component OLED be controlled by transistor T4, so that light-emitting component
OLED maintains shutdown in write phase.
Please refer to Fig. 6.Fig. 6 is to exemplify another display panel 100 according to the implementation of the other parts of present disclosure
Signal sequence schematic diagram.As shown in fig. 6, in other parts embodiment, in address period Poff, the scanning of display panel 100
Signal S1 [1]~S1 [K] is sequentially connected, and LED control signal EM [G] is located at shutdown voltage level.In luminous period Pon, display
The scanning signal S1 [1] of panel 100~S1 [K] shutdown, LED control signal EM [G] are located at luminous voltage level.For example,
Scanning signal S1 [1] can be used to drive the pixel PI1 in Figure 1A and Figure 1B, the scanning signal in this embodiment, in Fig. 6
S1 [1] can be used to drive the grid of transistor T1 (such as the scanning signal S1 [N] in Figure 1A and Figure 1B).Scanning signal S1
[2] can be used to drive the pixel PI2 in Figure 1B.The rest may be inferred, and subsequent scanning signal can be used to drive display panel
Other subsequent pixels in 100.LED control signal EM [G] is to control the display panel above-mentioned multiple pixel (examples in 100
Such as the pixel PI1-PI3 in Figure 1B) it is shone (such as the LED control signal EM [N] in Figure 1A and Figure 1B).
In other words, each pixel in display panel 100 is sequentially connected respective according to scanning signal S1 [1]~S1 [K]
Write circuit 140 is to be respectively written into data-signal Vdata [m].Later, each pixel in display panel 100 is further according to luminous
Control signal EM [G] on-state drive circuit 160 is shown with lighting together.
It is worth noting that, the signal sequence that skilled artisan can be directly acquainted with Fig. 6 be intended to how base
Display panel 100 in above-mentioned multiple and different embodiments is to execute the operation and function, therefore no longer this is repeated.
Please refer to Fig. 7 A, Fig. 7 B.Fig. 7 A, Fig. 7 B are to exemplify another display according to the implementation of the other parts of present disclosure
Panel 100 and its signal sequence schematic diagram.In Fig. 7 A, Fig. 7 B illustrated embodiment, with similar element in the embodiment of Figure 1A
It is to be indicated with identical component symbol, operates in previous paragraph expositor, repeated no more in this.With Figure 1A illustrated embodiment
It compares, in other parts embodiment, as shown in Figure 7 A, transistor T3 is to receive the first LED control signal EM1 [N].It mends
The control terminal of transistor TC1 is repaid to receive the second LED control signal EM2 [N].
As shown in Figure 7 B, in corresponding embodiment, in first period P1, the first LED control signal EM1 [N] and second
LED control signal EM2 [N] is located at shutdown voltage level.In second phase P2, the second LED control signal EM2 [N] is by turning off
Voltage level switchs to luminous voltage level, and the first LED control signal EM1 [N] can be according to the luminescence display of display panel 100
Demand switches to luminous voltage level or shutdown voltage level.
In this way, by the way that LED control signal is divided into two kinds, in second phase P2, so that compensation transistor TC1
Conducting can be maintained to compensate the output of signal Vcomp [n] according to the second LED control signal EM2 [N], and to drive
Transistor T2 can be according to the on or off of first LED control signal EM1 [N] selectivity to switch bright show slinkingly in circuit 160
Show.
Although disclosed method is shown and described as herein first is that the step of arranging or event, but it is to be understood that institute
The sequence of these steps or event for showing should not be construed as limited significance.For example, part steps can be occurred with different order
And/or with other than illustrated herein and/or described step or event other steps or event occur simultaneously.In addition,
When implementing one or more aspects or embodiment described herein, and not all is all required the step of this shows.In addition,
One or more steps herein may also execute the step of one or more separates and/or in the stage.
In conclusion the disclosure passes through in the above-mentioned each embodiment of application, compensation electricity is shared by two or more pixels
The framework on road 120 can save the area of layout.In addition, carrying out data-signal write-in and benefit respectively by display panel 100
It repays, so that the compensation time does not influence resolution ratio, thus can be shortened the write time of data-signal, be suitable for high-resolution display
Device.
Although present disclosure is disclosed as above with embodiment, so it is not limited to present disclosure, affiliated skill
Art field technical staff is in the spirit and scope for not departing from present disclosure, when can make various variations and retouching, therefore this public affairs
The protection scope of content is opened subject to view appended claims institute defender.