CN109862281A - Camera Link Imaging System with Adjustable Exposure Time in Global Shutter Mode - Google Patents
Camera Link Imaging System with Adjustable Exposure Time in Global Shutter Mode Download PDFInfo
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Abstract
Global shutter mode lower time for exposure adjustable Camera Link imaging system, it is related to a kind of based on cmos image sensor global shutter mode lower time for exposure adjustable Camera Link imaging system, for imaging characteristic of the research detector under global shutter, it will be resetted simultaneously using Camera Link interface and bearing member, image data read to analyze, realize wide time for exposure adjustable range application, the last line by the frame useful signal hopping edge in Camera Link agreement in output picture frame is described；And the row useful signal exported only occurs in the corresponding output valid data stage, null phase is in the low level of blanking.Due to the corresponding stage timing control signal of the picture lag of output, the triggering of output row useful signal is carried out using the output data synchronization signal of every row, and different trigger conditions is set according to the difference of operating mode.The image of acquisition can be carried out a variety of correlated-double-sampling experiments by the present invention on host computer, convenient, flexible.
Description
Technical field
The present invention relates to a kind of adjustable Camera Link imaging systems of global shutter mode lower time for exposure, specifically relate to
And it is a kind of based on cmos image sensor global shutter mode lower time for exposure adjustable Camera Link imaging system.
Background technique
A kind of implementation of global shutter working method of cmos image sensor, is by reset signal and bearing member, image
It is exported by frame, first exports reset frame, then export picture frame, finally progress digital correlation is double sampled, carries out picture frame and reset
The phase reducing of frame.For the frame frequency for improving cmos image sensor as far as possible, under different time for exposure length, detector is in
Different operating modes；In order to study imaging characteristic of the detector under global shutter, need same using Camera Link interface
When by reset and bearing member, image data read to analyze.
Therefore, it is necessary to output frame effectively and row useful signal carry out Fine design, by the number of reset frame and picture frame
According to merging into a frame image, and during a frame, frame useful signal is only capable of a hopping edge occur, and high level has to
Covering resets and the effective image data of picture frame；The high level of row useful signal corresponds to the valid data of every row, and in every row
The invalid data stage and non-reset and image line stage be all necessary for low level.
Summary of the invention
The present invention simultaneously will to study imaging characteristic of the detector under global shutter using Camera Link interface
It resets and bearing member, image data is read to be analyzed, realize wide time for exposure adjustable range application, a kind of global shutter is provided
Mode lower time for exposure adjustable Camera Link imaging system.
Global shutter mode lower time for exposure adjustable Camera Link imaging system, including cmos image sensor, at
As controller and Camera Link interface circuit and transmission cable；
Clock signal needed for imaging controller generates cmos image sensor work, cmos image sensor Sequential output
For serial data comprising reset signal and bearing member, image to imaging controller, the imaging controller carries out serioparallel exchange and data
After conditioning, is sent data to by Camera Link interface circuit and transmission cable and carry out image on the computer with capture card
The analysis and processing of data；The cmos image sensor according to the difference of time for exposure, work in different operating modes, when
Time for exposure length is lower than the duration in SI stage, and cmos image sensor works under mode A, cycle of states RST_RD
Stage, SI stage, FOT stage and SIG_RD stage；The SI stage is the integration phase for starting permutation, and the RST_RD stage is multiple
Bit image reads the stage line by line, and the FOT stage is the charge stage that storage is collected, and the SIG_RD stage is that bearing member, image reads rank line by line
Section；
When length is higher than the duration in SI stage and is lower than reset frame and the lasting total time in SI stage between upon exposure,
Cmos image sensor works under B-mode, and cycle of states is RST_RD_A stage, SI stage, RST_RD_B stage, FOT rank
Section and SIG_RD stage, the RST_RD_A stage are that the reset image before the SI stage reads stage, RST_RD_B stage line by line
The stage is read line by line for the reset image after the SI stage；
Length is higher than reset frame and the lasting total time in SI stage and is lower than reset frame, picture frame and SI rank between upon exposure
Section lasting total time when, cmos image sensor work under C mode, cycle of states be the RST_RD stage, the FOT stage,
SIG_RD_A stage, SI stage and SIG_RD_B stage, the SIG_RD_A stage are that the bearing member, image before the SI stage is read line by line
Stage out, SIG_RD_B stage are that the bearing member, image after the SI stage reads the stage line by line；
When length is higher than the lasting total time of reset frame, picture frame and SI stage between upon exposure, cmos image sensor
Work under D mode, cycle of states be RST_RD stage, FOT stage, SI stage, SIG_RD stage and BLANK stage, it is described
The BLANK stage is the do-nothing operation stage.
Beneficial effects of the present invention:
One, Camera Link imaging system of the present invention jumps the frame useful signal in Camera Link agreement
It is described along the last line in output picture frame；And the row useful signal exported only goes out in the corresponding output valid data stage
Existing, null phase is in the low level of blanking.Due to the corresponding stage timing control signal of the picture lag of output, using every row
Output data synchronization signal carry out the triggering of output row useful signal, and different triggerings is set according to the difference of operating mode
Condition.The present invention can by reset and bearing member, image progress acquire simultaneously in real time, progress cmos image sensor performance assessment and
Analysis.
Two, the image of acquisition can be carried out a variety of phases by Camera Link imaging system of the present invention on host computer
Double sampled experiment is closed, it is convenient, flexible.
Three, Camera Link imaging system of the present invention is to meet a variety of time for exposure length corresponding a variety of
Reset the requirement with bearing member, image while acquisition using Camera link interface under cmos image sensor operating mode.
Detailed description of the invention
Fig. 1 is global shutter mode lower time for exposure of the present invention adjustable Camera Link imaging system block diagram；
Fig. 2 is that cmos image sensor works in the timing diagram of mode A；
Fig. 3 is that cmos image sensor works in the timing diagram of B-mode；
Fig. 4 is that cmos image sensor works in the timing diagram of C mode；
Fig. 5 is that cmos image sensor works in the timing diagram of D mode；
Fig. 6 is the cycle of states schematic diagram of mode A；
Fig. 7 is the cycle of states schematic diagram of B-mode；
Fig. 8 is the cycle of states schematic diagram of C mode；
Fig. 9 is the cycle of states schematic diagram of D mode.
Specific embodiment
Specific embodiment one illustrates present embodiment in conjunction with Fig. 1 to Fig. 9, and the global shutter mode lower time for exposure is adjustable
Camera Link imaging system, including cmos image sensor, imaging controller, Camera Link interface circuit and transmission
Cable and computer with capture card；
Clock signal needed for imaging controller generates cmos image sensor work, cmos image sensor Sequential output
The serial data containing reset signal and bearing member, image to imaging controller, after carrying out the data conditionings such as serioparallel exchange, with
Camera Link interface protocol sends data to the electricity with capture card by Camera Link interface circuit and transmission cable
The analysis and processing of image data are carried out on brain；
The cmos image sensor is according to the difference of time for exposure, and work is under different working modes.
Length is lower than the duration in SI stage between upon exposure, then works under mode A, and cycle of states is RST_RD rank
Section, SI stage, FOT stage and SIG_RD stage；
When length is higher than the duration in SI stage and is lower than reset frame and the lasting total time in SI stage between upon exposure,
It then works under B-mode, cycle of states is RST_RD_A stage, SI stage, RST_RD_B stage in stage FOT and SIG_RD rank
Section；
Length is higher than reset frame and the lasting total time in SI stage and is lower than reset frame, picture frame and SI rank between upon exposure
It when the lasting total time of section, then works under C mode, cycle of states is RST_RD stage, FOT stage, SIG_RD_A stage, SI
Stage and SIG_RD_B stage；
When length is higher than the lasting total time of reset frame, picture frame and SI stage between upon exposure, then work in D mode
Under, the cycle of states of experience is RST_RD stage, FOT stage, SI stage, SIG_RD stage and BLANK stage.In reset frame and
The line number that picture frame is effectively read is lower than width, at least 1 row shared by reset frame and picture frame.
The SI stage is the integration phase for starting permutation, and the RST_RD stage is that reset image reads stage, FOT rank line by line
The charge stage that section is collected for storage, SIG_RD stage are that bearing member, image reads the stage line by line；The SIG_RD_A stage is SI
Bearing member, image before stage reads the stage line by line, and the SIG_RD_B stage is that the bearing member, image after the SI stage reads the stage line by line；Institute
Stating the RST_RD_A stage is that the reset image before the SI stage reads the stage line by line, and the RST_RD_B stage is the reset diagram after the SI stage
As reading the stage line by line；The BLANK stage is the do-nothing operation stage.
In present embodiment, the changing rule of cmos image sensor work row address are as follows: in reset and picture frame, ground
Location is that every row is incremented by；The address of most footline is identical as previous row；The address in FOT stage and BLANK stage and most end row address phase
Together；The address in SI stage, it is identical as cmos image sensor most end row address under A and D operating mode；At B and C mode,
The address in SI stage is identical as last line row address (the non-detector most end row address) in stage previous stage RST_RD.
Illustrate present embodiment in conjunction with Fig. 2 to Fig. 5, row useful signal LVAL occurs during useful signal, non-effective letter
It is the low level of blanking during number；Its specific mode is same using the single clock burst pulse such as output data of sequential count signal
Step signal is triggered；I.e. for A and D operating mode, only reading stage (RST_RD and SIG_RD with picture signal are being resetted
Stage) carry out the triggering (clear operation) of row useful signal counter；And for B and C mode, not only in corresponding reset and figure
As the reading stage (RST_RD_A, SIG_RD_A, SIG_RD_B, RST_RD_B stage) of signal is triggered, while in SI rank
The first trip of section carries out row useful signal counter triggering (operation).It is corresponding that useful signal counter in count value reaches the row period
After pixel clock number, count value is kept, and is otherwise carried out incremental.
The effective initial position of the row of first trip is delayed with respect to the failing edge of first trip output data synchronization signal are as follows: mn+p, it is first
The effective end position of capable row is mn+p+k with respect to the failing edge delay of first trip output data synchronization signal, and m is output in formula
Delay line number of the valid data relative to data synchronizing signal SYNC, for the positive integer greater than 1；N is that each output row is corresponding
Pixel clock number, for the positive integer greater than 100；P is to detect effective output data during the channel correcting of data training
Position relative data synchronization signal SYNC delay pixel number, for the positive integer greater than 0；K is that a line valid data are corresponding
Pixel clock number, for the positive integer greater than 100.
Illustrate present embodiment in conjunction with Fig. 2 to Fig. 5, the hopping edge of the effective auxiliary signal Frame_buf of frame is only in image
The last line of frame occurs；By the rising and falling edges to the Frame_buf detected, then it is delayed, it is final to carry out
Export the generation of row useful signal.The jump with the row useful signal of output respectively of the rising and falling edges of frame useful signal FVAL
Along alignment.For under A, B and C operating mode, the effective rising edge alignment of first trip row of rising edge and reset frame is (with respect to reset frame
The failing edge delay of first trip output data synchronization signal is rn+p), the failing edge of failing edge and picture frame most footline useful signal
(failing edge of relative image frame most footline output data synchronization signal is delayed are as follows: rn+p+k for alignment；That is the negative arteries and veins of frame useful signal
Rushing persistence length is n-k pixel clock period.For D operating mode, the first trip output data in rising edge and BANK stage is same
The failing edge delay for walking signal is rn+p), the failing edge of failing edge and picture frame most footline useful signal is aligned (relative image frame
The failing edge of most footline output data synchronization signal is delayed are as follows: rn+p+k).
Imaging controller in present embodiment uses the FPGA 6vlx550tff1760 of Xilinx company；Cmos image
Sensor uses the detector of Chang Guangchen core company；Camera Link interface circuit uses DS90CR287 chip and Xiang Guan electricity
Road；Capture card uses the product of the industrial company of Triratna；Computer uses the desktop computer with PCIe slot.
Claims (5)
1. global shutter mode lower time for exposure adjustable Camera Link imaging system, including cmos image sensor, imaging
Controller and Camera Link interface circuit and transmission cable；
Clock signal needed for imaging controller generates cmos image sensor work, cmos image sensor Sequential output include
To imaging controller, the imaging controller carries out serioparallel exchange and data conditioning for reset signal and the serial data of bearing member, image
Afterwards, it is sent data to by Camera Link interface circuit and transmission cable and carries out image data on the computer with capture card
Analysis and processing；It is characterized in that:
The cmos image sensor works according to the difference of time for exposure in different operating modes, upon exposure between length
Lower than the duration in SI stage, cmos image sensor works under mode A, cycle of states be the RST_RD stage, the SI stage,
FOT stage and SIG_RD stage；The SI stage is the integration phase for starting permutation, and the RST_RD stage is that reset image is read line by line
Stage out, FOT stage are the charge stage that storage is collected, and the SIG_RD stage is that bearing member, image reads the stage line by line；
When length is higher than the duration in SI stage and is lower than reset frame and the lasting total time in SI stage between upon exposure, CMOS
Imaging sensor work under B-mode, cycle of states be the RST_RD_A stage, the SI stage, the RST_RD_B stage, the FOT stage and
SIG_RD stage, the RST_RD_A stage are that the reset image before the SI stage reads the stage line by line, and the RST_RD_B stage is SI
Reset image after stage reads the stage line by line；
Length is higher than reset frame and the lasting total time in SI stage and is lower than reset frame, picture frame and SI stage between upon exposure
When continuing total time, cmos image sensor works under C mode, and cycle of states is RST_RD stage, FOT stage, SIG_RD_
A stage, SI stage and SIG_RD_B stage, the SIG_RD_A stage are that the bearing member, image before the SI stage reads the stage line by line,
The SIG_RD_B stage is that the bearing member, image after the SI stage reads the stage line by line；
When length is higher than the lasting total time of reset frame, picture frame and SI stage between upon exposure, cmos image sensor work
Under D mode, cycle of states is RST_RD stage, FOT stage, SI stage, SIG_RD stage and BLANK stage, the BLANK
Stage is the do-nothing operation stage.
2. global shutter mode lower time for exposure adjustable Camera Link imaging system according to claim 1, special
Sign is: in the reset frame and picture frame, the line number effectively read is lower than width shared by reset frame and picture frame.
3. global shutter mode lower time for exposure adjustable Camera Link imaging system according to claim 1, special
Sign is, the changing rule of the row address of the cmos image sensor work are as follows: in reset frame and picture frame, address change
It is incremented by for every row；The address of most footline is identical as previous row address；The address in FOT stage and BLANK stage and most end row address
It is identical；
The address in SI stage, it is identical as cmos image sensor most end row address under mode A and D mode；In B-mode and C mould
Under formula, the address in SI stage is identical as the last line row address of previous stage respectively.
4. global shutter mode lower time for exposure adjustable Camera Link imaging system according to claim 1, special
Sign is that the row useful signal of the cmos image sensor occurs during useful signal, is blanking during non-effective signal
Low level；
Specific implementation are as follows: triggered using the single clock narrow pulse signal of sequential count signal；For mode A and D
Mode carries out the triggering of row useful signal counter in RST_RD stage and SIG_RD stage；For B and C mode, corresponding
RST_RD_A stage, SIG_RD_A stage, SIG_RD_B stage and RST_RD_B stage are triggered, while in the head in SI stage
The triggering of traveling every trade useful signal counter, useful signal counter reach row period corresponding pixel clock number in count value
Afterwards, count value is kept, and otherwise carries out count；
The effective initial position of first trip row is delayed with respect to the failing edge of first trip output data synchronization signal are as follows: mn+p, first trip row have
The end position of effect is mn+p+k with respect to the failing edge delay of first trip output data synchronization signal；
M is the delay line number for exporting valid data relative to data synchronizing signal SYNC, for the positive integer greater than 1；N is each defeated
It goes on a journey corresponding pixel clock number, for the positive integer greater than 100；P is during the channel correcting of data training, and detection has
The delay pixel number of the position relative data synchronization signal SYNC of output data is imitated, for the positive integer greater than 0；K is that a line is effective
The corresponding pixel clock number of data, for the positive integer greater than 100.
5. global shutter mode lower time for exposure adjustable Camera Link imaging system according to claim 1, special
Sign is that the hopping edge of the effective auxiliary signal Frame_buf of the frame of cmos image sensor goes out in the last line of picture frame
It is existing；By the rising and falling edges of the effective auxiliary signal Frame_buf of the frame detected, then it is delayed, final output
Row useful signal；
The rising edge and failing edge of frame useful signal are aligned with the hopping edge of the row useful signal of output respectively, in mode A, B mould
Under formula and C mode, failing edge delay of the rising edge with respect to the first trip output data synchronization signal of reset frame of frame useful signal is
rn+p；
The failing edge delay of the failing edge relative image frame most footline output data synchronization signal of frame useful signal is rn+p+k,
That is, the negative pulse persistence length of frame useful signal is n-k pixel clock period；
For D mode, the failing edge of the first trip output data synchronization signal of the rising edge and BANK stage of frame useful signal is delayed
Failing edge delay for rn+p, the failing edge relative image frame most footline output data synchronization signal of frame useful signal is rn+p+
k。
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| CN113179359A (en) * | 2021-04-21 | 2021-07-27 | 中国科学院长春光学精密机械与物理研究所 | Serial image data training system based on synchronous words |
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