CN109861076B - Picosecond-level pulse generation circuit for semiconductor laser - Google Patents

Abstract

The invention discloses a picosecond pulse generation circuit for a semiconductor laser, which comprises a trigger signal module and a CMOS pulse generation module, wherein the trigger signal module is connected with the CMOS pulse generation module, and the CMOS pulse generation module generates pulse output. The invention utilizes the competing relationship between the and gate input and output to produce a short pulse. The amplitude and pulse width of the pulse can be controlled by adjusting the bias voltage levels of the varactor and MOSFET. Can generate electric pulse signals with the pulse width ranging from 80ps to 270ns and the amplitude of up to 1.8V. The driving method can be conveniently applied to the driving of the semiconductor laser.

Description

A Picosecond Pulse Generation Circuit for Semiconductor Lasers

technical field

The invention relates to the field of electronic technology, in particular to a picosecond pulse generation circuit for semiconductor lasers.

Background technique

In modern technology, semiconductor lasers have become more and more mature, and among them, semiconductor lasers are mainly pulsed lasers, which are small in size, long in life, and can be pumped by simple current injection. The current is compatible with integrated circuits and thus can be monolithically integrated with them. And can also directly modulate the current with different frequencies to obtain laser pulse output modulated with different frequencies. It has been widely used in laser communication, optical storage, optical gyroscope, laser printing, ranging and radar. Therefore, it is of great significance to develop a pulse generating circuit with continuously adjustable frequency.

At present, the two main ways of generating electrical pulses are: MOS tube devices and microwave solid-state devices such as avalanche transistors. MOS tube devices are used as switching devices, and the electrical pulse signals generated are mostly used in series to generate nanosecond high-voltage pulses, which are not suitable for driving general semiconductor lasers. The pulse power generated by microwave solid-state devices is generally large, but the pulse width is generally in the nanosecond level and the circuit is relatively complex, which is not enough to drive picosecond or even sub-picosecond laser pulses. Therefore, in order to obtain an electrical pulse signal with a narrow pulse width and a considerable amplitude, other pulse generation methods must be explored.

SUMMARY OF THE INVENTION

The purpose of the present invention is to provide a picosecond pulse generation circuit for semiconductor lasers in view of the deficiencies of the prior art.

The concrete technical scheme that realizes the object of the present invention is:

A picosecond pulse generation circuit for a semiconductor laser, the circuit comprises: a trigger signal module and a CMOS pulse generation module, the trigger signal module is connected to a CMOS pulse generation module, and the CMOS pulse generation module generates a pulse output; wherein: the The trigger signal module includes crystal oscillator U1, potentiometer R1, resistor R2, capacitor C5, capacitor C6 and capacitor C7. The power supply voltage VCC is 3.3V, the frequency is 1.8MHZ, and the rising edge is 1ns. The VCC terminal of the crystal oscillator U1 is connected to the power supply VCC through three parallel capacitors C5, C6 and C7, the GND terminal is grounded, and the OUT terminal is connected to the potentiometer R1 to control the amplitude of the crystal oscillator output signal, and the adjusted output signal is connected to To the lower-level CMOS pulse generation module, the resistor R2 is connected in parallel with the output terminal of the trigger signal module and then grounded for current limiting protection;

The CMOS pulse generation module includes a CMOS pulse generation chip Pulse_G, a potentiometer R3, a potentiometer R4, a capacitor C7, a capacitor C8 and a capacitor C9, wherein the CMOS pulse generation chip Pulse_G has several pins corresponding respectively: pin 0 is the grounding of the Vss terminal ; Pin 1 is the IN terminal connected to the trigger signal output by the front-stage trigger module; Pin 2 is the TB control terminal connected to the effective end of the potentiometer R3, one end of the left and right ends of the potentiometer R3 is connected to the power supply VDD, and the other end is grounded; Pin 3 is the OUT end for the pulse Signal output terminal, pin 4 is the PAD_VDD terminal connected to the power supply VDD; pin 5 is the CORE_VDD terminal connected to the power supply VDD through parallel capacitor C8, capacitor C9 and capacitor C10; One end is connected to the power supply VDD, and one end is grounded; the potentiometers R3 and R4 control the input voltage of TA and TB by controlling the size of the resistance.

The CMOS pulse generation chip Pulse_G includes three on-chip inverters B1, inverter B2, inverter B3, MOSFET tube M1, MOSFET tube M2, MOSFET tube M3, varactor C1, varactor C2, and varactor. Capacitor C3, varactor C4 and AND gate T1, wherein each inverter consists of a PMOS and an NMOS, the G poles of the PMOS and NMOS are connected as the input of the inverter, and the S pole of the PMOS is an NMOS. The D pole is connected as the output terminal; the three inverters are sequentially connected according to the output terminal of the inverter B1 and the input terminal of the inverter B2, and the output terminal of the inverter B2 is connected to the input terminal of the inverter B3. The input terminal of the inverter B1 is connected to the trigger signal, and the output terminal of the inverter B3 is connected to the input terminal A of the AND gate T1; The D pole is connected to the power supply VDD in parallel, and the S poles of the NMOS transistors of the inverter B1, the inverter B2, and the inverter B3 are sequentially connected to the D poles of the MOSFET transistor M1, MOSFET M2, and MOSFET M3, and then connected in parallel to the TA. ;One end of the varactor C1, the varactor C2, the varactor C3, and the varactor C4 are connected in parallel to the output of the inverter B1, the inverter B2, the inverter B3, and the gate T1, and the other end is connected in parallel To TB; connect the trigger signal to the input terminal B of the AND gate T1.

Beneficial effects of the present invention:

The invention makes full use of the most advanced integrated circuit technology at present, generates a peak pulse based on the competition-risk relationship between the input and output gates in the digital logic circuit, and uses the delay time of the CMOS inverter and the CMOS power supply voltage to control the output pulse width respectively. And the amplitude is used as the trigger signal of the semiconductor laser, which has great application prospect.

Description of drawings

Fig. 1 is the structure diagram of the present invention;

2 is a circuit diagram of a CMOS pulse generating chip Pulse_G of the present invention;

FIG. 3 is a logical schematic diagram of the CMOS pulse generating circuit of the present invention.

Detailed ways

In order to make the objectives, technical solutions and advantages of the present invention more clearly understood, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

The invention adopts a trigger signal circuit and a CMOS pulse generating circuit based on a 40nm process to generate an ultra-short picosecond pulse signal, which is suitable for driving applications of semiconductor lasers.

Example

Referring to FIG. 1, it is a structural diagram of the present invention. The present invention includes two modules. In the figure, the left side is the data trigger signal module, and the right side is the pulse generation module. The active crystal oscillator U1 generates a square wave trigger signal as the data input of the CMOS pulse generation module. Finally, the CMOS pulse generation module generates a pulse signal with continuously adjustable amplitude and pulse width. The amplitude and pulse width of the signal can be adjusted by TA and TB. .

Each component of this embodiment will be described in detail below.

trigger signal module

In this embodiment, the trigger signal module is a square wave signal generating circuit, which includes an active crystal oscillator U1 and a potentiometer R1, the output end of the active crystal oscillator U1 is connected to the potentiometer R1, and the potentiometer R1 adjusts the amplitude of the square wave signal , The active crystal oscillator U1 generates a square wave signal with a fixed frequency, and generates a square wave signal with an amplitude of 1.7V and a repetition frequency of 1.8MHz through the potentiometer R1, and the rising edge of the square wave is about 1ns. R2 is the current limiting resistor to ground.

CMOS pulse generation module

Referring to FIG. 1, the right part is a CMOS pulse generating module, which includes: a CMOS pulse generating circuit chip Pulse_G designed by the present invention, potentiometers R3 and R4, capacitors C7, C8, and C9. Among them, the pin 0 of the chip Pulse_G is the grounding of the VSS terminal, the pin 1 of the chip Pulse_G is the square wave data signal generated by the IN terminal connected to the front-stage trigger signal module, and the pin 2 of the chip Pulse_G is the effective end of the TB input connected to the potentiometer R4. One end of the terminal is connected to the power supply VDD, and the other end is grounded; the pin 3 of the chip Pulse_G is the output of the OUT terminal pulse signal; the pin 4 of the chip Pulse_G is connected to VDD; the pin 5 of the chip Pulse_G is the CORE_VDD terminal through the parallel capacitors C8, C9, C10 Connect to the power supply VDD , the pin 6 of the chip Pulse_G is TA input, connected to the effective end of potentiometer R3, the left and right ends of R3 are connected to the power supply VDD, and one end is grounded. The potentiometers R3 and R4 control the input voltage of TA and TB by controlling the size of the resistance.

Referring to Figure 2, in the circuit diagram of the CMOS pulse generation chip Pulse_G, a delay circuit is composed of three inverters B1, B2 and B3. After a certain delay, the input square wave pulse signal is generated by the AND gate T1. It is the same as the pulse waveform of the same width as the delay. The pulse width and shape of the generated waveform can be controlled by adjusting the bias voltages of the varactors C1-C4 and the MOS transistors M1-M3. The principle logic diagram is shown in Figure 3. It can be seen from the simplified schematic diagram that Figure 3 contains two logic modules, a NOT gate and an AND gate. The connection method of the two is shown in Figure 3. The circuit uses the competition between the input and output gates to generate a short pulse. The input waveform is divided into two signals, which follow different transmission paths. The first signal is directly connected to the input terminal of the AND gate, and the second signal is connected to the input terminal of the NOT gate. The propagation delay introduced by the NOT gate causes only a small portion of the two input signals to the AND gate to cross, resulting in a short pulse. Among them, the MOS transistors M1, M2, and M3 can be equivalent to variable resistors under the TA voltage to control the amplitude and pulse width of the pulse waveform by controlling the operating current of the circuit. The size of the varactors C1-C4 is equivalent to an adjustable capacitance by controlling the TB voltage, thereby controlling the delay time of the inverters B1, B2, and B3, thereby controlling the width and amplitude of the pulse.

The power supply voltage VDD of the CMOS pulse generating module is 1.1V-2V.

In this embodiment, the value of the potentiometer R1 is 100Ω, the value of the resistor R2 is 50Ω, and the value of the capacitors C5, C6, and C7 are respectively 10uF, 1uF, and 1nF.

The potentiometers R3 and R4 are 100kΩ, and the capacitors C8, C9, and C10 are 10uF, 1uF, and 1nF, respectively.

The supply voltage VCC is 3.3V and the frequency is 1.8MHz.

The working process of this embodiment is as follows:

Step 1. The trigger signal module generates a square wave data signal through the active crystal oscillator and adjusts the square wave data signal with the working voltage of 1.7V and the working frequency of 1.8MHz through the potentiometer R1;

Step 2. After the trigger data signal arrives, the CMOS pulse generation module directly inputs one channel to the input end of the AND gate of T1, and the other channel reaches the input end of the AND gate T1 after a certain delay through B1, B2, and B3. competition and risk-taking, thereby generating a spike signal at the AND gate;

Step 3. Adjust the potentiometers R3 and R4 respectively to change the equivalent variable resistance size of M1, M2 and M3 and the size of the varactors C1, C2, C3 and C4 to change the delay time and working current of the inverter. The pulse width and amplitude of the pulse signal can be adjusted;

Step 4: Adjust the power supply voltage VDD of the pulse generating module from 1.1V to 2V, and adjust the width and amplitude of the pulse.

Actual tests show that the picosecond-level pulse signal generated by this embodiment has an adjustable range of pulse width of 80ps-270ns and an adjustable range of pulse amplitude of 600mV-1.8V. The pulse waveform is stable, the jitter is small, and the adjustable precision is high. Therefore, it is very suitable for pulsed driving applications of semiconductor lasers.

So far, the present embodiment has been described in detail with reference to the accompanying drawings. From the above description, those skilled in the art should have a clear understanding of the present invention.

In addition, the above definitions of various elements and methods are not limited to various specific structures, shapes or manners mentioned in the embodiments, and those of ordinary skill in the art can simply modify or replace them, for example:

(1) In this embodiment, the chip process size used is a 40nm process, and other process sizes can also be selected to realize the integration of the chip circuit;

(2) The size of the varactor can also be set according to specific requirements, so that other parameter pulse signals can be realized.

To sum up, the present invention mainly generates a square wave data signal by using a crystal oscillator. After being delayed by three inverters, a positive pulse signal with the same width as the delay time is generated at the AND gate and then output to the semiconductor laser. The width and amplitude can be controlled by adjusting the size of the equivalent resistance, the varactor and the power supply voltage. Experiments show that the pulse generator of the invention meets the pulse driving requirements of the semiconductor laser.

The above embodiment is only a preferred solution of the present invention, and is not intended to limit the scope of the essential technical content of the present invention. Although the present invention has been described in detail with reference to the embodiments, those of ordinary skill in the art should understand that any modification, equivalent replacement, improvement, etc. made to the present invention within the spirit and principle of the present invention defined in the claims should be Included in the protection scope of the present invention.

Claims (1)

1. A picosecond pulser circuit for a semiconductor laser, comprising: the CMOS pulse generator comprises a trigger signal module and a CMOS pulse generation module, wherein the trigger signal module is connected with the CMOS pulse generation module, and the CMOS pulse generation module generates pulse output; wherein: the trigger signal module comprises a crystal oscillator U1, a potentiometer R1, a resistor R2, a capacitor C5, a capacitor C6 and a capacitor C7, the VCC end of the crystal oscillator U1 is connected with a power VCC through three capacitors C5, a capacitor C6 and a capacitor C7 which are connected in parallel, the GND end is grounded, the OUT end controls the amplitude of an output signal of the crystal oscillator through being connected with the potentiometer R1, the regulated output signal is connected to the lower-level CMOS pulse generation module, and the resistor R2 is connected with the output end of the trigger signal module in parallel and then grounded;

the CMOS Pulse generation module comprises a CMOS Pulse generation chip Pulse _ G, a potentiometer R3, a potentiometer R4, a capacitor C7, a capacitor C8 and a capacitor C9, wherein the CMOS Pulse generation chip Pulse _ G is provided with a plurality of pins which correspond to the pins respectively: pin 0 is Vss terminal ground; pin 1 is IN end connected with the trigger signal output by the preceding stage trigger module; the pin 2 is an effective end of a TB control terminal potentiometer R3, one end of the left end and the right end of the potentiometer R3 is connected with a power supply VDD, and the other end is grounded; a pin 3 is an OUT end and a pulse signal output end, and a pin 4 is a PAD _ VDD end and a power supply VDD; a pin 5 is a CORE _ VDD end and is connected with a power supply VDD through a parallel capacitor C8, a capacitor C9 and a capacitor C10; pin 6 is a TA control end and is connected with an effective end of a potentiometer R4, one end of the left end and the right end of the potentiometer R4 is connected with a power supply VDD, and the other end is grounded; wherein:

the CMOS Pulse generation chip Pulse _ G comprises a phase inverter B1, a phase inverter B2, a phase inverter B3, a MOSFET tube M1, a MOSFET tube M2, a MOSFET tube M3, a varactor tube C1, a varactor tube C2, a varactor tube C3, a varactor tube C4 and an AND gate T1, wherein each phase inverter consists of a PMOS and an NMOS, the G poles of the PMOS and the NMOS are connected to serve as the input end of the phase inverter, and the S pole of the PMOS and the D pole of the NMOS are connected to serve as the output end; the inverter is connected with the input end of an inverter B2 according to the output end of an inverter B1 in sequence, the output end of an inverter B2 is connected with the input end of an inverter B3 in a cascade mode, the input end of the inverter B1 is connected with a trigger signal, and the output end of an inverter B3 is connected with the input end A of an AND gate T1; d poles of PMOS tubes of the phase inverter B1, the phase inverter B2 and the phase inverter B3 are connected with a power supply VDD in parallel, and S poles of NMOS tubes of the phase inverter B1, the phase inverter B2 and the phase inverter B3 are connected with D poles of a MOSFET tube M1, a MOSFET tube M2 and a MOSFET tube M3 in sequence and then connected to TA in parallel; one end of a varactor C1, a varactor C2, a varactor C3 and a varactor C4 are connected in parallel to the output ends of an inverter B1, an inverter B2, an inverter B3 and an AND gate T1 in sequence, and the other end of the varactor C4 is connected in parallel to a TB; the input terminal B of the and gate T1 is connected to the trigger signal.

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