CN109814315B - Multi-gate pixel structure and driving method thereof - Google Patents
Multi-gate pixel structure and driving method thereof Download PDFInfo
- Publication number
- CN109814315B CN109814315B CN201910193581.8A CN201910193581A CN109814315B CN 109814315 B CN109814315 B CN 109814315B CN 201910193581 A CN201910193581 A CN 201910193581A CN 109814315 B CN109814315 B CN 109814315B
- Authority
- CN
- China
- Prior art keywords
- pixel
- gate
- sub
- line
- pixels
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000000034 method Methods 0.000 title claims abstract description 17
- 239000010409 thin film Substances 0.000 claims description 21
- 239000011159 matrix material Substances 0.000 claims description 3
- 238000005452 bending Methods 0.000 claims 3
- 239000004973 liquid crystal related substance Substances 0.000 abstract description 4
- 230000009286 beneficial effect Effects 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 5
- 230000009977 dual effect Effects 0.000 description 4
- 239000003990 capacitor Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 1
Images
Landscapes
- Liquid Crystal (AREA)
- Liquid Crystal Display Device Control (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Abstract
本发明提供一种多栅极像素结构及其驱动方法，属于显示技术领域。该发明针对田字形像素排布方式创新地采用了具有四倍栅走线的像素结构，并调整了栅极驱动信号的驱动方式，实现了多栅极像素结构的液晶显示驱动，既满足了对每一个像素的数据信号写入，4个像素共用数据走线，由于走线共用，使得像素开口率得到提升，使得Source IC数量为常用的单栅极走线像素结构的1/4，进一步节省IC驱动数据信号，降低了工艺成本。并且采用本发明技术方案使W/Y像素和R/G/B像素都由不同的栅极走线控制，利于对W/Y像素显示的控制，使IC算法简单化。
The invention provides a multi-gate pixel structure and a driving method thereof, belonging to the technical field of display. The invention innovatively adopts a pixel structure with quadruple gate lines for the arrangement of square-shaped pixels, and adjusts the driving mode of the gate driving signal to realize the liquid crystal display driving of the multi-gate pixel structure, which not only satisfies the requirements for The data signal of each pixel is written, and 4 pixels share the data wiring. Due to the sharing of wiring, the pixel aperture ratio is improved, so that the number of Source ICs is 1/4 of the commonly used single-gate wiring pixel structure, further saving The IC drives the data signal, reducing the process cost. In addition, by adopting the technical solution of the present invention, the W/Y pixels and the R/G/B pixels are controlled by different gate lines, which is beneficial to the control of the W/Y pixel display and simplifies the IC algorithm.
Description
Technical Field
The invention belongs to the technical field of display, and particularly relates to a multi-Gate (multi-Gate) pixel structure and a driving method thereof.
Background
A Liquid Crystal Display (LCD) includes a gate driving circuit, a data driving circuit, and a pixel region. The gate driving circuit comprises a plurality of gate lines and sequentially generates gate driving signals, the data driving circuit comprises a plurality of data lines and is used for generating data driving signals, the gate lines are mutually parallel straight lines, and the data lines are mutually parallel straight lines; the pixels in the pixel region are formed by interleaving gate lines and data lines, and are driven by gate driving signals generated by the corresponding gate lines to receive data driving signals generated by the corresponding data lines. In order to reduce the cost, a Dual gate pixel structure is widely applied to the LCD, but the Dual gate pixel still requires one half of a driving IC (integrated circuit) data line, and the cost reduction is limited.
Disclosure of Invention
In view of the problems in the prior art, an object of the present invention is to provide a multi-gate pixel structure and a driving method thereof, which can achieve liquid crystal display driving of a 4-fold gate pixel structure, further save IC driving data signals, and further reduce cost.
In order to achieve the purpose, the technical scheme of the invention is as follows:
a multi-grid pixel structure comprises a plurality of pixel repeating units, wherein each pixel repeating unit comprises a pixel unit, a data line and a COM line, each pixel unit is composed of four sub-pixels and is arranged in a 2 x 2 matrix mode, and a thin film transistor and a pixel electrode are arranged in each sub-pixel arean、Gn+1、Gn+2And Gn+3G, the data line is arranged between the first row of sub-pixels and the second row of sub-pixels, wherein the data line is connected with the drain electrodes of the four transistors, the pixel electrode is connected with the source electrode of the corresponding thin film transistornThe gate line is connected with the gate of the thin film transistor in the first sub-pixel region, Gn+1The gate line is connected with the gate of the thin film transistor in the second sub-pixel region, Gn+2The gate line is connected with the gate of the thin film transistor in the third sub-pixel region, Gn+3The gate lines are connected with the gates of the thin film transistors in the fourth sub-pixel area, and the four gate lines are composed of straight lines and zigzag routing lines.
Further, G in four gate linesnAnd Gn+3For Zig zag routing, Gn+1And Gn+2Is a straight wire.
A driving method of a multi-gate pixel structure comprises the following steps:
step 1: at a first moment in time GnGate lines are high, the remaining gate lines are low, and GnThe thin film transistor connected with the gate line is turned on, and the Data signal is written into the Data line;
step 2: second moment of time, Gn+1Gate lines are high, the remaining gate lines are low, and Gn+1The thin film transistor connected with the gate line is turned on, and the Data signal is written into the Data line;
and step 3: at a third moment in time Gn+2Gate lines are high, the remaining gate lines are low, and Gn+2The thin film transistor connected with the gate line is turned on, and the Data signal is written into the Data line;
and 4, step 4: at a fourth moment in time Gn+3Gate lines are high, the remaining gate lines are low, and Gn+3The thin film transistor connected to the gate line is turned on, and a Data signal is written into the Data line.
Further, the four sub-pixels are a red sub-pixel R, a green sub-pixel G, a blue sub-pixel B and a white sub-pixel W, or a combination of R, G, B and a yellow sub-pixel Y.
Further, the pixel driving sequence may also be G in sequencen+3、Gn+2、Gn+1To GnAnd driving in reverse direction.
The invention also provides a display panel comprising a quadruple gate drive pixel structure as described above.
The COM routing layout and the non-Dn data signal routing position are overlapped with the pixel electrode of R, G, B, W pixels to form a storage capacitor.
In summary, due to the adoption of the technical scheme, the invention has the beneficial effects that:
1. the pixel structure with the quadruple grid wiring is adopted, the driving mode of the grid driving signal is adjusted, the liquid crystal display driving of the multi-grid pixel structure is realized, the writing of data signals of each pixel is met, 4 pixels share the data wiring, the pixel aperture opening ratio is improved due to the wiring sharing, the IC driving data signals are further saved, and the process cost is reduced.
2. By adopting the technical scheme of the invention, the Source IC number is 1/4 of the common single-grid wiring pixel structure, and the production process cost can be reduced; and the W/Y pixel and the R/G/B pixel are controlled by different grid wires, so that the control of W/Y pixel display is facilitated, and an IC algorithm is simplified.
Drawings
Fig. 1 is a schematic diagram of a dual gate pixel structure in the prior art.
Fig. 2 is a schematic view of a pixel repeating unit structure with four times of gate traces according to the present invention.
Fig. 3 is a schematic structural diagram of a pixel group having four times of gate traces according to the present invention.
FIG. 4 is a timing diagram of driving signals of a pixel group gate circuit with four times of gate traces according to the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention will be described in further detail with reference to the following embodiments and accompanying drawings.
FIG. 2 shows the invention with quadruple gate tracesThe structure of the pixel repeating unit is shown schematically. As shown in fig. 2, each pixel repeating unit includes a pixel unit, four Gate traces, a data line, and a COM line, the pixel unit is composed of R, G, B and W four sub-pixels, is 2 × 2 matrix arrangement, and is shaped like a "field", a Thin Film Transistor (TFT) and a pixel electrode are disposed in each sub-pixel region, and four Gate traces G are disposed in each sub-pixel regionn、Gn+1、Gn+2And Gn+3The data (Dn) routing is connected with 4 TFTs in one pixel repeating unit and provides data signals for the RGBW sub-pixels.
The Gn grid electrode is connected with the grid electrode of the R pixel TFT through a wire, the Dn data is connected with the drain electrode of the R pixel TFT through a wire, and the source electrode of the R pixel TFT is connected with the pixel electrode of the R pixel; the Gn +1 grid electrode is connected with the grid electrode of the G pixel TFT through a wire, the Dn data is connected with the drain electrode of the G pixel TFT through a wire, and the source electrode of the G pixel TFT is connected with the pixel electrode of the G pixel; the Gn +2 grid electrode is connected with the grid electrode of the B pixel TFT through a wire, the Dn data is connected with the drain electrode of the B pixel TFT through a wire, and the source electrode of the B pixel TFT is connected with the pixel electrode of the B pixel; the Gn +3 grid electrode wire is connected with the grid electrode of the W pixel TFT, the Dn data wire is connected with the drain electrode of the W pixel TFT, and the source electrode of the W pixel TFT is connected with the pixel electrode of the W pixel.
The COM routing layout and the non-Dn data signal routing position are overlapped with the pixel electrode of R, G, B, W pixels to form a storage capacitor.
Fig. 3 is a schematic structural diagram of a pixel group having four times of gate traces according to the present invention. A pixel group is composed of a plurality of pixel repeating units. FIG. 4 is a timing diagram of driving signals of a pixel group gate circuit with four times of gate traces according to the present invention. After the Gn inputs a grid opening signal, the Dn routes and inputs a data signal, and the data signal is written into an R Pixel (red Pixel). Then Gn is closed, Gn +1 inputs a grid opening signal, Dn wires input a data signal, and the data signal is written into a G Pixel (Green Pixel). By analogy, Gn +1 is closed, Gn +2 inputs a grid opening signal, Dn lines input a data signal, and the data signal is written into a B Pixel (Blue Pixel). By analogy, Gn +2 is closed, Gn +3 inputs a grid opening signal, Dn wires input a data signal, and the data signal is written into a W Pixel (White Pixel).
In the driving display process, the driving sequence is from top to bottom according to Gn, Gn +1, Gn +2 and …, and the driving sequence can also be from …, Gn +3, Gn +2, Gn +1 to Gn in reverse direction.
In the TFT-LCD industry, the driving method IC is expensive, for example, FHD resolution, and the conventional dual Gate driving method is adopted, so 1920 × 3/2-2880 channel ICs are required, and 2 1440 channel ICs can be used for driving. The invention adopts a 4-time gate driving mode, an IC with 1920 × 3/4-1440 channels is needed, only 1 IC with 1440 channels is needed, and the cost of the IC is reduced by one time.
While the invention has been described with reference to specific embodiments, any feature disclosed in this specification may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise; all of the disclosed features, or all of the method or process steps, may be combined in any combination, except mutually exclusive features and/or steps.
Claims (5)
1. A multi-grid pixel structure comprises a plurality of pixel repeating units, wherein each pixel repeating unit comprises a pixel unit, a data line and a COM line, each pixel unit is composed of four sub-pixels and is arranged in a 2 x 2 matrix mode, and a thin film transistor and a pixel electrode are arranged in each sub-pixel regionn、Gn+1、Gn+2And Gn+3G, the data line is arranged between the first row of sub-pixels and the second row of sub-pixels, wherein the data line is connected with the drain electrodes of the four transistors, the pixel electrode is connected with the source electrode of the corresponding thin film transistornThe gate line is connected with the gate of the thin film transistor in the first sub-pixel region, Gn+1The gate line is connected with the gate of the thin film transistor in the second sub-pixel region, Gn+2The gate line is connected with the gate of the thin film transistor in the third sub-pixel region, Gn+3The gate line is connected to a gate electrode of the thin film transistor in the fourth sub-pixel region,the four gate lines are composed of straight lines and zigzag routing lines; g in the four gate linesnAnd Gn+3For Zig zag routing, Gn+1And Gn+2Is a straight line, wherein, the gate line GnTaking the sub-pixel area of the first column in the nth row as a straight line, then bending the sub-pixels surrounding the second column in the nth row upwards, repeating the processes of straight line extension and bending surrounding, and forming zigzag routing on the sub-pixels in the nth row; gate line Gn+3The sub-pixels surrounding the n +1 th row and the first column are bent downwards, the sub-pixel areas in the n +1 th row and the second column are straight lines, the processes of straight line extension and bending surrounding are repeated, and zigzag routing is formed on the sub-pixels in the n +1 th row.
2. The multi-gate pixel structure of claim 1, wherein the four sub-pixels are a red sub-pixel R, a green sub-pixel G, a blue sub-pixel B, and a white sub-pixel W, or a combination of two sub-pixels R, G, B and a yellow sub-pixel Y.
3. A method of driving a multi-gate pixel structure according to claim 1, comprising the steps of:
step 1: at a first moment in time GnGate lines are high, the remaining gate lines are low, and GnThe thin film transistor connected with the gate line is turned on, and the Data signal is written into the Data line;
step 2: second moment of time, Gn+1Gate lines are high, the remaining gate lines are low, and Gn+1The thin film transistor connected with the gate line is turned on, and the Data signal is written into the Data line;
and step 3: at a third moment in time Gn+2Gate lines are high, the remaining gate lines are low, and Gn+2The thin film transistor connected with the gate line is turned on, and the Data signal is written into the Data line;
and 4, step 4: at a fourth moment in time Gn+3Gate lines are high, the remaining gate lines are low, and Gn+3The thin film transistor connected to the gate line is turned on, and a Data signal is written into the Data line.
4. The method of claim 3, wherein the pixel driving sequence is G in ordern+3、Gn+2、Gn+1To GnAnd driving in reverse direction.
5. A display panel comprising the multi-gate pixel structure of claim 1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910193581.8A CN109814315B (en) | 2019-03-14 | 2019-03-14 | Multi-gate pixel structure and driving method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910193581.8A CN109814315B (en) | 2019-03-14 | 2019-03-14 | Multi-gate pixel structure and driving method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN109814315A CN109814315A (en) | 2019-05-28 |
| CN109814315B true CN109814315B (en) | 2021-04-30 |
Family
ID=66608965
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910193581.8A Active CN109814315B (en) | 2019-03-14 | 2019-03-14 | Multi-gate pixel structure and driving method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN109814315B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111477144A (en) * | 2020-04-09 | 2020-07-31 | 福建华佳彩有限公司 | Display screen structure and driving method thereof |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101171176B1 (en) * | 2004-12-20 | 2012-08-06 | 삼성전자주식회사 | Thin film transistor array panel and display device |
| KR101286516B1 (en) * | 2006-11-27 | 2013-07-16 | 엘지디스플레이 주식회사 | Liquid Crystal Display and Driving Apparatus thereof |
| KR20080077807A (en) * | 2007-02-21 | 2008-08-26 | 삼성전자주식회사 | Display |
| CN104391408B (en) * | 2014-11-25 | 2017-10-31 | 上海天马微电子有限公司 | Liquid crystal display panel and liquid crystal display device |
| JP6612613B2 (en) * | 2015-12-24 | 2019-11-27 | 株式会社ジャパンディスプレイ | Display device |
| CN106502002A (en) * | 2016-12-13 | 2017-03-15 | 深圳市华星光电技术有限公司 | A kind of smooth alignment method, display panels and preparation method thereof |
-
2019
- 2019-03-14 CN CN201910193581.8A patent/CN109814315B/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| CN109814315A (en) | 2019-05-28 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US11282464B2 (en) | Display panel | |
| JP5483517B2 (en) | Liquid crystal display | |
| JP6332953B2 (en) | Array substrate, drive control method thereof, and display device | |
| US20070091044A1 (en) | Liquid crystal display with improved pixel configuration | |
| EP2690490A2 (en) | Display device | |
| KR102566296B1 (en) | Display device | |
| US9489911B2 (en) | Display device | |
| US20140218347A1 (en) | Liquid crystal display and driving method thereof | |
| JP6588344B2 (en) | Transistor substrate and display device | |
| KR102764289B1 (en) | Liquid crystal display panel | |
| CN109814315B (en) | Multi-gate pixel structure and driving method thereof | |
| US9715859B2 (en) | LCD panel of dot inversion mode | |
| KR101272177B1 (en) | Rotation driving method for liquid crystal display device | |
| KR100947771B1 (en) | LCD panel and its driving device | |
| US10891892B2 (en) | Display device | |
| CN212084636U (en) | Demux display screen structure | |
| JP5328555B2 (en) | Display device | |
| CN111477137A (en) | A kind of Demux display screen structure and its driving method | |
| KR101245942B1 (en) | Liquid crystal panel and Liquid crystal display device and method driving for the same | |
| KR102045810B1 (en) | Display device | |
| CN106444194A (en) | Pixel array structure, preparing method thereof, and display panel | |
| KR101001052B1 (en) | LCD panel and driving method | |
| KR20170018155A (en) | Display device | |
| KR20050043410A (en) | Switching element for driving circuit of liquid crystal display |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |