CN109800468B - Register retiming-based multi-pipeline sequential circuit boxing operation method - Google Patents

Abstract

The invention proposes a multi-level sequential circuit packing operation method based on register retiming. The binning algorithm packs the look-up table circuit; according to the direction of the critical path of the sequential circuit, the type of the sequential circuit of the pipeline level after packing is judged, and the critical path delay calculation method of the sequential circuit after packing is used to calculate the key of the sequential circuit of the pipeline level after packing. Path Delay; retimes intermediate registers in the circuit based on the critical path delay. The invention can distribute the time delay of each pipeline stage as evenly as possible through register retiming, thereby improving the throughput rate of pipeline application, so that the application system can process more data in unit time; The mobile feature can reduce the critical path delay of the entire sequential circuit pipeline.

Description

A multi-pipeline sequential circuit packing operation method based on register retiming

technical field

The invention relates to the technical field of FPGA design flow, in particular to a multi-pipeline sequential circuit packing operation method based on register retiming.

Background technique

In the FPGA design process, the hardware description language (Hardware Description Language, HDL) designed by the hardware programmer generates a gate-level netlist (NAND gate circuit netlist) through logic synthesis, and the gate-level netlist is mapped to generate a look-up table (Look Up Table). , LUT) circuit, the look-up table circuit is packed into the logic block of the larger unit of the FPGA, and then through the layout and routing, the bit stream file that can be downloaded to the FPGA is finally generated, as shown in Figure 1. The hardware circuit design from the hardware description language designed by the programmer to the netlist downloaded into the chip needs to be processed in the stages of logic synthesis, mapping, boxing, and placement and routing, and the look-up table circuit generated after the mapping can be allocated to the chip through boxing. FPGA logic block.

The look-up table circuit packs most of the network cables into logic blocks by boxing. Literature [Betz V, Rose J. VPR: anew packing, placement and routing tool for FPGA research [C]. Proceedings of the International Workshop on Field-Programmable Logic and Applications, London, UK, 1997: 213-222.] Through the close Contact network cables are boxed to reduce the number of external wiring. Literature [Marquardt A, Betz V, Rose J. Using cluster based logic blocks and timing-drivenpacking to improve FPGA speed and density [C]. Proceedings of International ACMSymposium on Field-Programmable Gate Arrays Citation, Monterey, California, USA, 1999: 37-46.] While considering the degree of connection between the network cables, try to put the critical path into the box to reduce the critical path delay. The literature [Li Peng et al., FPGA packing algorithm based on network cable absorption and port occupancy analysis, "Journal of Computer Aided Design and Graphics", Volume 23, Issue 3, September 2011.] starts from the two aspects of network cable absorption and port occupancy. , which can more effectively improve the routing rate of subsequent circuits. Because the line delay from packing to the inside is much smaller than the outside line delay. The above solutions do not take into account that the circuit path delay after packing will change greatly, the critical path of the pipeline will also change, and the delay of each pipeline will become inconsistent due to packing, and the entire pipeline will be affected. Unified critical path delay constraint, the optimal critical path delay after sequential circuit packing in the original method is determined by the longest path delay in all pipeline stages.

SUMMARY OF THE INVENTION

Aiming at the technical problem that the existing method does not take into account that the circuit path delay will change greatly after packing, and the entire pipeline stage is constrained by a unified critical path delay, the present invention proposes a multi-pipeline stage timing sequence based on register retiming. The circuit packing operation method makes full use of the difference in the path delay of each pipeline stage. The retiming operation of the register can be used to average the delay of each pipeline stage, thereby effectively reducing the unified critical path delay of the pipeline sequential circuit and further improving the circuit system. throughput rate.

In order to achieve the above-mentioned purpose, the technical scheme of the present invention is realized as follows: a multi-pipeline sequential circuit packing operation method based on register retiming, the steps are as follows:

Step 1: Use the FPGA design process to process the hardware description language designed by the user through the logic synthesis and mapping stages to generate a look-up table circuit;

Step 2: Use the packing algorithm to pack the look-up table circuit;

Step 3: Determine the type of the pipeline-level sequential circuit after packing according to the direction of the critical path of the sequential circuit, and calculate the critical path delay of the pipeline-level sequential circuit after packing by using the method for calculating the critical path delay of the sequential circuit after packing;

Step 4: Retime the intermediate registers in the circuit according to the critical path delay calculated in Step 3.

A combined circuit representing the registers is arranged between the registers in the pipeline level sequential circuit, and the pipeline level sequential circuit includes a standard pipeline type sequential circuit, a branch pipeline type sequential circuit and an output port type sequential circuit in the pipeline stage; the branch pipeline type sequential circuit The circuit has branches at the register level, and there are output ports in the pipeline stage in the output port type circuit in the pipeline stage.

The critical path delay calculation method of the sequential circuit after packing is as follows:

(1) Standard pipeline sequential circuit: Calculate the longest circuit path delay of the pipeline stage between adjacent registers respectively, divide all the added longest circuit path delays by the number of pipeline stages, and obtain the pipeline stage sequence Circuit critical path delay;

(2) Branch pipeline sequential circuit: use the standard pipeline sequential circuit to solve the critical path delay method to calculate the critical path delay of each pipeline stage circuit composed of registers, and then select the larger value as the critical path of the entire pipeline stage sequential circuit delay;

(3) Output port sequential circuit in the pipeline stage: use the standard pipeline sequential circuit to solve the critical path delay method to calculate the critical path delay A of each pipeline without output ports, and use the standard pipeline sequential circuit to solve the critical path delay The method calculates the average delay B of all pipeline stages before the pipeline stage where the intermediate output port is located, and the end of the pipeline stage where the output port is located is set at the output port of the intermediate lookup table; select the critical path delay A and the average delay B of all pipeline stages to be larger The value is the critical path delay of the entire pipeline stage sequential circuit.

The method of using the critical path delay to calculate the direction of register retiming in the step 4 is as follows: according to the critical path delay calculated in step 3, the path delays of each pipeline stage in the entire pipeline circuit are evenly distributed, and are marked in the circuit. Demarcation point of each pipeline stage; judge the retiming direction of the registers between the pipeline stages in the pipeline circuit according to the demarcation point: if the demarcation point is in front of the corresponding register, the corresponding register needs to be retimed to the circuit input until the demarcation point; if the demarcation point is in front of the corresponding register point behind the corresponding register, the corresponding register needs to be retimed to the circuit output until the demarcation point.

For each register that needs to be retimed, first use the logic unit block register retiming method to determine whether it is inter-logic unit block retiming or intra-logic unit block retiming, and select the target logic unit block; The timing method retimes the registers in the corresponding basic logic unit inside the target logic unit block to the front end or back end of the circuit.

The method for register retiming of the described logic unit block: the basic logic unit is finally boxed into the logic unit block of the FPGA. From the perspective of the logic unit block, there are two cases of register retiming:

(1) Retiming between logic unit blocks: the register in the BLE in the logic unit block I is moved to the BLE in the logic unit block II;

(2) Internal retiming of the logic unit block: A register in one of the BLEs in the logic unit block is moved to another BLE in the logic unit block.

In described step 2, the method that packing algorithm carries out FPGA logic unit block packing is:

(a) Lookup table circuit netlist BLE packing, the two-way selector in BLE is configured according to the actual situation of the lookup table circuit;

(b) Select a BLE as a seed to load into the target FPGA logic unit block;

(c) Select BLE to continue loading into the target FPGA logic unit block according to the attraction function value, until the BLE resource inside the logic block unit block is full or the external port reaches the physical upper limit of the FPGA logic unit block;

(d) Select a new seed BLE to continue boxing unboxed LU blocks until all BLEs are boxed.

In step (a) of the packing algorithm: a single LUT performs BLE packing, the register resources in BLE are idle, and the two-way selector is configured to be connected as the output port of the LUT; if one LUT output drives a register for BLE When packing, both the LUT and register resources in BLE are used, and the two-way selector configuration is connected as the output port of the register; if one LUT output drives two paths, that is, the look-up table circuit has two output ports at the same time, because the BLE It can only be set as one port output, so the circuit needs to be installed in two BLEs, one of which is configured with LUT resources, the register resources are idle, and the two-way selector configuration is connected to the output port of the LUT; the other BLE is configured with LUT resources For line direct connection, register resource configuration, two-way selector configuration is connected as the output port of the register.

The circuit BLE register retiming method after packing is as follows: Since the main resource of the pipeline-level sequential circuit is the look-up table circuit, most of the register resources in the BLE are idle, creating conditions for subsequent circuit register retiming after packing; for In the case where two registers of the pipeline stage circuit are directly connected, the registers can be retimed in sequence;

According to the register retiming direction, it can be divided into the following two types:

(1) The BLE register is retimed to the front end of the circuit: the register in the second BLE needs to be retimed to the first BLE. If the internal register resources of the first BLE are idle, the register in the second BLE can be retimed to the inside of the first BLE. At the same time, the two-way selectors in the first BLE are configured to be connected to the output ports of the register, and the two-way selectors in the second BLE are configured to be connected to the output ports of the lookup table; if the internal register resources of the first BLE are occupied, the first BLE Retiming to the front end of the circuit frees up resources for register retiming at the back end of the circuit;

(2) The BLE register is retimed to the back end of the circuit: the registers in the first BLE and the second BLE need to be retimed to the third BLE. If the internal register resources of the third BLE are idle, the first BLE and the second BLE can be neutralized. The register in the third BLE is retimed to the inside of the third BLE, and the two-way selector configuration in the third BLE is connected as the output port of the register, and the two-way selector configuration in the first BLE and the second BLE is connected as the output port of the lookup table; if The third BLE internal register resource is occupied, then the third BLE can be retimed to the back end of the circuit to free up resources for the register retiming of the front end of the circuit.

The beneficial effects of the present invention are that the critical path delay of the entire sequential circuit pipeline can be reduced by utilizing the feature that the registers packed into the logic block can be moved. In the design of a specific pipeline circuit, the critical path delay (CPD) (that is, the longest pipeline stage delay among all pipeline stages included in the pipeline) determines the system throughput rate. The smaller the CPD, the higher the system throughput rate. High, the present invention can distribute the delay of each pipeline stage as evenly as possible through register retiming, thereby improving the throughput rate of pipeline applications. The increase in throughput rate means that the application system processes more data per unit time.

Description of drawings

In order to explain the embodiments of the present invention or the technical solutions in the prior art more clearly, the following briefly introduces the accompanying drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are only These are some embodiments of the present invention. For those of ordinary skill in the art, other drawings can also be obtained according to these drawings without creative efforts.

Figure 1 shows the design flow of the FPGA.

Figure 2 is a flow chart of the present invention.

FIG. 3 is a structural diagram of an FPGA logic unit block, wherein (a) is an FPGA, (b) is a logic unit block, and (c) is a basic logic unit.

Figure 4 is a diagram of an example of look-up table circuit BLE packing, in which (a) is the look-up table BLE packing, (b) is the look-up table output plus register BLE packing, (c) is the look-up table output to drive two paths BLE boxing.

Figure 5 is a standard pipelined look-up table circuit.

Figure 6 is a branch-pipelined look-up table circuit.

Figure 7 is a look-up table circuit with an output port in the pipeline stage.

FIG. 8 is a schematic diagram of the retiming of the lookup table circuit BLE register to the front end of the circuit after packing according to the present invention.

FIG. 9 is a schematic diagram of retiming the lookup table circuit BLE register to the back end of the circuit after packing according to the present invention.

FIG. 10 is a schematic diagram of the retiming of the logic unit block register according to the present invention.

Figure 11 is a flow chart for finding the critical path delay (CPD) and time slack for a single pipeline stage.

FIG. 12 is a schematic diagram showing the direction determination of register retiming between pipeline stages.

Detailed ways

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, but not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

As shown in Figure 2, a multi-pipeline sequential circuit packing operation method based on register retiming, the steps are as follows:

Step 1: Use the FPGA design flow to process the hardware description language designed by the user through the logic synthesis and mapping stages to generate a look-up table circuit.

As shown in Figure 1, the hardware description language designed by the user is processed through the FPGA design process to generate a look-up table circuit, including: generating a gate-level netlist (NAND gate circuit netlist) from the hardware description language designed by the user through the logic synthesis stage , the gate-level netlist is mapped to generate a Look Up Table (LUT) circuit, and it is determined that the LUT circuit meets the requirements of a multi-pipeline sequential circuit.

Step 2: Use the binning algorithm to bin the look-up table circuit.

The structure of the FPGA logic unit block is shown in Figure 3. The FPGA logic unit block consists of a two-layer structure, the first layer of logic unit blocks and the second layer of basic logic units (Basic Logic Element, BLE). The FPGA is composed of logic unit blocks, as shown in Figure 6(a), and the logic unit block is composed of BLEs with several connection resources shared, as shown in Figure 6(b). A single BLE consists of a LUT, a register resource and a two-way selector, as shown in Figure 6(c). Usually, the lookup table and register resources inside BLE are configured according to the specific circuit.

The traditional FPGA logic cell block packing steps are as follows:

(1) Look-up table (LUT) circuit netlist BLE packing

When the lookup table circuit BLE is boxed, the two-way selector in the BLE is configured according to the actual situation of the circuit.

As shown in Figure 4(a), a single LUT is packed for BLE, the register resources in BLE are idle, and the two-way selector configuration is connected to the output port of the LUT. As shown in Figure 4(b), if a LUT output drives a register for BLE packing, both the LUT and register resources in BLE are used, and the two selectors are configured to be connected as the output ports of the register. As shown in Figure 4(c), if one LUT output drives two paths, that is, the look-up table circuit has two output ports at the same time. Since BLE can only be set to output from one port, the circuit needs to be installed in two BLEs. . The LUT resource is configured in BLE1, the register resource is idle, and the two-way selector is configured to be connected to the output port of the LUT; the LUT resource in BLE2 is configured to be directly connected to the line, the register resource is configured, and the two-way selector is configured to be connected to the output port of the register.

(2) Select a BLE to be loaded into the target FPGA logic unit block as a seed;

(3) Select BLE to continue loading into the target FPGA logic unit block according to the attraction function value;

The attraction function is calculated according to the formula proposed in the literature [Li Peng et al., FPGA packing algorithm based on network cable absorption and port occupancy analysis, "Journal of Computer Aided Design and Graphics", Volume 23, Issue 3, September 2011.]. This BLE boxing process continues until the internal BLE resources of the logic block unit block are full or the external port reaches the physical upper limit of the FPGA logic unit block;

(4) Select a new seed BLE to continue packing unpacked LU blocks until all BLEs are packed.

Step 3: Determine the type of the pipeline-level sequential circuit after packing according to the direction of the critical path of the sequential circuit, and calculate the critical path delay of the pipeline-level sequential circuit after packing by using the critical path delay calculation method of the sequential circuit after packing.

Single pipeline stage critical path delay (CPD) and time slack solution process:

Use the method shown in Figure 11 to find the critical path delay (CPD) and time slack for a single pipeline stage. The specific method is:

(a) Calculate the delay of each edge between the registers;

(b) Set the T _arrival value of the pipeline stage input register node to 0;

其中，i为流水线中的任意一个路径的起点，j为该路径的终点，T_arrival(i)为节点i的信号到达时间，T_arrival(j)为节点j的信号到达时间，fanin(j)代表连接节点j前的任意一个节点，delay(i,j)代表路径(i，j)的时延；(c) Calculate the T _arrival value of other nodes:

Among them, i is the starting point of any path in the pipeline, j is the end point of the path, T _arrival (i) is the signal arrival time of node i, T _arrival (j) is the signal arrival time of node j, fanin(j) Represents any node before connecting node j, and delay(i, j) represents the delay of path (i, j);

其中，registerout为任意一个输出端口的寄存器；(d) Set the value of all pipeline output port registers T _required to the critical path delay:

Among them, registerout is the register of any output port;

其中，fanout(i)代表节点i向后所驱动的任意节点，T_required(i)表示节点i的信号最迟到达时间，T_requierd(j)表示节点j的信号最迟到达时间；(e) Calculate the T _required value of other nodes using the following formula:

Among them, fanout(i) represents any node driven backward by node i, T _required (i) represents the latest arrival time of the signal of node i, and T _requierd (j) represents the latest arrival time of the signal of node j;

(f) Use the following formula to calculate the time slack value for any connection in the circuit: slack(i,j)=T _requierd (j)-T _arrival (i)-delay(i,j).

The critical path delay (CPD) solution process of the pipeline circuit:

A combinational circuit representing the registers is arranged between the registers in the pipeline stage circuit. The pipeline stage sequential circuit includes a standard pipeline type sequential circuit, a branch pipeline type sequential circuit and an output port type sequential circuit in the pipeline stage. Flow stages are divided into the following types according to the direction of their paths:

(1) Standard pipeline type

As shown in Figure 5, registers a, b, and c divide the circuit into two pipeline stages that are connected before and after, and the registers a to b and The longest circuit path delay between registers b and c is added and divided by the number of pipeline stages 2, and the critical path delay of the sequential circuit of this pipeline level can be calculated. Subsequently, the two pipeline stages can meet the critical path delay requirements by retiming the operation of register b. The critical path delay calculation method of standard pipeline sequential circuits is the basis for calculating the critical path delay of subsequent types of sequential circuits.

(2) branch pipeline type

The branch pipeline sequential circuit has branches at the register level. As shown in Figure 6, registers a, c, e, f and registers b, d, e, and f form two pipeline stages, their starting points are registers a and b, respectively, and the end points are register f. The critical path delay of the two pipelined circuits composed of registers a, c, e, and f and registers b, d, e, and f can be calculated by using the standard pipeline method shown in Figure 3, and then select The larger value is the critical path delay of the entire pipeline-level sequential circuit shown in Figure 4. Subsequently, all pipeline stages on the two branch routes can meet the critical path delay requirement by retiming the operations on registers c, d, and e.

(3) The output port type in the flow stage

There are output ports in the pipeline stage in the output port type circuit in the pipeline stage. As shown in Figure 7, there is a lookup table output in the pipeline stage between registers b and c to drive two paths, one leads to the pipeline stage terminal register c , and the other is the output port. Because of the limitation of the output port, the following registers cannot continue to retime to the front end of the circuit, so the method for calculating the critical path delay of the sequential circuit is divided into the following steps:

The critical path delay A of the pipeline stage circuit of registers a, b, c, d is obtained by using the standard pipeline method for solving the critical path delay shown in FIG. 5 . Calculate the average delay of all pipeline stages before the pipeline stage where the intermediate output port is located. The end of the pipeline stage where the output port is located is set at the output port of the intermediate lookup table, and the average pipeline level critical path delay B is calculated. The larger value of the critical path delay A and the average pipeline-level critical path delay B is selected as the critical path delay of the entire pipeline-level sequential circuit shown in FIG. 7 . Subsequently, all pipeline stages of the entire sequential circuit can meet the critical path delay requirements by retiming the operation of registers b and c.

Step 4: Retime the intermediate registers in the circuit according to the critical path delay calculated in Step 3.

Steps to calculate register retiming direction using critical path delay:

According to the critical path delay calculated in step 3, the path delay of each pipeline stage in the entire pipeline circuit is evenly distributed, and the demarcation points of each pipeline stage are marked in the circuit; as shown in Figure 12, according to the critical path delay, the given The demarcation points of the pipeline stages in the pipeline circuit should be A and B.

The retiming direction of the registers between the pipeline stages in the pipeline circuit is judged against the demarcation point: if the demarcation point is in front of the corresponding register, the corresponding register needs to be retimed to the circuit input until the demarcation point. As shown in Figure 12, the demarcation point A is in front of the corresponding register b, and the register b needs to be retimed to the circuit input until the demarcation point A is reached. If the demarcation point is behind the corresponding register, the corresponding register needs to be retimed to the circuit output until the demarcation point. As shown in Figure 12, the demarcation point B is behind the corresponding register c, and the register b needs to be re-timed to the circuit output until the demarcation point B.

For each register that needs to be retimed, first use the logic unit block register retiming method to determine whether it is inter-logic unit block retiming or intra-logic unit block retiming, and select the target logic unit block; The timing method retimes the registers in the corresponding basic logic unit inside the target logic unit block to the front end or back end of the circuit.

Circuit BLE register retiming after packing: Since the main resource of the pipeline-level sequential circuit is LUT, most of the register resources in BLE are idle, which creates conditions for subsequent circuit register retiming after packing. In the actual circuit, it is rare that the two registers of the pipeline circuit are directly connected. If it occurs, the registers can be retimed in sequence, which can also ensure the retiming operation of the circuit registers after packing.

The circuit BLE register retiming after boxing can be divided into the following two types according to the register retiming direction:

(1) The BLE register retimes to the front end of the circuit:

As shown in Figure 8, the registers in BLE2 need to be retimed to BLE1. If the internal register resources of BLE1 are idle, the registers in BLE2 can be retimed to the interior of BLE1. At the same time, the two selectors in BLE1 are configured to be connected to the output ports of the registers. The two-way selector in BLE2 is configured to be connected as the output port of the lookup table. If the BLE1 internal register resource is occupied, it can be retimed to the front end of the circuit to free up resources for the register retiming of the back end of the circuit.

(2) The BLE register retimes to the back end of the circuit

As shown in Figure 9, the registers in BLE1 and BLE2 need to be retimed to BLE3. If the internal register resources of BLE3 are idle, the registers in BLE1 and BLE2 can be retimed to the interior of BLE3, and the two selectors in BLE3 are configured to connect For the output port of the register, the two-way selector configuration in BLE1 and BLE2 is connected as the output port of the lookup table. If the BLE3 internal register resource is occupied, it can be retimed to the back end of the circuit to free up resources for the register retiming of the front end of the circuit.

Logical unit block register retiming:

Since the basic logic unit BLE is eventually boxed into the logic unit block of the FPGA, there are two cases of register retiming from the logic unit block perspective.

(1) Retiming between logic unit blocks: As shown in Figure 10, moving the register in BLE C in logic unit block A to BLE D in logic unit block B belongs to register retiming between logic unit blocks. Internally generated changes to BLE by retiming are described by the retiming of the BLE register after the boxing circuit.

(2) Internal retiming of the logic unit block: As shown in Figure 10, the movement of the register in the BLE A in the logic unit block B to the BLE B in the logic unit block B belongs to the internal retiming of the logic unit block. Internally generated changes to BLE by retiming are described by the retiming of the BLE register after the boxing circuit.

The above descriptions are only preferred embodiments of the present invention, and are not intended to limit the present invention. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the scope of the present invention. within the scope of protection.

Claims (7)

1. a multi-pipeline sequential circuit packing operation method based on register retiming, is characterized in that, its steps are as follows: Step 1: Use the FPGA design process to process the hardware description language designed by the user through the logic synthesis and mapping stages to generate a look-up table circuit; Step 2: Use the packing algorithm to pack the look-up table circuit; Step 3: Determine the type of the pipeline-level sequential circuit after packing according to the direction of the critical path of the sequential circuit, and calculate the critical path delay of the pipeline-level sequential circuit after packing by using the method for calculating the critical path delay of the sequential circuit after packing; The critical path delay calculation method of the sequential circuit after packing is as follows: (1) Standard pipeline sequential circuit: Calculate the longest circuit path delay of the pipeline stage between adjacent registers respectively, divide all the added longest circuit path delays by the number of pipeline stages, and obtain the pipeline stage sequence Circuit critical path delay; (2) Branch pipeline sequential circuit: use the standard pipeline sequential circuit to solve the critical path delay method to calculate the critical path delay of each pipeline stage circuit composed of registers, and then select the larger value as the critical path of the entire pipeline stage sequential circuit delay; (3) Output port sequential circuit in the pipeline stage: use the standard pipeline sequential circuit to solve the critical path delay method to calculate the critical path delay A of each pipeline without an output port, and use the standard pipeline sequential circuit to solve the critical path delay The method calculates the average delay B of all pipeline stages before the pipeline stage where the intermediate output port is located, and the end of the pipeline stage where the output port is located is set at the output port of the intermediate lookup table; select the critical path delay A and the average delay B of all pipeline stages to be larger The value is the critical path delay of the entire pipeline-level sequential circuit; Step 4: Retime the intermediate registers in the circuit according to the critical path delay calculated in Step 3; The circuit BLE register retiming method after packing is as follows: Since the main resource of the pipeline-level sequential circuit is the look-up table circuit, most of the register resources in the BLE are idle, creating conditions for subsequent circuit register retiming after packing; for In the case where two registers of the pipeline stage circuit are directly connected, the registers can be retimed in sequence; According to the register retiming direction, it can be divided into the following two types: (1) The BLE register is retimed to the front end of the circuit: the register in the second BLE needs to be retimed to the first BLE. If the internal register resources of the first BLE are idle, the register in the second BLE can be retimed to the inside of the first BLE. At the same time, the two-way selectors in the first BLE are configured to be connected to the output ports of the register, and the two-way selectors in the second BLE are configured to be connected to the output ports of the lookup table; if the internal register resources of the first BLE are occupied, the first BLE Retiming to the front end of the circuit frees up resources for register retiming at the back end of the circuit; (2) The BLE register is retimed to the back end of the circuit: the registers in the first BLE and the second BLE need to be retimed to the third BLE. If the internal register resources of the third BLE are idle, the first BLE and the second BLE can be neutralized. The register in the third BLE is retimed to the inside of the third BLE, and the two-way selector configuration in the third BLE is connected as the output port of the register, and the two-way selector configuration in the first BLE and the second BLE is connected as the output port of the lookup table; if The third BLE internal register resource is occupied, then the third BLE can be retimed to the back end of the circuit to free up resources for the register retiming of the front end of the circuit. 2. the multi-pipeline sequential circuit packing operation method based on register retiming according to claim 1, is characterized in that, between the registers in the described pipeline level sequential circuit, be provided with the combination circuit representing between the registers, pipeline level Sequential circuits include standard pipeline type sequential circuits, branch pipeline type sequential circuits and output port type sequential circuits in the pipeline stage; branch pipeline type sequential circuits have branches at the register level, and output port type circuits in the pipeline stage have outputs in the pipeline stage. port. 3. the multi-pipeline sequential circuit packing operation method based on register retiming according to claim 1 and 2, is characterized in that, utilizes critical path time delay in described step 4 to carry out the method for calculating the direction of register retiming as : According to the critical path delay calculated in step 3, the path delay of each pipeline stage in the entire pipeline circuit is evenly distributed, and the demarcation point of each pipeline stage is marked in the circuit; Timing direction judgment: if the demarcation point is in front of the corresponding register, the corresponding register needs to be retimed to the circuit input until the demarcation point; if the demarcation point is behind the corresponding register, the corresponding register needs to be retimed to the circuit output until the demarcation point. until. 4. the multi-pipeline sequential circuit packing operation method based on register retiming according to claim 3, is characterized in that, for each register that needs retiming, at first use logic unit block register retiming method to judge that it is logic unit Retiming between blocks or retiming within a logic unit block, select the target logic unit block; then use the post-packing circuit BLE register retiming method to retime the registers in the corresponding basic logic unit inside the target logic unit block to the front-end or back-end of the circuit. timing. 5. the multi-pipeline sequential circuit packing operation method based on register retiming according to claim 4, is characterized in that, the method for described logic unit block register retiming: basic logic unit is finally packed into the logic unit of FPGA There are two cases of register retiming in the block from the perspective of the logic unit block: (1) Retiming between logic unit blocks: the registers in the BLE in the logic unit block I are moved to the BLE in the logic unit block II; (2) Internal retiming of the logic unit block: A register in one of the BLEs in the logic unit block is moved to another BLE in the logic unit block. 6. the multi-pipeline sequential circuit packing operation method based on register retiming according to claim 1 or 5, is characterized in that, the method that packing algorithm carries out FPGA logic unit block packing in described step 2 is: (a) Lookup table circuit netlist BLE packing, the two-way selector in BLE is configured according to the actual situation of the lookup table circuit; (b) Select a BLE as a seed to load into the target FPGA logic unit block; (c) Select BLE according to the attraction function value and continue to load it into the target FPGA logic unit block until the internal BLE resources of the logic block unit block are full or the external port reaches the physical upper limit of the FPGA logic unit block; (d) Select a new seed BLE to continue boxing unboxed LU blocks until all BLEs are boxed. 7. The multi-pipeline sequential circuit packing operation method based on register retiming according to claim 6, wherein in step (a) of the packing algorithm: a separate LUT performs BLE packing, and the BLE The register resources of the BLE are idle, and the two-way selectors are configured to be connected as the output ports of the LUT; if one LUT output drives a register for BLE packing, both the LUT and register resources in the BLE are used, and the two-way selectors are configured and connected as The output port of the register; if one LUT output drives two paths, that is, the look-up table circuit has two output ports at the same time. Since BLE can only be set to one port output, the circuit needs to be installed in two BLEs, one of which is BLE. The LUT resource is configured in the middle, the register resource is idle, and the two-way selector is configured to be connected as the output port of the LUT; the other LUT resource in the BLE is configured as a line direct connection, the register resource is configured, and the two-way selector is configured to be connected as the output port of the register.

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