CN109787925B - Detection circuit, clock data recovery circuit and signal detection method - Google Patents
Detection circuit, clock data recovery circuit and signal detection method Download PDFInfo
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Abstract
A detection circuit, a clock data recovery circuit, and a signal detection method are disclosed. The phase detector includes: a main circuit for providing a plurality of intermediate signals and adjustment indication signals according to a data input signal and a reference clock signal, a first detection unit for generating a first logic signal according to the data input signal, the reference clock signal, the corresponding intermediate signals and a first clock signal preceding the reference clock signal; a second detection unit for generating a second logic signal according to the data input signal, the reference clock signal, the corresponding intermediate signal and a second clock signal lagging the reference clock signal; and a judging unit for generating an indication signal according to the logic relationship among the first logic signal, the second logic signal and the data input signal, wherein the indication signal characterizes the jitter compensation type required by the data input signal. The indication signal of the detection circuit characterizes the type of jitter compensation required for the data input signal, so that corresponding measures are taken to reduce the bit error rate.
Description
Technical Field
The present invention relates to the field of digital communication technology, and more particularly, to a detection circuit, a clock data recovery circuit, and a signal detection method.
Background
Clock data recovery circuit (Clock and Data Recovery, CDR) is the core module of a high-speed transceiver, which is an important component in a communication system. When the data stream is transmitted in the serial data line, no clock signal is attached, the serial data receiving end needs to extract a synchronous clock from the received data input signal through the clock data recovery circuit, and resample the data input signal by utilizing the synchronous clock to obtain stable and reliable data. However, the signal quality of the data input signal of the high-speed interconnection circuit is often severely lost after the data input signal is transmitted over a long distance, and in addition, the signal quality is further deteriorated by the environmental noise, so that the bit error rate (symbol error rate, SER) of the data input signal does not meet the requirement, and the difficulty of recovering the data at the receiving end is increased.
Long-range transmission signal loss is typically manifested as intersymbol interference (Inter Symbol Interference, ISI). Fig. 1 shows a waveform diagram of a prior art clock data recovery circuit. As shown in fig. 1, when the transmission channel bandwidth is insufficient to transmit the data input signal, it means that the time length of a single signal period cannot be enough for the data input signal to be well established. As shown at t1 and t2, the output signal cannot build up to the highest voltage in one cycle and cannot recover to the lowest voltage in one cycle, so that the rising and falling edges of the signal deviate from the ideal signal after recovery. When the transmission channel bandwidth is further reduced, the signal cannot be established in the time of two periods, more complex intersymbol interference phenomenon is generated and larger time deviation is brought, so that the quality of the signal is further deteriorated, and even the signal cannot exceed V 0/2 in one period, so that the signal cannot be recovered normally. In order to solve the problem of intersymbol interference, the prior art performs pre-emphasis on the output and adds an Equalizer (EQ) on the input and the receiving, the principle of which is to increase the high frequency gain to compensate for the high frequency loss of the channel. However, the high frequency gain is excessively increased, so that overcompensation of the high frequency portion of the signal also causes deterioration of signal jitter and also causes waste of power consumption.
Another factor affecting the performance of the data input signal is noise, which is introduced during the generation, transmission and reception of the data input signal, resulting in a degradation of the data input signal. When the input signal is noisy, the clock data recovery circuit bandwidth needs to be increased to track the jitter of the input signal to correctly recover the signal. However, the increase of the bandwidth of the clock data recovery circuit also causes the jitter of the clock data recovery circuit itself to become large, thereby affecting the bit error rate.
Both intersymbol interference and noise affect the signal quality, resulting in high bit error rates, but the solutions for both are not the same. The channel environment of the high-speed interconnection device is not unchanged, such as a network interface, a video interface and the like, the connection materials and the connection lengths used by different users are very different, the working environments are also different, and all the user demands cannot be solved by using the completely same configuration.
Disclosure of Invention
In view of the foregoing, it is an object of the present invention to provide a detection circuit, a clock data recovery circuit, and a signal detection method, in which a cause of jitter of a data input signal is determined based on the data input signal, a second logic signal, and a first logic signal, so that an equalizer and a bandwidth are adjusted to reduce an error rate, respectively, based on the result of the determination.
According to a first aspect of the present invention, there is provided a detection circuit comprising: a main circuit for providing a plurality of intermediate signals and adjustment indication signals according to a data input signal and a reference clock signal, a first detection unit for generating a first logic signal according to the data input signal, the reference clock signal, the corresponding intermediate signals and a first clock signal preceding the reference clock signal; a second detection unit for generating a second logic signal according to the data input signal, the reference clock signal, the corresponding intermediate signal and a second clock signal lagging the reference clock signal; and a judging unit for generating an indication signal according to a logic relationship among the first logic signal, the second logic signal and the data input signal, wherein the indication signal characterizes a jitter compensation type required by the data input signal.
Preferably, the indication signals include a first indication signal, a second indication signal and a third indication signal, the first indication signal is valid if the first logic signal is high level and the second logic signal is high level when the data input signal level state is changed, the second indication signal is valid if the second logic signal is high level and the first logic signal is high level when the data input signal level state is changed, and the third indication signal is valid if the first logic signal and/or the second logic signal is high level and the level state of the first logic signal and/or the second logic signal is kept unchanged when the data input signal level state is changed.
Preferably, the period of the reference clock signal is T, the phase difference between the first clock signal and the reference clock signal is greater than 0 and not greater than T/4, and the phase difference between the second clock signal and the reference clock signal is greater than 0 and not greater than T/4.
Preferably, the main circuit includes a first flip-flop, a second flip-flop, a third flip-flop, a fourth flip-flop, a first exclusive-or gate and a second exclusive-or gate, the intermediate signals include a first intermediate signal, a second intermediate signal, a third intermediate signal and a fourth intermediate signal, the adjustment indication signal includes a first adjustment indication signal and a second adjustment indication signal, the first flip-flop generates the first intermediate signal according to the data input signal and the reference clock signal, the second flip-flop generates the second intermediate signal according to the first intermediate signal and the reference clock signal, the third flip-flop generates the third intermediate signal according to a complementary signal of the data input signal and the reference clock signal, the fourth flip-flop generates the fourth intermediate signal according to the third intermediate signal and the reference clock signal, the first exclusive-or gate generates the first adjustment indication signal according to the second intermediate signal and the fourth intermediate signal, and the second exclusive-or gate generates the second adjustment indication signal according to the first intermediate signal and the fourth intermediate signal.
Preferably, the first detection unit includes a fifth flip-flop, a sixth flip-flop, and a third exclusive-or gate, the second detection unit includes a seventh flip-flop, an eighth flip-flop, and a fourth exclusive-or gate, the fifth flip-flop generates a first sampling signal according to the data input signal and a complementary signal of the first clock signal, the sixth flip-flop generates the first logic signal according to the first sampling signal and the reference clock signal, the seventh flip-flop generates a second sampling signal according to the data input signal and a complementary signal of the second clock signal, and the eighth flip-flop generates the second logic signal according to the second sampling signal and the reference clock signal.
Preferably, the first detecting unit, the second detecting unit and the judging unit are turned on when detecting, and the first detecting unit, the second detecting unit and the judging unit are turned off when stopping detecting.
According to a second aspect of the present invention, there is provided a clock data recovery circuit comprising: a detection circuit as described above, the main circuit of the detection circuit generating a recovered data signal; and the clock generation unit is used for providing clock signals, the clock signals comprise the reference clock signal, the first clock signal and the second clock signal, and the bandwidth of the clock signals is controlled by the indication signal.
Preferably, the method further comprises: and the equalizer is used for receiving an original signal and providing a compensation signal for the original signal so as to generate the data input signal, and the gain of the compensation signal is controlled by the indication signal.
Preferably, the indication signals include a first indication signal, a second indication signal and a third indication signal, the first indication signal being valid if the first logic signal is high and the second logic signal is high when the data input signal level state is changed, the second indication signal being valid if the second logic signal is high and the first logic signal is high when the data input signal level state is changed, the third indication signal being valid if the first logic signal and/or the second logic signal is high and the level state of the first logic signal and/or the second logic signal being kept unchanged when the data input signal level state is changed, wherein the gain of the compensation signal is decreased when the first indication signal is valid and the gain of the compensation signal is increased when the second indication signal is valid and the bandwidth of the clock signal is increased when the third indication signal is valid.
Preferably, the clock generating unit supplies the first clock signal and the second clock signal for signal detection before starting to receive the original signal, and stops supplying the first clock signal and the second clock signal for signal detection after receiving the original signal.
Preferably, the clock generation unit includes: a clock generator for generating the first clock signal; a first delay unit for generating the reference clock signal according to the first clock signal; and a second delay unit for generating the second clock signal according to the reference clock signal, wherein the period of the reference clock signal is T, the phase difference between the first clock signal and the reference clock signal is greater than 0 and not greater than T/4, and the phase difference between the second clock signal and the reference clock signal is greater than 0 and not greater than T/4.
Preferably, the method further comprises: and the filter is connected to the detection circuit and used for generating a voltage signal according to the adjustment indication signal, wherein the output end of the filter is connected to the clock generation unit, and the clock generation unit also generates a recovered clock signal according to the voltage signal and provides the recovered clock signal to the detection circuit.
According to a third aspect of the present invention, there is provided a signal detection method comprising: providing a plurality of intermediate signals and adjustment indication signals based on a data input signal and a reference clock signal, generating a first logic signal based on the data input signal, the reference clock signal, the corresponding intermediate signals, and a first clock signal that leads the reference clock signal; generating a second logic signal based on the data input signal, the reference clock signal, the corresponding intermediate signal, and a second clock signal that lags the reference clock signal; and generating an indication signal according to a logical relationship between the first logic signal, the second logic signal and the data input signal, the indication signal characterizing a type of jitter compensation required for the data input signal.
Preferably, the indication signals include a first indication signal, a second indication signal and a third indication signal, the first indication signal is valid if the first logic signal is high level and the second logic signal is high level when the data input signal level state is changed, the second indication signal is valid if the second logic signal is high level and the first logic signal is high level when the data input signal level state is changed, and the third indication signal is valid if the first logic signal and/or the second logic signal is high level and the level state of the first logic signal and/or the second logic signal is kept unchanged when the data input signal level state is changed.
Preferably, when the third indication signal is active, bandwidths of the reference clock signal, the first clock signal and the second clock signal are increased.
Preferably, the method further comprises: receiving an original signal and providing a compensation signal to the original signal to generate the data input signal, wherein the gain of the compensation signal is controlled by the first indication signal, wherein the gain of the compensation signal decreases when the first indication signal is active, and the gain of the compensation signal increases when the second indication signal is active.
Preferably, the method for generating the reference clock signal, the first clock signal and the second clock signal further comprises the steps of: generating the first clock signal; generating the reference clock signal from the first clock signal; and generating the second clock signal according to the reference clock signal, wherein the period of the reference clock signal is T, the phase difference between the first clock signal and the reference clock signal is more than 0 and not more than T/4, and the phase difference between the second clock signal and the reference clock signal is more than 0 and not more than T/4.
Preferably, the intermediate signal includes a first intermediate signal, a second intermediate signal, a third intermediate signal and a fourth intermediate signal, the adjustment indicating signal includes a first adjustment indicating signal and a second adjustment indicating signal, and the method for generating the adjustment indicating signal includes: the first intermediate signal is generated according to the data input signal and the reference clock signal, the second intermediate signal is generated according to the first intermediate signal and the reference clock signal, the third intermediate signal is generated according to the complementary signal of the data input signal and the reference clock signal, the fourth intermediate signal is generated according to the third intermediate signal and the reference clock signal, the first adjustment indication signal is generated according to the second intermediate signal and the fourth intermediate signal, and the second adjustment indication signal is generated according to the first intermediate signal and the fourth intermediate signal.
Preferably, the method for generating the first logic signal and the second logic signal comprises: generating a first sampling signal according to the complementary signals of the data input signal and the first clock signal, generating the first logic signal according to the first sampling signal and the reference clock signal, generating a second sampling signal according to the complementary signals of the data input signal and the second clock signal, and generating the second logic signal according to the second sampling signal and the reference clock signal.
Preferably, the first clock signal and the second clock signal are received and the indication signal is generated when signal detection is performed, and the first clock signal and the second clock signal are stopped and the generation of the indication signal is stopped when signal detection is stopped.
The detection circuit, the clock data recovery circuit and the signal detection method provided by the invention distinguish jitter caused by intersymbol interference and noise in the data input signal according to the phase relation among the data input signal, the first logic signal and the second logic signal, and respectively adjust the equalizer and the bandwidth according to the judging result, thereby minimizing the error rate. Furthermore, the detection circuit, the clock data recovery circuit and the signal detection method do not need to work continuously, and can be started only once when a channel is established or at intervals, so that extra power consumption is not brought to the original receiving end circuit.
Drawings
The above and other objects, features and advantages of the present invention will become more apparent from the following description of embodiments of the present invention with reference to the accompanying drawings, in which:
FIG. 1 shows a waveform diagram of a clock data recovery circuit according to the prior art;
Fig. 2 shows a schematic circuit configuration of a phase detector according to the prior art;
Fig. 3 shows a timing diagram of a phase detector according to the prior art;
FIG. 4 shows a block diagram of a clock data recovery circuit according to an embodiment of the invention;
FIG. 5 shows a schematic diagram of a clock generation unit according to an embodiment of the invention;
fig. 6 shows a timing diagram of a clock generation unit according to an embodiment of the invention;
fig. 7 is a schematic circuit diagram of a phase detector according to an embodiment of the present invention.
List of reference numerals
100. Clock data recovery circuit
110. Equalizer
120. Clock generating unit
121. First delay unit
122. Second delay unit
123. Clock generator
130. Phase discriminator
131. Main circuit
132. First detection unit
133. Second detection unit
140. Judgment unit
150. Filter device
200. Detection circuit
Detailed Description
Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. The same reference numbers will be used throughout the drawings to refer to the same or like parts. For clarity, the various features of the drawings are not drawn to scale.
The following describes in further detail the embodiments of the present invention with reference to the drawings and examples.
Fig. 2 shows a schematic circuit configuration of a phase detector according to the prior art; fig. 3 shows a timing diagram of a phase detector according to the prior art.
A Phase-locked loop (PLL) is a core component of a clock data recovery circuit, and a Phase detector is a key component in the Phase-locked loop circuit. As shown in fig. 2, taking a bang-bang phase detector type clock data recovery circuit as an example, the prior art phase detector includes a first stage flip-flop and a second stage flip-flop and a logic circuit. The first stage flip-flop includes flip-flop Q1 and flip-flop Q2 for sampling a data input signal to obtain a data sampling sequence. The second stage flip-flop includes flip-flop Q3 and flip-flop Q4 for retiming the data sample sequence and outputting the recovered data signal. The logic circuit includes an exclusive or gate U1 and an exclusive or gate U2 for comparing a phase difference between the data sampling sequence and the recovered data signal to output phase difference signals UP and DN.
As shown in fig. 3, when the clock data recovery circuit is locked, the falling edge of the clock signal CKS is aligned with the inverted edge of the inputted data input signal DIN, thereby ensuring a maximum margin when the rising edge of the clock signal CKS takes data. Since the falling edge of the clock signal CKS is aligned with the inverting edge of the data input signal DIN, it is possible that the falling edge of the clock signal CKS samples the data input signal DIN before and after the inversion of the data input signal DIN, and the probability of occurrence of both is substantially uniform when non-ideal effects are not considered.
The clock data recovery circuit causes the clock signal CKS to track the jitter of the data input signal DIN, but if the jitter of the data input signal DIN is caused by ISI, the clock signal CKS cannot be judged by the conventional design, which causes the change direction of the clock signal CKS to be opposite to the direction of the intersymbol interference, so that the error rate is increased, and if the jitter of the data input signal DIN is caused by noise, the clock signal CKS is required to track the change of the data input signal DIN rapidly. The requirements of the bandwidth of the response of the intersymbol interference and noise to the clock data recovery circuit are therefore not uniform, i.e. if the jitter is caused by the intersymbol interference, the clock data recovery circuit is as far as possible not to track, whereas if the jitter is caused by the noise, the clock data recovery circuit should track as much as possible.
In order to solve the need of the opposite intersymbol interference and noise, the application detects and records the jitter characteristic of the signal, then counts and analyzes whether the jitter cause is intersymbol interference or noise in the digital circuit, if the jitter cause is intersymbol interference, adjusts the equalizer characteristic of the front-end amplifying circuit or can adjust the pre-emphasis characteristic of the transmitting stage if the transmission protocol has the function of reverse transmission instruction, and if the jitter cause is noise, adjusts the bandwidth of the clock data recovery circuit so that the clock data recovery circuit can better track the input signal.
Fig. 4 shows a block diagram of a clock data recovery circuit according to an embodiment of the invention.
As shown in fig. 4, the clock data recovery circuit 100 according to the embodiment of the present invention includes an equalizer 110, a clock generation unit 120, a phase detector 130, a judgment unit 140, and a filter 150. The detection circuit 200 includes a phase detector 130 and a determination unit 140.
The equalizer 110 is connected to a first input terminal of the phase detector 120, and is configured to receive an original data input signal inputted thereto by an external circuit, compensate the original data input signal, generate a data input signal, and transmit the data input signal to the phase detector 120.
An output of the clock generation unit 120 is connected to a phase detector 130 for providing a clock signal. The first, second and third outputs of the clock generation unit 120 generate a reference clock signal CKS, a LEAD clock signal csk_lead (i.e., a first clock signal) and a LAG clock signal cks_lag (i.e., a second clock signal), respectively.
A first input terminal of the phase detector 130 is connected to the equalizer 110 for receiving a data input signal, and a second input terminal, a third input terminal and a fourth input terminal of the phase detector 130 are respectively connected to a first output terminal, a second output terminal and a third output terminal of the clock generating unit 130 for respectively receiving the reference clock signal CKS, the LEAD clock signal csk_lead and the LAG clock signal cks_lag. The phase detector 130 is configured to generate a data sampling sequence and a recovered data signal Q2, and compare a phase difference between the data sampling sequence and the recovered data signal Q2 to output a phase difference signal UPL (i.e., a first logic signal), a phase difference signal DNL (i.e., a second logic signal), a phase difference signal UP (i.e., a first adjustment control signal), and a phase difference signal DN (i.e., a second adjustment control signal).
The judging unit 140 is configured to receive the recovered data signal Q2 and the phase difference signals UPL, UP, DN and DNL, convert the recovered data signal Q2 and the phase difference signals UPL, UP, DN and DNL into parallel data, reduce the frequency, judge the relationship between the data input signal and the phase difference signals UPL and DNL by using the digital signal, thereby judging the reason for jitter of the data input signal, and generate at least two indication signals according to the judging result to respectively adjust the high frequency gain of the equalizer 110 and the bandwidth of the clock generating unit 120. For example, the judging unit 140 generates a first indication signal and a second indication signal for adjusting the high frequency gain of the equalizer 110, and the judging unit 140 generates a third indication signal for adjusting the bandwidth of the clock generating unit 120. The judging unit 140 includes, for example, a microcontroller (microcomputer, MCU).
Preferably, after the high-frequency gain of the equalizer 110 and the bandwidth of the clock generating unit 120 are adjusted, the two sampling paths of the leading clock signal csk_lead and the lagging clock signal cks_lag and the judging unit 140 are turned off to reduce the power consumption.
Preferably, the judging unit 140 and the two sampling paths of the leading clock signal csk_lead and the lagging clock signal cks_lag are turned on only when the transmission channel of the transceiver is established or at intervals, so as to reduce power consumption without affecting the performance of the clock data recovery circuit.
In this embodiment, if the number of times that the phase difference signals DNL and UPL appear 1 is small, the determination result of the determination unit 140 is that the error rate is small, and the equalizer 120 clock generation unit 120 is not adjusted. If the number of times of 1 occurrence of the phase difference signals DNL and UPL is large, the determination result of the determining unit 140 is that the error rate is large, and further analysis of the cause of jitter of the data input signal is required.
When a plurality of continuous unchanged data input signals change, if the phase difference signal UPL is always 1 and the phase difference signal DNL is always 1 when the data input signals continuously flip, the judgment result of the judgment unit 140 is that the intersymbol interference is serious, and the judgment unit 140 generates a first indication signal to transmit to the equalizer 120, so as to adjust the equalizer 120 and reduce the high-frequency gain.
When a plurality of continuous unchanged data input signals change, if the phase difference signal DNL is always 1 and the phase difference signal UPL is always 1 when the data input signals continuously flip, the judgment result of the judgment unit 140 is that the intersymbol interference is serious, and the judgment unit 140 generates a second indication signal to transmit to the equalizer 120, so as to adjust the equalizer 120 and increase the high-frequency gain.
If the phase difference signal DNL or UPL is continuously 1 and is independent of the sequence pattern of the data input signal, the input jitter is considered to be large, the bandwidth of the clock generating unit 120 is insufficient for normal tracking, and the judging unit 140 generates a second indication signal to transmit to the clock generating unit 120 to increase the bandwidth of the clock generating unit 120.
The detection circuit 200 includes a phase detector 130 and a judging unit 140 for detecting a data input signal and generating at least a detection signal including at least one of the above-mentioned judging results. Preferably, the detection circuit 200 further outputs at least two indication signals generated according to the detection signals for controlling the equalizer 110 and the clock generation unit 120, respectively, according to the determination result.
The filter 150 is connected to an output terminal of the phase detector 140, and the clock generating unit 120 is connected to an output terminal of the filter 150, and the filter 150 and the clock generating unit 120 are configured to receive phase difference signals UP and DN generated by the phase detector 150 and output a recovered clock signal.
FIG. 5 shows a schematic diagram of a clock generation unit according to an embodiment of the invention; fig. 6 shows a timing diagram of a clock generation unit according to an embodiment of the invention.
As shown in fig. 5, the clock generating unit 120 of the embodiment of the present invention includes, for example, a first delay unit 151, a second delay unit 122, and a clock generator 123 for providing a clock signal. The first, second and third outputs of the clock generation unit 120 generate the reference clock signal CKS, the LEAD clock signal csk_lead and the LAG clock signal cks_lag, respectively.
The clock generator 123 generates a leading clock signal csk_lead and transmits the leading clock signal csk_lead to the first delay unit 121; the first delay unit 121 generates the reference clock signal CKS according to the LEAD clock signal csk_lead, and transmits the reference clock signal CKS to the second delay unit 122, and the second delay unit 122 generates the LAG clock signal cks_lag. The clock generator 123 includes, for example, at least one of a voltage controlled oscillator, a phase interpolator, or a quartz crystal resonator.
As shown in fig. 6, the period of the reference clock signal CKS is T based on the phase of the reference clock signal CKS. The leading clock signal CSK_LEAD is leading to the reference clock signal CKS, and the phase difference between the leading clock signal CSK_LEAD and the reference clock signal CKS is more than 0 and less than or equal to T/4; the LAG clock signal cks_lag LAGs the reference clock signal CKS, and the phase difference between the LAG clock signal cks_lag and the reference clock signal CKS is greater than 0 and less than or equal to T/4. Preferably, the phase difference between the leading clock signal CSK_LEAD and the reference clock signal CKS is equal to T/8; the phase difference between the LAG clock signal cks_lag and the reference clock signal CKS is equal to T/8.
Fig. 7 is a schematic circuit diagram of a phase detector according to an embodiment of the present invention.
As shown in fig. 7, the phase detector 130 according to the embodiment of the present invention includes a main circuit 131, a first detecting unit 132, and a second detecting unit 133.
The main circuit 131 includes a flip-flop Q1, a flip-flop Q2, a flip-flop Q3, a flip-flop Q4, an exclusive-or gate U1, and an exclusive-or gate U2. The flip-flop Q1 generates a first intermediate signal according to the data input signal DIN and the reference clock signal CKS, the flip-flop Q1 generates a second intermediate signal according to the first intermediate signal and the reference clock signal CKS, the flip-flop Q3 generates a third intermediate signal according to the complementary signal of the data signal DIN and the reference clock signal CKS, the flip-flop Q4 generates a fourth intermediate signal according to the third intermediate signal and the reference clock signal CKS, the exclusive-or gate U1 generates a first adjustment indication signal according to the second intermediate signal and the fourth intermediate signal, and the exclusive-or gate U2 generates a second adjustment indication signal according to the first intermediate signal and the fourth intermediate signal. The main circuit 131 outputs the second intermediate signal as the recovered data signal DIN to the next-stage receiving circuit.
The first detection unit 132 includes a flip-flop Q5, a flip-flop Q6, and an exclusive or gate U3. The flip-flop Q5 generates a first sampling signal from the complement of the data signal DIN and the LEAD clock signal csk_lead, the sixth flip-flop generates a first logic signal from the first sampling signal and the reference clock signal CKS,
The second detection unit 133 includes a flip-flop Q7, a flip-flop Q8, and an exclusive or gate U4. The flip-flop Q7 generates a second sampling signal according to the complementary signal of the data signal DIN and the LAG clock signal cks_lag, and the flip-flop Q8 generates a second logic signal according to the second sampling signal and the reference clock signal CKS. The flip-flops Q1 to Q8 are, for example, D flip-flops.
Compared with the prior art, a first detection unit comprising a trigger Q5, a trigger Q6 and an exclusive OR gate U3 and a second detection unit comprising a trigger Q7, a trigger Q8 and an exclusive OR gate U4 are added, and a data input signal DIN, a leading clock signal CSK_LEAD and a lagging clock signal CKS_LAG are utilized to generate two signals DNL and UPL. Because the LEAD clock signal cks_lead precedes the reference clock signal CKS, if the UPL signal is1, the reference clock signal CKS is considered to lag the data input signal DIN by too much; because the LAG clock signal cks_lag is later than the reference clock signal CKS, if the DNL signal is1, the reference clock signal CKS may be considered to lead the data input signal DIN too much; if the UPL signal and DNL signal are often 1, it is difficult to indicate that the reference clock signal CDR tracks the data input signal DIN, and the clock has large jitter relative to the data.
Embodiments in accordance with the present invention, as described above, are not intended to be exhaustive or to limit the invention to the precise embodiments disclosed. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best utilize the invention and various modifications as are suited to the particular use contemplated. The invention is limited only by the claims and the full scope and equivalents thereof.
Claims (13)
1. A detection circuit, comprising:
a main circuit for providing a plurality of intermediate signals and adjustment indication signals based on the data input signal and the reference clock signal,
A first detection unit for generating a first logic signal according to the data input signal, the reference clock signal, the corresponding intermediate signal and a first clock signal preceding the reference clock signal;
A second detection unit for generating a second logic signal according to the data input signal, the reference clock signal, the corresponding intermediate signal and a second clock signal lagging the reference clock signal; and
A judging unit for generating an indication signal according to a logical relation among the first logic signal, the second logic signal and the data input signal, the indication signal representing a jitter compensation type required for the data input signal, the jitter compensation type including an intersymbol interference type and a noise type,
Wherein the first detection unit comprises a fifth trigger, a sixth trigger and a third exclusive-OR gate,
The second detection unit comprises a seventh trigger, an eighth trigger and a fourth exclusive-OR gate,
The fifth flip-flop generating a first sampling signal from a complement of the data input signal and the first clock signal, the sixth flip-flop generating the first logic signal from the first sampling signal and the reference clock signal,
The seventh flip-flop generating a second sampling signal from a complement of the data input signal and the second clock signal, the eighth flip-flop generating the second logic signal from the second sampling signal and the reference clock signal,
The indication signals comprise a first indication signal, a second indication signal and a third indication signal,
If the first logic signal is high and the second logic signal is high when the data input signal level state changes, the first indication signal is active,
If the second logic signal is high and the first logic signal is high when the data input signal level state changes, the second indication signal is active,
If the first logic signal and/or the second logic signal are high and the level state of the first logic signal and/or the second logic signal remains unchanged when the level state of the data input signal is changed, the third indication signal is valid,
When the third indication signal is active, the bandwidths of the reference clock signal, the first clock signal and the second clock signal are increased,
Receiving an original signal and providing a compensation signal to the original signal to generate the data input signal, the gain of the compensation signal being controlled by the first indication signal and the second indication signal,
When the first indication signal is active, the gain of the compensation signal is reduced,
When the second indication signal is active, the gain of the compensation signal increases.
2. The detection circuit of claim 1, wherein the reference clock signal has a period of T, the first clock signal and the reference clock signal have a phase difference of greater than 0 and no greater than T/4, and the second clock signal and the reference clock signal have a phase difference of greater than 0 and no greater than T/4.
3. The detection circuit of claim 1, wherein the detection circuit comprises a logic circuit,
The main circuit comprises a first trigger, a second trigger, a third trigger, a fourth trigger, a first exclusive-OR gate and a second exclusive-OR gate,
The intermediate signals include a first intermediate signal, a second intermediate signal, a third intermediate signal and a fourth intermediate signal,
The adjustment indicating signal comprises a first adjustment indicating signal and a second adjustment indicating signal,
The first flip-flop generates the first intermediate signal from the data input signal and the reference clock signal,
The second flip-flop generates the second intermediate signal from the first intermediate signal and the reference clock signal,
The third flip-flop generates the third intermediate signal from the complement of the data input signal and the reference clock signal,
The fourth flip-flop generates the fourth intermediate signal from the third intermediate signal and the reference clock signal,
The first exclusive-or gate generates the first adjustment indication signal from the second intermediate signal and the fourth intermediate signal,
The second exclusive-or gate generates the second adjustment indication signal according to the first intermediate signal and the fourth intermediate signal.
4. The detection circuit of claim 1, wherein the detection circuit comprises a logic circuit,
When the detection is carried out, the first detection unit, the second detection unit and the judging unit are started,
And when the detection is stopped, the first detection unit, the second detection unit and the judging unit are turned off.
5. A clock data recovery circuit, comprising:
The detection circuit of any one of claims 1 to 4, the main circuit of the detection circuit generating a recovered data signal;
a clock generating unit, configured to provide a clock signal, where the clock signal includes the reference clock signal, the first clock signal, and the second clock signal, and a bandwidth of the clock signal is controlled by the indication signal; and
A filter connected to the detection circuit for generating a voltage signal based on the adjustment indication signal,
The output end of the filter is connected to the clock generation unit, and the clock generation unit also generates a recovered clock signal according to the voltage signal and provides the recovered clock signal to the detection circuit.
6. The clock data recovery circuit of claim 5, further comprising: and the equalizer is used for receiving an original signal and providing a compensation signal for the original signal so as to generate the data input signal, and the gain of the compensation signal is controlled by the indication signal.
7. The clock data recovery circuit of claim 6, wherein,
The indication signals include a first indication signal and a second indication signal for adjusting a high frequency gain of the equalizer, a third indication signal for adjusting a bandwidth of the clock generation unit,
If the first logic signal is high and the second logic signal is high when the data input signal level state changes, the first indication signal is active,
If the second logic signal is high and the first logic signal is high when the data input signal level state changes, the second indication signal is active,
If the first logic signal and/or the second logic signal are high and the level state of the first logic signal and/or the second logic signal remains unchanged when the level state of the data input signal is changed, the third indication signal is valid,
Wherein the gain of the compensation signal is reduced when the first indication signal is active,
When the second indication signal is active, the gain of the compensation signal is increased,
When the third indication signal is active, the bandwidth of the clock signal increases.
8. The clock data recovery circuit of claim 6, wherein,
Before starting to receive the original signal, the clock generating unit provides the first clock signal and the second clock signal for signal detection,
After receiving the original signal, the clock generation unit stops providing the first clock signal and the second clock signal to stop signal detection.
9. The clock data recovery circuit of claim 5, wherein the clock generation unit comprises:
A clock generator for generating the first clock signal;
a first delay unit for generating the reference clock signal according to the first clock signal; and
A second delay unit for generating the second clock signal according to the reference clock signal,
The period of the reference clock signal is T, the phase difference between the first clock signal and the reference clock signal is more than 0 and not more than T/4, and the phase difference between the second clock signal and the reference clock signal is more than 0 and not more than T/4.
10. A signal detection method, comprising:
A plurality of intermediate signals and adjustment indication signals are provided in dependence on the data input signal and the reference clock signal,
Generating a first logic signal from the data input signal, the reference clock signal, the corresponding intermediate signal, and a first clock signal that leads the reference clock signal;
generating a second logic signal based on the data input signal, the reference clock signal, the corresponding intermediate signal, and a second clock signal that lags the reference clock signal; and
Generating an indication signal based on a logical relation between the first logic signal, the second logic signal and the data input signal, the indication signal characterizing a type of jitter compensation required for the data input signal, the type of jitter compensation comprising an intersymbol interference type and a noise type,
Wherein the indication signals comprise a first indication signal, a second indication signal and a third indication signal,
If the first logic signal is high and the second logic signal is high when the data input signal level state changes, the first indication signal is active,
If the second logic signal is high and the first logic signal is high when the data input signal level state changes, the second indication signal is active,
If the first logic signal and/or the second logic signal are high and the level state of the first logic signal and/or the second logic signal remains unchanged when the level state of the data input signal is changed, the third indication signal is valid,
When the third indication signal is active, the bandwidths of the reference clock signal, the first clock signal and the second clock signal are increased,
Receiving an original signal and providing a compensation signal to the original signal to generate the data input signal, the gain of the compensation signal being controlled by the first indication signal and the second indication signal,
When the first indication signal is active, the gain of the compensation signal is reduced,
When the second indication signal is active, the gain of the compensation signal is increased,
Generating a first sampling signal from a complement of the data input signal and the first clock signal, generating the first logic signal from the first sampling signal and the reference clock signal,
And generating a second sampling signal according to the complementary signals of the data input signal and the second clock signal, and generating the second logic signal according to the second sampling signal and the reference clock signal.
11. The signal detection method of claim 10, further comprising generating the reference clock signal, the first clock signal, and the second clock signal, the method of generating the reference clock signal, the first clock signal, and the second clock signal comprising:
Generating the first clock signal;
generating the reference clock signal from the first clock signal; and
Generating the second clock signal from the reference clock signal,
The period of the reference clock signal is T, the phase difference between the first clock signal and the reference clock signal is more than 0 and not more than T/4, and the phase difference between the second clock signal and the reference clock signal is more than 0 and not more than T/4.
12. The method for detecting a signal according to claim 10, wherein,
The intermediate signals include a first intermediate signal, a second intermediate signal, a third intermediate signal and a fourth intermediate signal,
The adjustment indicating signal comprises a first adjustment indicating signal and a second adjustment indicating signal,
The method for generating the adjustment indicating signal comprises the following steps:
generating the first intermediate signal from the data input signal and the reference clock signal,
Generating the second intermediate signal from the first intermediate signal and the reference clock signal,
Generating the third intermediate signal from the complement of the data input signal and the reference clock signal,
Generating the fourth intermediate signal from the third intermediate signal and the reference clock signal,
Generating the first adjustment indication signal from the second intermediate signal and the fourth intermediate signal,
The second adjustment indication signal is generated from the first intermediate signal and the fourth intermediate signal.
13. The method for detecting a signal according to claim 10, wherein,
When signal detection is carried out, the first clock signal and the second clock signal are received, the indication signal is generated,
And when the signal detection is stopped, stopping receiving the first clock signal and the second clock signal, and stopping generating the indication signal.
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| CN113067655B (en) * | 2020-01-02 | 2023-05-12 | 上海诺基亚贝尔股份有限公司 | Method, apparatus, device and computer storage medium for clock synchronization |
| CN112130921B (en) * | 2020-09-30 | 2023-10-03 | 合肥沛睿微电子股份有限公司 | Method for quickly recovering working state and electronic device |
| CN117975844A (en) * | 2022-10-25 | 2024-05-03 | 摩星半导体(广东)有限公司 | A driving circuit and a display device |
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