CN109787595B - Matrix switch and control method thereof - Google Patents
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- CN109787595B CN109787595B CN201811641316.3A CN201811641316A CN109787595B CN 109787595 B CN109787595 B CN 109787595B CN 201811641316 A CN201811641316 A CN 201811641316A CN 109787595 B CN109787595 B CN 109787595B
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Abstract
The invention provides a matrix switch and a control method thereof, wherein the matrix switch decomposes a high-density matrix switch into a plurality of small-scale peripheral matrix switches and a central matrix switch, and the peripheral matrix switches and the central matrix switch are only communicated with switches belonging to the same row and column, so that the number of branches of signal transmission among rows and columns of the whole matrix switch can be reduced on the premise of not changing the scale of an external channel, and the bandwidth performance is improved; the control method can record the times that each switch in each matrix is closed and used, then selects one of the peripheral matrix switches which is unoccupied and has the least conducted times to form a passage with the central matrix switch, can realize the balance of the closing times of each row and each column of switches, and plans the using times of each switch according to the requirement, thereby avoiding the condition that part of switches are aged and the other part of switches are rarely used.
Description
Technical Field
The invention belongs to the technical field of switch software design, and particularly relates to a matrix switch and a control method thereof.
Background
The matrix switch in the automatic test system is a pivot connected with signals and used for flexibly switching a plurality of test points of a tested object and a plurality of test instruments. Along with the increase of the complexity of a tested object, the channel quantity and the bandwidth range of a tested signal are increased sharply, the requirements on the density and the bandwidth characteristics of a matrix switch are higher and higher, the indexes and the functions of an automatic test system are influenced by the performance of the existing matrix, and the bandwidth of the signal is restricted.
Referring to fig. 1, a matrix switch constructed in the prior art to realize an 8 × 32 matrix switch combination is shown; wherein n 1-n 32 are input ends, m 1-m 8 are output ends, if the input end n31 and the output end m7 are adopted to connect external equipment to be tested for function test, 32+8 and 40 branch points are provided in the signal transmission process, the number of the branch points is large, and the bandwidth of the signal is severely restricted.
Disclosure of Invention
In order to solve the above problems, the present invention provides a matrix switch and a control method thereof, which can reduce the number of branches of signal transmission between rows and columns and the length of a signal line on the premise of not changing the scale of an external channel, thereby improving the bandwidth performance.
A matrix switch comprises four MxN surrounding matrix switches and a2 NxM central matrix switch;
each row of the surrounding matrix switches is provided with an input end, each column is provided with an output end, and only the switches belonging to one row and the switches belonging to one column are communicated;
each row of the central matrix switch is respectively provided with two input ends, each column is provided with an output end, and only the switches belonging to one row and the switches belonging to one column are communicated;
the output ends of all the columns of the peripheral matrix switches are respectively connected with the input ends of the central matrix switch in a one-to-one correspondence mode, and the input ends of all the rows of the peripheral matrix switches and the output ends of all the columns of the central matrix switch are used for being connected with a test end of the equipment to be tested.
Further, the size of the peripheral matrix switches is 8 rows and 8 columns, and the size of the central matrix switch is 16 rows and 8 columns.
Further, the central matrix switch is arranged in the middle of the peripheral matrix switches.
Further, the switches in the central matrix switch and the peripheral matrix switch are relays.
A method of controlling a matrix switch, comprising the steps of:
s1: respectively connecting 4 multiplied by M input ends of all peripheral matrix switches with a test end of equipment to be tested, and randomly selecting the equipment to be tested as current test equipment; wherein M is the number of rows of each peripheral matrix switch;
s2: selecting any output end of the central matrix switch to be connected to the other test end of the current test equipment;
s3: acquiring a row where input ends of four matrix switches connected with the current test equipment are located and a column where output ends of a central matrix switch are located, and respectively representing the row where the input ends of the four matrix switches are located and the column where the output ends of the central matrix switch are located as an X row and a Y column, wherein X =1,2, …, M, Y =1,2, …, M;
s4: conducting N switches which are not occupied and are conducted for the least times in the X row of the N switches of the peripheral matrix switch where the input end connected with the current test equipment is located, and recording the conducted switches as X m Wherein m =1,2, …, N is the number of columns of each four-side matrix switch; then the Y column of the central matrix switch is connected with the switch X m The switches connected with the columns are conducted, so that a path is formed among the current test equipment, the peripheral matrix switches and the central matrix switch, and the function test of the current test equipment is realized;
s5: randomly selecting one piece of equipment to be tested as current testing equipment again, selecting any one of unoccupied output ends in the central matrix switch to be connected to the other testing end of the current testing equipment, and repeating the steps S3-S4 to complete the function test of the other current testing equipment; and repeating the steps until the function test of all the devices to be tested is completed.
Further, the size of the peripheral matrix switches is 8 rows and 8 columns, and the size of the central matrix switch is 16 rows and 8 columns.
Further, the central matrix switch is arranged in the middle of the peripheral matrix switches.
Further, the switches in the central matrix switch and the peripheral matrix switch are relays.
Has the advantages that:
1. the invention provides a matrix switch, which decomposes a high-density matrix switch into a plurality of small-scale peripheral matrix switches and a central matrix switch, wherein the peripheral matrix switches and the central matrix switch are only communicated with switches in a same row and a same column; if an external signal needs to be transmitted from a path formed by a certain input end of a certain peripheral matrix switch and a certain output end of a central matrix switch, only any switch on a row of the peripheral matrix switch where the input end is located needs to be conducted, and then a switch corresponding to a row of the central matrix switch where the central matrix switch connected with a row of the conducted switches is located is conducted on the row of the central matrix switch where the output end of the central matrix switch is located, so that the external signal can directly enter the selected central matrix switch output end from the peripheral matrix switch without passing through other peripheral matrix switches; therefore, the invention can reduce the branching number of signal transmission between the whole matrix switch row and column under the premise of not changing the scale of the external channel, thereby improving the bandwidth performance.
2. The control method of the matrix switch can record the times that each switch is closed and used, then selects one of the matrix switches at the periphery which is unoccupied and has the least conducting times to form a passage with the central matrix switch, can realize the balance of the closing times of the switches at each row and each column, and plans the using times of each switch according to the requirement, thereby avoiding the condition that part of the switches are aged and the other part of the switches are rarely used.
Drawings
FIG. 1 is a schematic diagram of a conventional matrix switch;
fig. 2 is a schematic structural diagram of a matrix switch provided in the present invention.
Detailed Description
In order to make the technical solutions better understood by those skilled in the art, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application.
Example one
A matrix switch according to the present embodiment will be described in detail below by taking an example of realizing an 8 × 32 matrix switch combination. Referring to fig. 2, the figure is a schematic structural diagram of a matrix switch provided in this embodiment.
To achieve an 8 × 32 matrix switch combination, the 8 × 32 matrix switch combination is decomposed into 4 8 × 8 peripheral matrix switches A1, A2, A3, and A4, and 1 16 × 8 central matrix switch B. Wherein, in order to further shorten the wiring distance of the PCB, the central matrix switch is arranged in the middle of the peripheral matrix switches.
Each row of the surrounding matrix switches is provided with an input end, each column is provided with an output end, and only the switches belonging to one row and the switches belonging to one column are communicated.
It should be noted that the input end of each row of the matrix switches around may be disposed on any one switch, and the output end of each column may also be disposed on any one switch; for the convenience of control, it is preferable that the input terminal of each row of the peripheral matrix switch is disposed on the last switch, and the output terminal is disposed on the last switch of each column.
For example, as shown in FIG. 2, the input terminals of the peripheral matrix switch A1 are n1 to n8, the input terminals of the peripheral matrix switch A2 are n9 to n16, the input terminals of the peripheral matrix switch A3 are n17 to n24, and the input terminals of the peripheral matrix switch A4 are n25 to n32.
Similarly, the input end of each row of the central matrix switch can be arranged on any switch, and the output end of each column can also be arranged on any switch; preferably, the two input terminals of each row of the central matrix switch are respectively arranged on the first switch and the last switch, the output terminal of each column is arranged on the first switch, and only the switches of the same row and the same column are communicated.
For example, as shown in fig. 2, the first switch and the last switch in each row of the central matrix switch are used as input terminals, and there are 32 input terminals in total, and these 32 input terminals are respectively connected to 32 output terminals of four peripheral matrix switches, and the output terminals of the central matrix switch are m1 to m8.
The output ends of all the columns of the peripheral matrix switches are respectively connected with the input ends of the central matrix switch in a one-to-one correspondence mode, and the input ends of all the rows of the peripheral matrix switches and the output ends of all the columns of the central matrix switch are used for being connected with a test end of the equipment to be tested.
It should be noted that the peripheral matrix switches and the central matrix switch are only communicated with the switches in the same row and the same column, that is, signals in the peripheral matrix switches and the central matrix switch cannot turn and can only be transmitted on one straight line, and if turning is needed, the switch at the turning position needs to be turned on; if an external signal enters the high bandwidth matrix switch of this embodiment from the input terminal n1 of the peripheral matrix switch A1, the external signal can only be transmitted on the first row of the peripheral matrix switch A1, and cannot be transmitted downward, and if downward transmission is required, a specific switch needs to be turned on, so that the external signal goes downward from the column where the switch is turned on.
Optionally, each of the small switches in the peripheral matrix switch and the central matrix switch is a relay, and if a contact of the relay is closed, the row and the column where the relay is located are communicated.
Example two
Based on the above embodiments, this embodiment provides a control method for a matrix switch, including the following steps:
s1: respectively connecting 4 multiplied by M input ends of all peripheral matrix switches with a test end of equipment to be tested, and randomly selecting the equipment to be tested as current test equipment; wherein M is the number of rows of each peripheral matrix switch;
s2: selecting any one output end of the central matrix switch to be connected to the other test end of the current test equipment;
s3: acquiring a row where input ends of four matrix switches connected with the current test equipment are located and a column where output ends of a central matrix switch are located, and respectively representing the row where the input ends of the four matrix switches are located and the column where the output ends of the central matrix switch are located as an X row and a Y column, wherein X =1,2, …, M, Y =1,2, …, M;
s4: conducting an unoccupied switch with the least conducted switch in the N switches in the X row of the peripheral matrix switch where the input end connected with the current test equipment is located, and recording the conducted switch as X m Wherein m =1,2, …, N is the number of columns of each four-side matrix switch; then the Y column of the central matrix switch is connected with the switch X m The switches connected with the columns are conducted, so that a path is formed among the current test equipment, the peripheral matrix switches and the central matrix switch, and the function test of the current test equipment is realized;
it should be noted that, if the switch X of the X-th row of the peripheral matrix switch is used m When turned on, the switch X is the peripheral matrix switch m All switches on the column are occupied; meanwhile, for any current test device, if the switches turned on by the peripheral matrix switches in the function test of the previous current test device are turned off before determining which switch on the X-th row of the peripheral matrix switches needs to be turned on in the function test, all the switches in the column where the turned-off switches are located are released.
S5: randomly selecting one piece of equipment to be tested as current testing equipment again, selecting any one of unoccupied output ends in the central matrix switch to be connected to the other testing end of the current testing equipment, and repeating the steps S3-S4 to complete the function test of the other current testing equipment; and repeating the steps until the function tests of all the devices to be tested are completed.
It should be noted that, for any current test device, if the output terminal of the central matrix switch occupied in the function test of the previous current test device is released before the output terminal of the central matrix switch used in the function test is determined, the released output terminal belongs to the unoccupied output terminal of the central matrix switch.
It should be noted that, each time a path is established between the peripheral matrix switch and the central matrix switch, in the simplest case, the first row is selected from the 1 st row to the 8 th row of the peripheral matrix switch, and when the path is established between the method and the central matrix switch, if a user turns on each row of the peripheral matrix switch in sequence each time, the number of times of using the relays in each row and each column of the peripheral matrix switch will be kept average, but in the actual use process, if the switches in the first row and the first column are not occupied, the user may preferentially select the switches in the first row to be turned on, and therefore, the number of times of using the relays in each row and each column of the peripheral matrix switch is different, and in the case of setting in sequence, the number of times of using the relays in the 1-8 rows and the 1-8 columns is then decreased in sequence, and the service life of each relay is constant, and the situations that the relays in the first rows and the first columns may be worn too fast may occur. Meanwhile, the switches arranged in the front row of the peripheral matrix switches are connected to the switches arranged in the front row of the central matrix, so that the switches arranged in the front row of the peripheral matrix switches are used too many times, which also results in that the switches arranged in the front row of the central matrix switches are used too many times.
Therefore, the present embodiment provides a method for controlling a matrix switch, which records the number of times that a relay is closed and used in each peripheral matrix switch, for example, the relay is closed and used cumulatively, and then selects one switch that is unoccupied and has the least number of times that the relay is turned on, so that the balance of the number of times that each column of relays in each row of the matrix switch is closed can be achieved, and a situation that some relays are aged and another part of relays are used rarely is avoided.
Referring to fig. 2, assuming that an input end n1 of a peripheral matrix switch A1 and an output end m8 of a central matrix switch are connected to two test ends of a device to be tested, that is, X =1, y =8, a closed path is to be implemented between the device to be tested and the high bandwidth matrix switch of this embodiment, one switch may be randomly selected from the 1 st row and the 1 st column of the peripheral matrix switch A1 to be turned on, at this time, assuming that the 1 st column is selected, a test signal of the device to be tested will go down along the 1 st row and the 1 st column of the peripheral matrix switch A1, because an output end of the 1 st column of the peripheral matrix switch A1 is connected to an input end of the 8 th row of the central switch matrix, the test signal will directly enter the 8 th row of the central switch matrix and be transmitted forward, at this time, a switch of the 8 th row and the 8 th column of the central matrix switch is turned on, the test signal will go up along the 8 th row and return to another test end of the device to be tested from the output end m8, thereby implementing a function test of the device to be tested.
Therefore, according to the control method of the matrix switch provided by the embodiment, when the test signal is input from the input ends of the matrix switches around, the corresponding matrix switch is closed, so that the test signal directly enters the selected small switch where the output end of the central matrix switch is located; meanwhile, the central matrix switch can be arranged in the middle of the four peripheral matrix switches, so that the wiring distance of the PCB is further shortened, and the signal bandwidth is improved.
The present invention may be embodied in other specific forms without departing from the spirit or essential attributes thereof, and it will be understood by those skilled in the art that various changes and modifications may be made herein without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (8)
1. A matrix switch, comprising four MxN peripheral matrix switches and a2 NxM central matrix switch;
each row of the surrounding matrix switches is provided with an input end, each column is provided with an output end, and only the switches belonging to one row and the switches belonging to one column are communicated;
each row of the central matrix switch is respectively provided with two input ends, each column is provided with an output end, and only the switches belonging to one row and the switches belonging to one column are communicated;
the output ends of all the columns of the peripheral matrix switches are respectively connected with the input ends of the central matrix switch in a one-to-one correspondence mode, and the input ends of all the rows of the peripheral matrix switches and the output ends of all the columns of the central matrix switch are used for being connected with a test end of the equipment to be tested.
2. A matrix switch according to claim 1 wherein the dimensions of the four surrounding matrix switches are 8 rows and 8 columns and the dimensions of the central matrix switch are 16 rows and 8 columns.
3. A matrix switch according to claim 1, characterized in that the central matrix switch is arranged in the middle of the four peripheral matrix switches.
4. A matrix switch as claimed in claim 1 wherein the switches in the central and peripheral matrix switches are relays.
5. A control method based on the matrix switch of claim 1, characterized by comprising the following steps:
s1: respectively connecting 4 multiplied by M input ends of all surrounding matrix switches with a test end of equipment to be tested, and randomly selecting the equipment to be tested as current test equipment; wherein M is the number of rows of each peripheral matrix switch;
s2: selecting any one output end of the central matrix switch to be connected to the other test end of the current test equipment;
s3: acquiring a row where input ends of four matrix switches connected with the current test equipment are located and a column where output ends of a central matrix switch are located, and respectively representing the row where the input ends of the four matrix switches are located and the column where the output ends of the central matrix switch are located as an X row and a Y column, wherein X =1,2, …, M, Y =1,2, …, M;
s4: conducting N switches which are not occupied and are conducted for the least times in the X row of the N switches of the peripheral matrix switch where the input end connected with the current test equipment is located, and recording the conducted switches as X m Wherein m =1,2, …, N is the number of columns of each four-side matrix switch; then the Y column of the central matrix switch is connected with the switch X m The switches connected with the columns are conducted, so that a path is formed among the current test equipment, the peripheral matrix switches and the central matrix switch, and the function test of the current test equipment is realized;
s5: randomly selecting a piece of equipment to be tested as current test equipment again, selecting any one of unoccupied output ends in the central matrix switch to be connected to the other test end of the current test equipment, and repeating the steps S3-S4 to complete the function test of the other current test equipment; and repeating the steps until the function test of all the devices to be tested is completed.
6. The method as claimed in claim 5, wherein the size of the peripheral matrix switches is 8 rows and 8 columns, and the size of the central matrix switch is 16 rows and 8 columns.
7. A method of controlling matrix switches according to claim 5, wherein the central matrix switch is arranged in the middle of the four matrix switches.
8. The method of claim 5, wherein the switches in the central matrix switch and the peripheral matrix switch are relays.
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| CN112484309B (en) * | 2020-10-30 | 2022-12-13 | 青岛经济技术开发区海尔热水器有限公司 | A control method and an electric water heater for the alternate use of multiple switches |
| CN115848200B (en) * | 2023-02-06 | 2023-05-16 | 石家庄科林电气股份有限公司 | Group control charging system and control method thereof |
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|---|---|---|---|---|
| EP0373714A1 (en) * | 1988-12-16 | 1990-06-20 | Koninklijke Philips Electronics N.V. | Coupling network for a data processor, comprising a series connection of at least one crossbar switch and at least one array of silos, and data processor comprising such a coupling network |
| EP1045265A2 (en) * | 1999-04-16 | 2000-10-18 | Agilent Technologies Inc., A Delaware Corporation | Optical switch having test ports |
| CN104515949A (en) * | 2014-12-26 | 2015-04-15 | 北京航天测控技术有限公司 | General adaptive assembly for interface and signal path planning method based on adaptive assembly |
| CN108318718A (en) * | 2017-12-26 | 2018-07-24 | 北京航天测控技术有限公司 | A method of it improving high-density matrix and switchs bandwidth performance |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006153793A (en) * | 2004-12-01 | 2006-06-15 | Agilent Technol Inc | Switching matrix for semiconductor characteristics measuring device |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0373714A1 (en) * | 1988-12-16 | 1990-06-20 | Koninklijke Philips Electronics N.V. | Coupling network for a data processor, comprising a series connection of at least one crossbar switch and at least one array of silos, and data processor comprising such a coupling network |
| EP1045265A2 (en) * | 1999-04-16 | 2000-10-18 | Agilent Technologies Inc., A Delaware Corporation | Optical switch having test ports |
| CN104515949A (en) * | 2014-12-26 | 2015-04-15 | 北京航天测控技术有限公司 | General adaptive assembly for interface and signal path planning method based on adaptive assembly |
| CN108318718A (en) * | 2017-12-26 | 2018-07-24 | 北京航天测控技术有限公司 | A method of it improving high-density matrix and switchs bandwidth performance |
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