CN109783395B

CN109783395B - Memory access method, exchange chip, memory module and electronic equipment

Info

Publication number: CN109783395B
Application number: CN201711132919.6A
Authority: CN
Inventors: 牛功彪; 郭青松
Original assignee: Alibaba Group Holding Ltd
Current assignee: Alibaba Group Holding Ltd
Priority date: 2017-11-15
Filing date: 2017-11-15
Publication date: 2023-03-31
Anticipated expiration: 2037-11-15
Also published as: CN109783395A

Abstract

The embodiment of the application provides a memory access method, a switching chip, a memory module and electronic equipment. In the embodiment of the present application, a switch chip is added in the memory module, the switch chip interconnects memory granules with a bit width of L1 included in each memory block in the memory module, and provides a virtual memory block adapted to the bit width L of the memory controller to the memory controller based on the memory blocks, the bit width of the virtual memory space is L2, and L = L2 × N, L < L1 is satisfied, so that the memory controller can successfully access the first memory block. Since the actual memory space of the first memory block is L1 × N > L2 × N, it can be seen that the memory capacity expansion can be achieved without increasing the number of CPUs integrated with the memory controller, and the implementation cost is relatively low.

Description

Memory access method, exchange chip, memory module and electronic equipment

Technical Field

The present application relates to the field of storage technologies, and in particular, to a memory access method, a switch chip, a memory module, and an electronic device.

Background

In the use process of devices such as a server and a terminal device, the situation of insufficient memory often occurs. The memory capacity is primarily limited by the capacity of the memory controller and the individual memory grains. The capacity of a single Memory particle depends on the particle process and the manufacturing process of a Dynamic Random Access Memory (DRAM), and the particle process is slow to progress, and cannot meet the demand of application on the Memory capacity in time.

In order to solve the problem of memory requirement, the conventional method increases the memory capacity by increasing the number of memory controllers, and since the memory controllers are integrated with a Central Processing Unit (CPU), the implementation cost of this method is high, and therefore a new solution is needed to solve the problem of memory capacity expansion.

Disclosure of Invention

Aspects of the present application provide a memory access method, a switch chip, a memory module, and an electronic device, so as to implement memory capacity expansion and reduce implementation cost.

An embodiment of the present application provides a memory access method, which is applicable to a memory module, where the memory module includes at least one memory block, and each memory block includes N memory granules with a bit width of L1, where the method includes:

splitting a data signal with the bit width L output by a memory controller into N downlink data signals with the bit width L2 according to a bit width mapping relation between the bit width L corresponding to the first memory block in the memory module and the bit width L2;

splicing the N downlink data signals with the bit width L2 into K1 data signals with the bit width L1 according to an addressing mapping relation between the bit width L1 and the bit width L2 corresponding to the first memory block;

writing the K1 data signals with the bit width of L1 into K1 memory grains of the first memory block; wherein, L = L2N, L2< L1, K1< = N, and L1, L2, K1, N are all positive integers.

An embodiment of the present application further provides a memory access method, which is applicable to a memory module, where the memory module includes at least one memory block, and each memory block includes N memory granules with a bit width of L1, where the method includes:

reading K2 data signals with L1 bit width from K2 memory granules of a first memory block in the memory module;

splitting the K2 data signals with the bit width L1 into N groups of uplink data signals with the bit width L2 according to an addressing mapping relation between the bit width L1 and the bit width L2 corresponding to the first memory block, wherein each group comprises L1/L2 uplink data signals with the bit width L2;

combining the N groups of uplink data signals with the bit width L2 into L1/L2 data signals with the bit width L according to the bit width mapping relation between the bit width L corresponding to the first memory block and the bit width L2, and sequentially outputting the data signals to a memory controller; wherein, L = L2 × N, L2< L1, K2< = N, and L1, L2, K2, N are all positive integers.

The embodiment of the present application further provides a memory module, including: the memory comprises at least one memory block and an exchange chip, wherein each memory block comprises N memory particles with L1 bit width;

the switch chip includes: the memory controller comprises a control unit, an uplink port group connected with the memory controller and a plurality of downlink port groups correspondingly connected with each memory particle in at least one memory block; the control unit is respectively connected with the uplink port and the plurality of downlink port groups;

the control unit is used for: providing a virtual memory space adapted to the bit width L of the memory controller to the memory controller based on the at least one memory block, where the bit width of the virtual memory space is L2, L = L2 × N, L2< L1, and L1, L2, and N are positive integers.

An embodiment of the present application further provides a switch chip, including: the memory control device comprises a control unit, an uplink port group connected with a memory controller and a plurality of downlink port groups correspondingly connected with memory particles in at least one memory block contained in a memory module; the control unit is respectively connected with the uplink port and the plurality of downlink port groups;

the control unit is used for: providing a virtual memory space adapted to a bit width L of the memory controller to the memory controller based on the at least one memory block, where a bit width of the virtual memory space is L2, L = L2 × N, L2< L1, and L1, L2, and N are positive integers.

An embodiment of the present application further provides an electronic device, including: the memory module, the memory controller and the processor provided by the above embodiments; and the processor accesses the memory module through the memory controller.

In the embodiment of the present application, a switch chip is added in the memory module, the switch chip interconnects memory grains with a bit width of L1 included in each memory block in the memory module, and provides a virtual memory block adapted to the bit width L of the memory controller to the memory controller based on the memory blocks, the bit width of the virtual memory space is L2, and L = L2 × N, L < L1 is satisfied, so that the memory controller can successfully access each memory block. Since the actual memory space of the memory block is L1 × N > L2 × N, it can be seen that the memory capacity expansion can be realized without increasing the number of CPUs integrated with the memory controller, and the realization cost is relatively low.

Drawings

The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the application and together with the description serve to explain the application and not to limit the application. In the drawings:

fig. 1 is a schematic structural diagram of a memory module according to an exemplary embodiment of the present disclosure;

fig. 2 is a schematic structural diagram of a switch chip according to another exemplary embodiment of the present application;

FIG. 3 is a schematic diagram of another switch chip according to another exemplary embodiment of the present application;

fig. 4 is a schematic flowchart of a memory access method according to another exemplary embodiment of the present application;

fig. 5 is a schematic flow chart illustrating another memory access method according to another exemplary embodiment of the present application;

fig. 6 is a schematic structural diagram of an electronic device according to still another exemplary embodiment of the present application.

Detailed Description

In order to make the objects, technical solutions and advantages of the present application more apparent, the technical solutions of the present application will be described in detail and completely with reference to the following specific embodiments of the present application and the accompanying drawings. It should be apparent that the described embodiments are only some of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

In the face of the problem of memory capacity expansion in the prior art, the embodiment of the present application provides a solution, and the basic idea is: the memory controller is characterized in that a switching chip is added in the memory module, the switching chip interconnects memory particles with bit width L1 contained in each memory block in the memory module, and provides a virtual memory block adaptive to the bit width L of the memory controller for the memory controller based on the memory blocks, the bit width of a virtual memory space is L2, and L = L2 x N, L < L1 is met, so that the memory controller can successfully access each memory block. Since the actual memory space of the memory block is L1 × N > L2 × N, it can be seen that the memory capacity expansion can be realized without increasing the number of CPUs integrated with the memory controller, and the realization cost is relatively low.

The technical solutions provided by the embodiments of the present application are described in detail below with reference to the accompanying drawings.

Fig. 1 is a schematic structural diagram of a memory module 100 according to an exemplary embodiment of the present disclosure. As shown in fig. 1, the memory module 100 includes: at least one memory block (RANK) and a switch chip.

Each RANK includes N memory grains with a bit width L1. The memory granule is the smallest unit of memory that forms the memory module 100, and may also be referred to as a memory chip. Bit width L1 of the memory granule represents the number of data bits that the memory granule can provide in one clock cycle. L1 and N are positive integers. In general L1=2 ⁿ And n is a positive integer. For example, L1 can be the number of bits supported by any memory grain process such as 8, 4, 16, etc. At least one RANK constitutes the real storage space of the memory module 100. The CPU accessing the memory module 100 through the memory controller is actually the process of accessing the memory granules contained in each RANK in the memory module 100 through the memory controller. For simplicity of description, the phrase "the CPU accesses the memory module 100 or the memory granule through the memory controller" may be simply expressed as "the memory controller accesses the memory module 100 or the memory granule".

Alternatively, the memory granules may be any one of phase change memory (PRAM), static Random Access Memory (SRAM), dynamic Random Access Memory (DRAM), other types of Random Access Memory (RAM), read Only Memory (ROM), electrically Erasable Programmable Read Only Memory (EEPROM), flash memory, compact disc read only memory (CD-ROM), digital Versatile Disc (DVD), magnetic cassette tape, and the like.

For the sake of distinction, let the bit width of the memory controller be L, i.e. the number of data bits that the memory controller can write into or read from the memory module 100 in one clock cycle. Generally, the bit width L of the memory controller is greater than the bit width L1 of a single memory granule. According to the prior art process, a RANK can contain a maximum number of memory granules of L/L1 in order to adapt to the bit width L of the memory controller. For example, assuming that the bit width L =72bit of the memory controller and the bit width of the memory granule =8bit, a RANK can be obtained according to the processing method of the prior art, which can include at most 72/8=9 memory granules. If one wants to extend the storage capacity of the RANK, it is common practice to try to use memory granules with larger capacity. If 9 memory grains are already the maximum capacity supported by the memory grain process, it means that the storage capacity of the RANK cannot be expanded any more.

In this embodiment, in order to implement the memory capacity expansion, a swap chip is added in the memory module 100. The switch chip is used for realizing interconnection between the memory particles included in each RANK and interconnection between the memory module 100 and the memory controller; on the other hand, a virtual memory space adapted to the bit width L of the memory controller is provided to the memory controller based on the memory blocks in the memory module 100, so as to achieve the purpose of capacity expansion. As shown in fig. 1, the switch chip mainly includes: the system comprises a control unit, an uplink port group and a plurality of downlink port groups.

The upstream port set is used for connecting a memory controller, so as to implement interconnection between the memory module 100 and the memory controller. The uplink port set includes a plurality of pins, such as a data line pin, a control line pin, and an address line pin, which are in one-to-one correspondence with signal pins of the memory controller facing the memory module 100. Optionally, the interface standard followed by the upstream port group may be the same as the interface standard followed by the memory controller to improve the degree of adaptation between the ports. Alternatively, the interface standard to which the upstream port set and the memory controller conform may be, but is not limited to, the JTAG standard. As shown in fig. 1, the upstream port group is denoted as INTERFACE _ M. Where M represents the number of RANKs included in the memory module 100, and M =2 ⁿ And n may be an integer of 0, 1, 2, 3, etc.

The plurality of downlink port groups are used for connecting the memory granules included in each RANK, so as to realize interconnection between the memory granules included in each RANK. For convenience of illustration, fig. 1 shows a case where only one RANK is connected to the switch chip, but is not limited to one RANK. Correspondingly, fig. 1 also only shows N downstream PORT groups included in the switch chip, which are PORT _1, PORT _2, … … and PORT _ N, where N represents the number of memory granules included in one RANK. One downstream port group corresponds to one memory granule. Each downlink port group also comprises a plurality of pins such as a data line pin, a control line pin, an address line pin and the like, which are respectively in one-to-one correspondence with the signal pins of the corresponding memory particles. Optionally, the interface standard complied with by each downstream port group may be the same as the interface standard complied with by the corresponding memory granule. Alternatively, the interface standard compliant with the downstream port set and the memory granule may be, but is not limited to, the JTAG standard.

The control unit is mainly used for providing a virtual memory space adapted to the bit width L of the memory controller to the memory controller based on at least one memory block included in the memory module 100, so as to implement memory expansion.

Optionally, the control unit may provide a virtual memory space adapted to the bit width L of the memory controller to the memory controller through mapping of the data bit width in the process that the memory controller accesses the RANK in the memory module 100, so as to implement memory expansion. The mapping process of the data bit width is performed by taking RANK as a unit. In other words, during the process of accessing each RANK by the memory controller, the control unit maps the data bit width for each RANK to provide a different virtual RANK to the memory controller.

For example, when the memory controller accesses the first RANK in the memory module 100, the control unit maps the data bit width of the first RANK to provide a virtual memory space adapted to the bit width L of the memory controller for the memory controller, thereby implementing memory expansion. Wherein, the bit width of the virtual memory space is L2, and L = L2N, L2 is satisfied<L1. L2 is a positive integer, generally L2=2 ^m And m is a positive integer. For example, L2 can be any number of bits less than L1 among the number of bits supported by the memory grain process such as 2, 4, etc. The data bit width mapping for the first RANK effectively maps the first RANK comprising N memory granules with bit width L1 to a dummy RANK comprising N memory granules with bit width L2.

In the case that the bit width of the memory controller is L, in the memory module 100 provided in this embodiment, the maximum number of memory granules that can be included in one RANK is N = L/L2, because L2 is smaller than L1, compared with the prior art, the number of memory granules that can be included in each RANK is increased, and in the case that the bit width L1 of the memory granules is not changed, the memory capacity is increased. For example, if the bit width L =72bit of the memory controller, the bit width of the memory granule =8bit, and the bit width L2=4bit of the virtual memory space, a RANK can be obtained by the processing method in the prior art and can include at most 72/8=9 memory granules; in this embodiment, one RANK can contain at most 72/4=18 memory granules. This means that, for the same memory controller, the memory module of the prior art can support a RANK comprising 9 memory granules at most, while the memory module 100 of the present embodiment can support a RANK comprising 18 memory granules, which greatly expands the memory capacity.

In the above embodiment or the following embodiments, the memory controller accesses the memory module 100 mainly involve two processes of reading data from the memory module 100 and writing data into the memory module 100, and the process of the memory controller performing the read-write operation on each RANK is similar, except that the read-write data is different. Therefore, in the following embodiments of the present application, a process of performing data bit width mapping on the control unit by taking a process of performing read/write operations on the first RANK in the memory module 100 by the memory controller as an example will be described in detail.

The process of the memory controller writing data to the first RANK in the memory module 100 provided in the embodiment of the present application includes:

in the first step, the memory controller sends the memory address of the data to be written to the first RANK via the address line. The process is straight-through, the control unit does not perform special processing, namely, the memory address sent by the memory controller can directly reach the memory granules through the exchange chip.

In the second step, the memory controller sends out a memory write command through the control line, and selects the memory granules in the first RANK to inform the memory granules that data needs to be written into the memory granules. The process is also straight-through, and the control unit does not perform special processing, namely, the memory write command of the memory controller can directly reach the memory granules through the exchange chip. In this embodiment, it is assumed that the memory controller selects K1 memory granules in the first RANK, K1< = N, and K1 is a positive integer.

Thirdly, the memory controller outputs data with bit width L to the exchange chip through a data line; a control unit in the switch chip splits a data signal with a bit width of L output by a memory controller into N downlink data signals with a bit width of L2 according to a bit width mapping relation between the bit width L corresponding to the first RANK and the bit width L2; splicing N downlink data signals with the bit width L2 into K1 data signals with the bit width L1 according to an addressing mapping relation between the bit width L1 and the bit width L2 corresponding to the first RANK; and writing the K1 data signals with the bit width of L1 into K1 memory grains of the first memory block. At this point, the process of the memory controller writing data to the first RANK in the memory module 100 provided in this embodiment is finished.

The process of the memory controller reading data from the first RANK in the memory module 100 provided in the embodiment of the present application includes:

in the first step, the memory controller sends the memory address of the data to be read to the first RANK via the address line. The process is straight-through, the control unit does not perform special processing, namely, the memory address sent by the memory controller can directly reach the memory granules through the exchange chip.

In the second step, the memory controller issues a memory read command through the control line to select the memory granule in the first RANK to notify the memory granule that data needs to be read from the memory granule. The process is also straight-through, and the control unit does not perform special processing, namely, the memory read command of the memory controller can directly reach the memory granules through the exchange chip. In this embodiment, it is assumed that the memory controller selects K2 memory granules in the first RANK, K2< = N, and K2 is a positive integer.

Thirdly, a control unit in the exchange chip reads K2 data signals with L1 bit width from K2 memory particles of the first RANK; according to an addressing mapping relation between a bit width L1 and a bit width L2 corresponding to a first RANK, splitting K2 data signals with a bit width L1 into N groups of uplink data signals with a bit width L2, wherein each group comprises L1/L2 uplink data signals with a bit width L2; according to the bit width mapping relation between the bit width L corresponding to the first RANK and the bit width L2, N sets of uplink data signals with the bit width L2 are combined into L1/L2 data signals with the bit width L, and the data signals are sequentially output to a memory controller. At this point, the process of the memory controller reading data from the first RANK in the memory module 100 provided in this embodiment is finished.

It should be noted that, with the memory module 100 provided in the embodiment of the present application, in the process of the memory controller writing data to the first RANK and reading data from the first RANK, the processing logic of the memory controller and the memory granules is hardly changed, and the compatibility is better.

Before using the memory module 100 provided in this embodiment, an addressing mapping relationship between the bit width L1 and the bit width L2 may be formed in advance according to parameters, such as the number N of memory granules included in each RANK, the bit width L1 of the memory granules, and the bit width L2 of the virtual storage space. It should be noted that the forming process of the addressing mapping relationship between the bit width L1 and the bit width L2 corresponding to different RANKs is the same, but because the memory address ranges corresponding to different RANKs are different, the content of the addressing mapping relationship between the bit width L1 and the bit width L2 corresponding to different RANKs is different.

Taking the formation of the addressing mapping relationship between the bit width L1 and the bit width L2 corresponding to the first RANK as an example, the control unit in the switch chip may perform serial addressing on N memory grains in the first RANK to obtain an addressing sequence; then, dividing the memory address in the addressing sequence into L1 × N/L2 address segments, wherein the memory address in each address segment belongs to an address adaptive to the bit width L2; then dividing the L1N/L2 address segments into N address groups, wherein each group comprises L1/L2 address segments; and finally, establishing a mapping relation between the addressing sequence and the N address groups as an addressing mapping relation between the bit width L1 and the bit width L2 corresponding to the first RANK.

Alternatively, the address segments belonging to the same memory granule in the L1 × N/L2 address segments may be divided into one address group, so that the L1 × N/L2 address segments are divided into N address groups. Of course, other grouping schemes may be used in addition to this grouping scheme.

In some exemplary embodiments, in the process of generating the memory module 100, parameters such as the bit width L1, the bit width L2, and the number N of memory granules included in each RANK may be preset in the memory module 100. Based on this, in the process of forming the addressing mapping relationship between the bit width L1 and the bit width L2, the parameters such as the bit width L1 and the bit width L2 preset in the memory module 100, and the number N of memory particles included in each RANK may be directly used.

In other exemplary embodiments, to increase the flexibility of the memory module 100 in use, the memory module 100 supports configuration operations. Based on this, before using the memory module 100, the bit width L1, the bit width L2, and the number N of memory granules included in each RANK can be configured by the configuration instruction at any time. For example, parameters such as the bit width L1, the bit width L2, and the number N of memory granules included in each RANK may be configured through an interface of a device in which the memory module 100 is located. Therefore, the bit width L2 can be flexibly configured according to the application requirements, and the use mode of the memory module 100 is improved.

In the above embodiment, the process of mapping the data bit width of the control unit by taking the first RANK in the memory module 100 as an example is described in detail. In some embodiments, the memory module 100 includes a RANK, i.e., a first RANK. In an embodiment where the memory module 100 includes a RANK, the first RANK may be determined directly and then read from or write to the first RANK. In other embodiments, the memory module 100 includes two or more RANKs. In the embodiment where the memory module 100 includes two or more RANKs, a number may be set for each RANK, where the numbers of different RANKs are different, and a RANK number and memory address range mapping table is pre-established, where a memory address range corresponding to each RANK is stored in the mapping table, and different memory address ranges correspond to different RANKs, and a sum of the memory address ranges corresponding to all the RANKs included in the memory module 100 forms an addressing range of the memory module 100. Based on this, when the memory controller needs to write data into the memory module 100 or read data from the memory module 100, the RANK number and the memory address range mapping table may be queried according to the memory address that is output by the memory controller and is adapted to the bit width L2, so as to obtain the first RANK number; and determining the RAK identified by the first RANK number as the first RANK from at least one RANK, and then performing read-write operation on the first RANK. For example, the control unit may match the memory address output by the memory controller and adapted to the bit width L2 in each memory address range in the mapping table, and then obtain the RANK number corresponding to the memory address range in the matching, that is, the first RANK number. The process of performing the read/write operation on the first RANK refers to the description of the foregoing embodiment, and is not described herein again.

Alternatively, in some embodiments, the Memory Module 100 may be implemented In a standard manner, such as a standard Dual In-line Memory Module (DIMM), a Small Outline Dual In-line Memory Module (SO-DIMM), and the like. The memory module 100 of the standard type is compatible with various devices requiring a memory module in the prior art, such as a server, a terminal device, and the like.

Alternatively, in other embodiments, the memory module 100 may be implemented in a non-standard form. For example, the width, length, and thickness of the memory module 100 can be determined according to the specific application requirements, and are not limited by various memory standards, so as to realize the diversification of the memory module style.

Further, in addition to the memory module 100, the embodiment of the present application further provides a switch chip, which is suitable for the memory module 100. As shown in fig. 2, an exemplary embodiment of the present application provides a switch chip including: the system comprises a control unit, an uplink port group and a plurality of downlink port groups. In fig. 2, INTERFACE _ M indicates an uplink port group, where M in "INTERFACE _ M" is the same as the number of RANKs included in the memory module 100, and M =2 ⁿ And n may be an integer of 0, 1, 2, 3, etc. In fig. 2, PORT _1 to PORT _ i represent a plurality of downstream PORT groups, i is a natural number and is the same as the total number of memory cells in the memory module 100.

The upstream port set is used for connecting a memory controller, so as to implement interconnection between the memory module 100 and the memory controller. The uplink port set includes a plurality of pins, such as a data line pin, a control line pin, and an address line pin, which are respectively in one-to-one correspondence with signal pins of the memory controller facing the memory module 100. Optionally, the interface standard followed by the upstream port group may be the same as the interface standard followed by the memory controller to improve the degree of adaptation between the ports. Optionally, the interface standard compliant with the upstream port set and the memory controller may be, but is not limited to, the JTAG standard.

The plurality of downlink port sets are used for connecting the memory granules included in each RANK in the memory module 100, so as to implement interconnection between the memory granules included in each RANK. One downstream port group corresponds to one memory granule. Each downlink port group also comprises a plurality of pins such as a data line pin, a control line pin, an address line pin and the like, which are respectively in one-to-one correspondence with the signal pins of the corresponding memory particles. Optionally, the interface standard complied with by each downstream port group may be the same as the interface standard complied with by the corresponding memory granule. Alternatively, the interface standard compliant with the downstream port set and the memory granule may be, but is not limited to, the JTAG standard.

The control unit is mainly configured to provide a virtual memory space adapted to the bit width L of the memory controller to the memory controller based on at least one memory block included in the memory module 100, so as to implement memory expansion.

For example, when the memory controller accesses the first RANK in the memory module 100, the control unit provides a virtual memory space adapted to the bit width L of the memory controller to the memory controller through mapping of the data bit width, so as to implement memory expansion. Wherein the bit width of the virtual memory space is L2, and L = L2 × N, L2 is satisfied<L1. L2 is a positive integer, generally L2=2 ^m And m is a positive integer. For example, L2 can be any number of bits less than L1 among the number of bits supported by the memory grain process such as 2, 4, etc. The data bit width mapping for the first RANK effectively maps the first RANK comprising N memory grains with bit width L1 to a virtual RANK comprising N memory grains with bit width L2.

Under the condition that the bit width of the memory controller is L, based on the switch chip provided in this embodiment, the maximum number N = L/L2 of memory granules that can be included in one RANK in the memory module 100, because L2 is smaller than L1, compared with the prior art, the number of memory granules that can be included in each RANK is increased, and under the condition that the bit width L1 of the memory granules is not changed, the memory capacity is increased. For example, if the bit width L =72bit of the memory controller, the bit width of the memory granule =8bit, and the bit width L2=2bit of the virtual memory space, a RANK can be obtained by the processing method in the prior art and can include at most 72/8=9 memory granules; based on the switch chip provided in this embodiment, one RANK of the memory module 100 may include 72/2=36 memory grains at most. This means that, for the same memory controller, the memory module of the prior art can support a RANK comprising 9 memory granules at most, while based on the switch chip of the present embodiment, the memory module 100 can support a RANK comprising 36 memory granules, which greatly expands the memory capacity.

For example, the process of the memory controller accessing the first RANK in the memory module 100, the process of the control unit providing the virtual memory space adapted to the bit width L of the memory controller to the memory controller through mapping of the data bit width mainly includes: for a specific description, reference may be made to the foregoing embodiments for describing the memory module, and details are not repeated herein.

In some exemplary embodiments, another implementation structure of a switch chip is shown in fig. 3, and includes: the system comprises a control unit, an uplink port group and a plurality of downlink port groups, wherein the control unit mainly comprises: the device comprises a port virtual module, an addressing module and a mapping table module. The functions of the uplink port group and the plurality of downlink port groups may be referred to in the foregoing embodiments, and are not described herein again. In this embodiment, the functions of the port virtual module, the addressing module, and the mapping table module are mainly described.

The port virtual module is mainly used for providing a virtual memory space adapted to a bit width L of the memory controller to the memory controller through mapping of a data bit width in a process that the memory controller accesses the memory module 100, thereby realizing memory expansion. The process of the port virtual module performing the data bit width mapping during the process of the memory controller accessing the memory module 100 may refer to the description of the foregoing embodiments, and is not described herein again.

The addressing module is mainly used for forming an addressing mapping relation between bit width L1 and bit width L2 corresponding to each RANK. The process of the addressing module for forming the addressing mapping relation between the bit width L1 and the bit width L2 corresponding to each RANK is the same, and the difference is that: the addressing mapping relation between the bit width L1 and the bit width L2 corresponding to different RANKs has different contents.

Taking the addressing mapping relationship between the bit width L1 and the bit width L2 corresponding to the first RANK as an example, the addressing module may perform serial addressing on N memory grains in the first RANK to obtain an addressing sequence; then, splitting the memory address in the addressing sequence into L1/N/L2 address segments, wherein the memory address in each address segment belongs to an address adaptive to the bit width L2; then dividing the L1N/L2 address segments into N address groups, wherein each group comprises L1/L2 address segments; and finally, establishing a mapping relation between the addressing sequence and the N address groups as an addressing mapping relation between the bit width L1 and the bit width L2 corresponding to the first RANK.

Alternatively, the addressing module may divide address segments belonging to the same memory granule among the L1 × N/L2 address segments into one address group, thereby dividing the L1 × N/L2 address segments into N address groups. Of course, other grouping schemes may be used in addition to this grouping scheme.

Correspondingly, the mapping table module is mainly used for storing the addressing mapping relationship between the bit width L1 and the bit width L2 corresponding to each RANK. Optionally, the addressing module may write an addressing mapping relationship between the bit width L1 and the bit width L2 corresponding to each RANK into the mapping table module.

Further optionally, as shown in fig. 3, the switch chip further includes: and a configuration unit. The configuration unit supports a user to configure the memory module 100. For example, the configuration unit may configure parameters such as bit width L1, bit width L2, and the number N of memory granules included in each RANK in response to the configuration instruction.

Further optionally, as shown in fig. 3, the switch chip further includes: and a plurality of port driving units corresponding to the plurality of downstream port groups one to one. In this embodiment, considering that the number of the downlink port groups is increased, in order to implement compatibility with the memory controller, the port driving unit is provided for each downlink port group, so that each downlink port group can be normally driven, and the memory controller can successfully access the expanded memory module 100 with the original power. For the port virtual module of the control unit, the port virtual module may be connected to each downlink port group through the port driver module corresponding to each downlink port group.

It should be noted that the switch chips provided in the above embodiments are all applicable to the memory module 100.

Furthermore, in addition to the memory module 100 and the switch chip, the embodiment of the present application further provides a memory access method suitable for the memory module 100. As shown in fig. 4, an exemplary memory access method includes:

401. according to a bit width mapping relation between a bit width L corresponding to a first memory block (RANK) in the memory module and a bit width L2, splitting a data signal with a bit width L output by a memory controller into N downlink data signals with a bit width L2.

402. According to an addressing mapping relation between a bit width L1 and a bit width L2 corresponding to the first RANK, N downlink data signals with the bit width L2 are spliced into K1 data signals with the bit width L1.

403. Writing K1 data signals with L1 bit width into K1 memory grains of a first RANK; wherein, L is a bit width of the memory controller, L1 is a bit width of the memory granules included in each RANK in the memory module, N is a number of the memory granules included in each RANK in the memory module, and L = L2 × N, L2< L1, K1< = N, and L1, L2, K1, N are positive integers.

The embodiment shown in fig. 4 mainly describes a general process of the memory controller writing data to the memory module, and the detailed flow refers to the description of the foregoing implementation. In this embodiment, the K1 memory granules in the first RANK may be selected by a memory write command issued by the memory controller.

The memory controller can write data into the memory module through the switching chip, and can read data from the memory module through the switching chip. As shown in fig. 5, another exemplary memory access method includes:

501. k2 data signals with a bit width L1 are read from K2 memory grains of a first memory block (RANK) in the memory module.

502. According to an addressing mapping relation between a bit width L1 and a bit width L2 corresponding to a first RANK, splitting K2 data signals with a bit width L1 into N groups of uplink data signals with a bit width L2, wherein each group comprises L1/L2 uplink data signals with a bit width L2.

503. Combining N groups of uplink data signals with the bit width L2 into L1/L2 data signals with the bit width L according to the bit width mapping relation between the bit width L corresponding to the first RANK and the bit width L2, and sequentially outputting the data signals to a memory controller; wherein L is a bit width of the memory controller, L1 is a bit width of memory granules included in each RANK in the memory module, N is a number of memory granules included in each RANK in the memory module, and L = L2 × N, L2< L1, K2< = N, and L1, L2, K2, and N are positive integers.

The embodiment shown in fig. 5 mainly describes the general process of the memory controller reading data from the memory module, and the detailed flow refers to the description of the foregoing implementation. In this embodiment, the K2 memory granules in the first RANK may be selected by a memory read command issued by the memory controller.

In some embodiments, before writing data to or reading data from the first RANK, the N memory grains in the first RANK may be serially addressed to obtain an addressing sequence; dividing the memory address in the addressing sequence into L1/N/L2 address segments, wherein the memory address in each address segment belongs to an address adaptive to the bit width L2; dividing L1 × N/L2 address segments into N address groups; and establishing a mapping relation between the addressing sequence and the N address groups as an addressing mapping relation between bit width L1 and bit width L2 corresponding to the first RANK.

Alternatively, in the above process, the address segments belonging to the same memory granule in the L1 × N/L2 address segments may be divided into one address group, so that the L1 × N/L2 address segments are divided into N address groups.

In some embodiments, the memory module supports configuration operations. Based on this, before serial addressing is performed on N memory granules in the first RANK to obtain an addressing sequence, the bit width L1, the bit width L2, and the number N of memory granules included in each RANK may be configured according to the configuration instruction, so as to provide parameters required for forming an addressing mapping relationship between the bit width L1 and the bit width L2.

In some embodiments, the memory module includes a RANK. Based on this, it may be directly determined that the RANK included in the memory module is the first RANK, and then the write operation shown in fig. 4 and/or the read operation shown in fig. 5 may be performed on the first RANK.

In other embodiments, the memory module includes two or more RANKs. In these embodiments, a number may be set for each RANK, the numbers of different RANKs are different, and a RANK number and memory address range mapping table is pre-established, where the memory address range corresponding to each RANK is stored in the mapping table, the different RANKs correspond to different memory address ranges, and the sum of the memory address ranges corresponding to all the RANKs included in the memory module forms an addressing range of the memory module. Based on this, when the memory controller needs to write data into the memory module 100 or read data from the memory module 100, the RANK number and the memory address range mapping table may be queried according to the memory address that is output by the memory controller and is adapted to the bit width L2, so as to obtain the first RANK number; from among the at least one RANK, the RANK identified by the first RANK number is determined as the first RANK, and then the write operation shown in fig. 4 and/or the read operation shown in fig. 5 is performed with respect to the first RANK. For example, the memory address output by the memory controller and adapted to the bit width L2 may be matched in each memory address range in the mapping table, and then the RANK number corresponding to the memory address range in matching, that is, the first RANK number, may be obtained.

It should be noted that the execution subjects of the steps of the methods provided in the above embodiments may be the same device, or different devices may be used as the execution subjects of the methods. For example, the execution subjects of steps 401 to 403 may be device a; for another example, the execution subject of steps 401 and 402 may be device a, and the execution subject of step 403 may be device B; and so on.

In addition, in some of the flows described in the above embodiments and the drawings, a plurality of operations are included in a specific order, but it should be clearly understood that the operations may be executed out of the order presented herein or in parallel, and the sequence numbers of the operations, such as 401, 402, etc., are merely used to distinguish various operations, and the sequence numbers themselves do not represent any execution order. Additionally, the flows may include more or fewer operations, and the operations may be performed sequentially or in parallel. It should be noted that, the descriptions of "first", "second", etc. in this document are used for distinguishing different messages, devices, modules, etc., and do not represent a sequential order, nor limit the types of "first" and "second" to be different.

Furthermore, in addition to the memory module 100, the switch chip and the memory access method, an embodiment of the present application further provides an electronic device. As shown in fig. 6, the electronic device includes the memory module 100, the memory controller 200 and the processor 300 provided in the above embodiments. The processor 300 accesses the memory module 100 through the memory controller 200.

Optionally, the memory controller 200 is integrated with the processor 300. In the process of accessing the memory module 100 by the processor 300 through the memory controller 200, the processing logic of the processor 300 and the memory controller 200 are the same as that of the prior art, and are not described herein again. The processing logic of the memory module 100 can refer to the description of the foregoing embodiments, and is not described herein again.

Alternatively, the electronic device may be a server, a terminal device, an in-vehicle device, or the like. The server may be a conventional server, a cloud host, a virtual center, or the like. The terminal equipment can be a smart phone, a personal computer, a desktop computer, a tablet computer and the like.

Further, according to different implementation forms of the electronic device, as shown in fig. 6, the electronic device may further include at least one of the following components: communication component 400, display 500, power component 600, audio component 700, and the like. Only some of the components are schematically shown in fig. 6, and the electronic device is not meant to include only the components shown in fig. 6.

The communication component 400 in fig. 6 may be configured to facilitate wired or wireless communication between the device to which the communication component 400 belongs and other devices. The device to which the communication component 400 belongs may access a wireless network based on a communication standard, such as WiFi,2G or 3G, or a combination thereof. In an exemplary embodiment, the communication component 400 receives a broadcast signal or broadcast related information from an external broadcast management system via a broadcast channel. In an exemplary embodiment, the communication component 400 further includes a Near Field Communication (NFC) module to facilitate short-range communications. For example, the NFC module may be implemented based on Radio Frequency Identification (RFID) technology, infrared data association (IrDA) technology, ultra Wideband (UWB) technology, bluetooth (BT) technology, and other technologies.

The display 500 in fig. 6 may include a screen, which may include a Liquid Crystal Display (LCD) and a Touch Panel (TP). If the screen includes a touch panel, the screen may be implemented as a touch screen to receive an input signal from a user. The touch panel includes one or more touch sensors to sense touch, slide, and gestures on the touch panel. The touch sensor may not only sense the boundary of a touch or slide action, but also detect the duration and pressure associated with the touch or slide operation.

The power supply assembly 600 in fig. 6 provides power to the various components of the device to which the power supply assembly 600 belongs. The power components 600 may include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power for the devices to which the power components belong.

The audio component 700 in fig. 6 is configured to output and/or input an audio signal. For example, the audio component includes a Microphone (MIC) configured to receive an external audio signal when the device to which the audio component 700 belongs is in an operating mode, such as a call mode, a recording mode, and a voice recognition mode. The received audio signal may further be stored in a memory or transmitted via the communication component 400. In some embodiments, the audio assembly 700 further comprises a speaker for outputting audio signals.

As will be appreciated by one skilled in the art, embodiments of the present invention may be provided as a method, system, or computer program product. Accordingly, the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present invention may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.

The present invention is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

In a typical configuration, a computing device includes one or more processors (CPUs), input/output interfaces, network interfaces, and memory.

The memory may include forms of volatile memory in a computer readable medium, random Access Memory (RAM) and/or non-volatile memory, such as Read Only Memory (ROM) or flash memory (flash RAM). Memory is an example of a computer-readable medium.

Computer-readable media, including both non-transitory and non-transitory, removable and non-removable media, may implement information storage by any method or technology. The information may be computer readable instructions, data structures, modules of a program, or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static Random Access Memory (SRAM), dynamic Random Access Memory (DRAM), other types of Random Access Memory (RAM), read Only Memory (ROM), electrically Erasable Programmable Read Only Memory (EEPROM), flash memory or other memory technology, compact disc read only memory (CD-ROM), digital Versatile Discs (DVD) or other optical storage, magnetic cassettes, magnetic tape magnetic disk storage or other magnetic storage devices, or any other non-transmission medium that can be used to store information that can be accessed by a computing device. As defined herein, computer readable media does not include transitory computer readable media (transmyedia) such as modulated data signals and carrier waves.

It should also be noted that the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising a … …" does not exclude the presence of another identical element in a process, method, article, or apparatus that comprises the element.

The above description is only an example of the present application and is not intended to limit the present application. Various modifications and changes may occur to those skilled in the art to which the present application pertains. Any modification, equivalent replacement, improvement or the like made within the spirit and principle of the present application shall be included in the scope of the claims of the present application.

Claims

1. A memory module, comprising: the memory device comprises at least one memory block and an exchange chip, wherein each memory block comprises N memory particles with a bit width of L1;

the control unit is used for: in the process of accessing the at least one memory block, mapping data bit width based on a bit width mapping relationship between bit width L and bit width L2 and an addressing mapping relationship between bit width L1 and bit width L2 corresponding to the at least one memory block, so as to provide a virtual memory space adapted to bit width L of the memory controller to the memory controller, where the bit width of the virtual memory space is L2, L = L2 × N, L2< L1, and L1, L2, and N are positive integers.

2. The memory module of claim 1, wherein the control unit is specifically configured to:

and in the process that the memory controller accesses a first memory block in the memory module, mapping the data bit width of the first memory block based on the bit width mapping relation between the bit width L and the bit width L2 corresponding to the first memory block and the addressing mapping relation between the bit width L1 and the bit width L2 so as to provide the virtual memory space for the memory controller.

3. The memory module of claim 2, wherein the control unit is specifically configured to:

splitting a data signal with the bit width L output by the memory controller into N downlink data signals with the bit width L2 according to a bit width mapping relation between the bit width L corresponding to the first memory block and the bit width L2;

writing the K1 data signals with the bit width of L1 into K1 memory grains of the first memory block; wherein K1< = N, and K1 is a positive integer.

4. The memory module of claim 2, wherein the control unit is specifically configured to:

reading K2 data signals with L1 bit width from K2 memory grains of the first memory block;

combining the N groups of uplink data signals with the bit width L2 into L1/L2 data signals with the bit width L according to the bit width mapping relation between the bit width L corresponding to the first memory block and the bit width L2, and sequentially outputting the data signals to the memory controller; wherein K2< = N, and K2 is a positive integer.

5. The memory module according to claim 3 or 4, wherein the control unit is further configured to:

serially addressing the N memory particles in the first memory block to obtain an addressing sequence;

splitting the memory address in the addressing sequence into L1 x N/L2 address segments, wherein the memory address in each address segment belongs to an address adaptive to the bit width L2;

dividing the L1 × N/L2 address segments into N address groups;

and establishing a mapping relation between the addressing sequence and the N address groups as an addressing mapping relation between the bit width L1 and the bit width L2.

6. The memory module of claim 5, wherein the control unit is specifically configured to: and dividing address segments belonging to the same memory grain in the L1 × N/L2 address segments into an address group.

7. The memory module according to any of claims 2-4, wherein the control unit is further configured to:

inquiring a memory block number and a memory address range mapping table according to a memory address which is output by the memory controller and is adaptive to the bit width L2 so as to acquire a first memory block number;

and determining the memory block identified by the first memory block number from the at least one memory block as the first memory block.

8. The memory module according to any of claims 1-4, wherein the control unit is further configured to: and configuring the bit width L1, the bit width L2 and the memory granule number N included in each memory block according to the configuration instruction.

9. A switch chip, comprising: the memory control device comprises a control unit, an uplink port group connected with a memory controller and a plurality of downlink port groups correspondingly connected with memory particles in at least one memory block contained in a memory module; the control unit is respectively connected with the uplink port and the plurality of downlink port groups;

the control unit is used for: in the process of accessing the at least one memory block, mapping the data bit width based on the bit width mapping relationship between the bit width L and the bit width L2 corresponding to the at least one memory block and the addressing mapping relationship between the bit width L1 and the bit width L2, so as to provide a virtual memory space adapted to the bit width L of the memory controller for the memory controller, where the bit width of the virtual memory space is L2, L = L2 × N, L2< L1, and L1, L2, and N are positive integers.

10. The switch chip according to claim 9, wherein the control unit is specifically configured to:

11. The switch chip of claim 10, wherein the control unit is specifically configured to:

12. The switch chip of claim 10, wherein the control unit is specifically configured to:

13. The switch chip of claim 11 or 12, wherein the control unit is further configured to:

splitting the memory address in the addressing sequence into L1 × N/L2 address segments, wherein the memory address in each address segment belongs to an address adaptive to the bit width L2;

dividing the L1 × N/L2 address segments into N address groups;

14. The switch chip of any of claims 9-12, further comprising: a plurality of port driving units corresponding to the plurality of downlink port groups one to one; the control unit is respectively connected with the plurality of downlink port groups through the plurality of port driving units.

15. An electronic device, comprising: the memory module, memory controller and processor of any of claims 1-8; the processor accesses the memory module through the memory controller.

16. A memory access method, adapted to a switch chip in a memory module, where the memory module further includes at least one memory block, each memory block includes N memory granules with a bit width of L1, the switch chip is connected to a memory controller through an uplink port group included in the switch chip, and is correspondingly connected to each memory granule in the at least one memory block through a plurality of downlink port groups included in the switch chip, and the method includes:

in the process of accessing a first memory block in the memory module, splitting a data signal with a bit width of L output by a memory controller into N downlink data signals with a bit width of L2 according to a bit width mapping relation between the bit width L corresponding to the first memory block in the memory module and the bit width L2;

17. The method of claim 16, further comprising:

according to the addressing mapping relation between the bit width L1 and the bit width L2, splitting the K2 data signals with the bit width L1 into N groups of uplink data signals with the bit width L2, wherein each group comprises L1/L2 uplink data signals with the bit width L2;

combining the N groups of uplink data signals with the bit width L2 into L1/L2 data signals with the bit width L according to the bit width mapping relation between the bit width L and the bit width L2, and sequentially outputting the data signals to the memory controller; wherein K2< = N, and K2 is a positive integer.

18. The method as claimed in claim 16, wherein before according to the addressing mapping relationship between bit width L1 and bit width L2 corresponding to the first memory block, the method further comprises:

dividing the L1/N/L2 address segments into N address groups;

and establishing a mapping relation between the addressing sequence and the N address groups as an addressing mapping relation between bit width L1 and bit width L2 corresponding to the first memory block.

19. The method of claim 18, wherein the dividing the L1 x N/L2 address segments into N address groups comprises:

and dividing address segments belonging to the same memory grain in the L1 × N/L2 address segments into an address group.

20. The method of claim 19, wherein prior to serially addressing the N memory grains in the first memory block to obtain an addressing sequence, the method further comprises:

and configuring the bit width L1, the bit width L2 and the memory granule number N included in each memory block according to the configuration instruction.

21. The method according to any of claims 16-20, wherein before splitting the data signal with bit width L into a downstream data signal with bit width L2, the method further comprises:

22. A memory access method, adapted to a switch chip in a memory module, where the memory module further includes at least one memory block, each memory block includes N memory granules with a bit width of L1, the switch chip is connected to a memory controller through an uplink port group included in the switch chip, and is correspondingly connected to each memory granule in the at least one memory block through a plurality of downlink port groups included in the switch chip, and the method includes:

reading K2 data signals with L1 bit width from K2 memory granules of a first memory block in the memory module in the process of accessing the first memory block in the memory module;

combining the N groups of uplink data signals with the bit width L2 into L1/L2 data signals with the bit width L according to the bit width mapping relation between the bit width L corresponding to the first memory block and the bit width L2, and sequentially outputting the data signals to a memory controller; wherein, L = L2N, L2< L1, K2< = N, and L1, L2, K2, N are all positive integers.