CN109768790B - SOC multi-voltage-domain input processing circuit - Google Patents
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- CN109768790B CN109768790B CN201910256889.2A CN201910256889A CN109768790B CN 109768790 B CN109768790 B CN 109768790B CN 201910256889 A CN201910256889 A CN 201910256889A CN 109768790 B CN109768790 B CN 109768790B
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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Abstract
The invention discloses an SOC multi-voltage-domain input processing circuit, which comprises a register unit and an input processing unit, wherein the register unit comprises inverters INV1 and INV2 which are connected in series, the input processing unit comprises more than two input processing circuits, the output end of at least one input processing circuit is connected with the output end of the inverter INV1, the output ends of the other input processing circuits are connected with the output end of the inverter INV2, so that the output VOUT of the SOC multi-voltage-domain input processing circuit is formed, and the VOUT is connected with the input end of the inverter INV 1; the input processing circuit processes the input signal, and when the input signal is in a high level, the input processing circuit outputs a low level; the output priorities of the inverters INV1 and INV2 are lower than the input processing circuit, and when the output of the inverter INV1 is inconsistent with the output of the input processing circuit connected with the inverter INV1, the output of the input processing circuit is preferentially supplied to the inverter INV2, and the inverter INV2 and the input processing circuit thereof are vice versa. The invention can effectively solve the processing problem of a plurality of voltage domains.
Description
Technical Field
The invention belongs to the technical field of chips, and particularly relates to an SOC multi-voltage domain input processing circuit.
Background
In an SOC (System on Chip) Chip, a plurality of voltage domains inside and outside the Chip are often controlled and coexist, and at this time, the plurality of voltage domains of the Chip need to be managed, and a method for processing a plurality of voltage signals in the prior art is as follows: each voltage domain is converted into the same voltage domain separately and then concentrated for logic processing. However, for some analog control signals, the voltage fluctuates within a certain range, and in this way, the P/N transistors input into the CMOS are turned on simultaneously, and thus, larger static power consumption is generated. And problems are more likely to occur when signals in the voltage domain are needed to control the self voltage domain to be closed. There is a need for an effective solution to this problem.
Disclosure of Invention
1. Problems to be solved
Aiming at the problem of inconvenient control of multiple voltage domains in the existing SOC chip, the invention provides an SOC multiple voltage domain input processing circuit.
2. Technical proposal
In order to solve the problems, the technical scheme adopted by the invention is as follows: the SOC multi-voltage-domain input processing circuit comprises a register unit and an input processing unit, wherein the register unit comprises inverters INV1 and INV2 connected in series, the input processing unit comprises more than two input processing circuits, the output end of at least one input processing circuit is connected with the output end of the inverter INV1, the output ends of the other input processing circuits are connected with the output end of the inverter INV2, so that the output VOUT of the SOC multi-voltage-domain input processing circuit is formed, and the VOUT is connected with the input end of the inverter INV 1;
The input processing circuit processes an input signal, and when the input signal is at a high level, the input processing circuit outputs a low level; the output priority of the inverters INV1 and INV2 is lower than that of the input processing circuit, when the output of the inverter INV1 is inconsistent with the output of the input processing circuit connected to the inverter INV1, the output information of the input processing circuit is preferentially output to the inverter INV2, and when the output of the inverter INV2 is inconsistent with the output of the input processing circuit connected to the inverter INV2, the output signal of the input processing circuit is preferentially output as VOUT. That is, when the inverter INV1 outputs a high level and the input processing circuit NA1 outputs a low level, the input terminal of the inverter INV2 is entered to be a low level; when the inverter INV2 outputs a high level, the input processing circuit NB1 outputs a low level, and VUOT outputs a low level.
The specific number of the input processing circuits can be determined according to the number of different voltage domains existing in the SOC chip system, a plurality of voltages in the SOC are respectively connected with an input end SET of the input processing circuit NA1 or an input end CLR of the input processing circuit NA1, when the voltage input is carried out at the SET end, the input processing circuit NA1 outputs a low level, and the output VOUT is a high level after passing through the inverter INV 2; when the voltage input is provided at the CLR terminal, the input processing circuit NA1 outputs a low level, and the direct output VOUT is a low level. The invention can conveniently realize that a plurality of voltage domain signals are converted into the same voltage domain signal for unified processing, and is particularly suitable for processing low-speed reset signals.
Further, the circuit also comprises a reset circuit, wherein the output end of the reset circuit is connected with the input end SET or CLR of one of the input processing circuits. When the reset circuit is used, the output end of the reset unit is connected to the input end of a certain input processing circuit, the specific connection SET or CLR can be determined according to the actual condition of the circuit, the reset circuit outputs a low-level signal to be connected to the input end SET of the input processing circuit NA1 at the moment of power-on of the whole system, the input end SET of the input processing circuit receives the low-level signal and then processes the low-level signal to output a low-level signal, and the low-level signal passes through the inverter INV2 and then outputs a high-level signal. If the reset circuit is connected to the input terminal CLR of the input processing circuit NB1, a low level signal is finally output because an inverter is not required. The reset circuit is mainly used for resetting the system and avoiding abnormal operation of the system during starting.
Further, the reset circuit includes a resistor R1, a capacitor C1 and an inverting amplifier INV3, where one end of the resistor R1 is connected to the voltage, the other end is connected to one end of the capacitor C1, the other end of the capacitor C1 is grounded, the connection between the resistor R1 and the capacitor C1 is connected to the input end of the inverter INV3, and the output end of the inverter INV3 is connected to the input end SET or CLR of the input processing circuit.
Further, the register unit further comprises a delay filter circuit, wherein the input end of the delay filter circuit is connected with the output end of the second inverter, and the output end of the delay filter circuit is the output VOUT of the SOC multi-voltage domain input processing circuit. The delay filter circuit can realize delay and filtering of signals and ensure the accuracy of output signals.
Further, the delay filter circuit includes inverters INVA, INVB and a capacitor C2, where the inverters INVA, INVB are sequentially connected in series, one end of the capacitor C1 is connected at the serial connection position of the inverters INVA, the other end of the capacitor C2 is grounded, the input end of the inverter INV is connected with the output end of the inverter INV2, and the output end of the inverter INVB is used as the output VOUT of the SOC multi-voltage domain input processing circuit.
Further, the input processing circuit is an NMOS tube, the source electrode of the NMOS tube is grounded, the drain electrode of the NMOS tube is the output end of the input processing circuit, and the grid electrode of the NMOS tube is the input end of the input processing circuit.
Further, the input processing circuit comprises two NMOS tubes NC1 and ND1 connected in series, wherein sources of the NMOS tubes NC1 and ND1 are connected with each other and then grounded, a grid electrode is connected with the grid electrode, a drain electrode of the NMOS tube NC1 is an output end of the input processing circuit, and a grid electrode of the NMOS tube NC1 is an input end of the input processing circuit. In order to avoid false triggering caused by low starting voltage of the NMOS tube, the two NMOS tubes NC1 and ND1 are connected in series, so that the starting voltage is increased to be more than 2 x VTH, and the accuracy of the whole circuit is improved.
Further, the inverter is a NOT gate composed of a PMOS tube and an NMOS tube.
3. Advantageous effects
(1) The invention can realize that a plurality of voltage domain signals are converted into the same voltage domain signal for processing;
(2) The invention has simple structure, reasonable design and easy manufacture.
Drawings
FIG. 1 is a circuit diagram of a register cell circuit and an input processing cell circuit of the present invention;
FIG. 2 is a circuit diagram of a reset unit circuit of the present invention;
fig. 3 is a circuit diagram of the internal structure of the inverter of the present invention;
FIG. 4-1 is a schematic diagram of one embodiment of a switching circuit of the present invention;
FIG. 4-2 is a schematic diagram of a second embodiment of the switching circuit of the present invention;
Fig. 5 is a circuit diagram of a delay filter circuit of the present invention.
Detailed Description
The invention is further described below in connection with specific embodiments.
As shown in FIG. 1, the SOC multi-voltage-domain input processing circuit comprises inverters INV1 and INV2, a DELAY filter circuit Delay BUFF and an input processing unit, wherein the inverters INV1 and INV2 and the DELAY filter circuit Delay BUFF are sequentially connected in series, and an output signal VOUT of the DELAY filter circuit Delay BUFF is connected with an input end of the inverter INV 1at the same time to form a register with filtering processing. The input processing unit includes more than two input processing circuits, at least one of which has its output terminal connected to the output terminal of the inverter INV1, which is designated as input processing circuit NA1 … NAn, and the other input processing circuits have its output terminal connected to the output terminal of the inverter INV2, which is designated as input processing circuit NB1 … NBn. Each input processing circuit is composed of an NMOS tube connected to the ground, the output of the inverter INV1 is connected to the drain of the NMOS tube in the input processing circuit NA1 … NAn, and the output of the inverter INV2 is connected to the drain of the NMOS tube of the input processing circuit NB1 … NBn. SET1 … SETn is a gate switch control signal input to the processing circuit NA1 … NAn, CLR1 … CLRn is a gate switch control signal input to the processing circuit NB1 … NBn, and the corresponding NMOS is controlled by the gate switch control signal, and the turn-on voltage of the NMOS transistor is determined by the threshold voltage VTH thereof.
When the input end of the input processing circuit NA1 … NAn is provided with a strong pull-down and the NMOS tube is conducted, VOUT outputs '1'; when the input processing circuit NB1 … NBn is input with strong pull-down and the NMOS tube is conducted, VOUT outputs '0'; when the input processing circuit NA1 … NAn and the input processing circuit NB1 … NBn have a strong pull-down at the same time, the signal of the input processing circuit NB1 … NBn is preferentially output and VOUT outputs "0" because the priority of the inverter INV2 is lower than that of the input processing circuit NB1 … NBn; when neither the input processing circuit NA1 … NAn nor the input processing circuit NB1 … NBn is strongly pulled down, the output is kept unchanged.
As shown in fig. 2, the reset circuit is composed of a resistor R1, a capacitor C1, and an inverter INV3, and an output terminal of the reset circuit is connected to an input terminal SET or CLR of the input processing circuit NA1 … NAn or NB1 … NBn, which outputs a reset "1" signal by power-on delay. Specifically, whether the input terminal SET to the processing unit circuit NA1 … NAn or the input terminal CLR to the processing circuit NB1 … NBn is connected can be determined according to different circuits. When the system is started, the system may not be started normally due to various reasons, the output signal POR of the reset circuit is 1, the POR is connected with the gate control signal of the corresponding NMOS tube of the processing unit circuit, so that the NMOS tube is turned on, the drain electrode of the NMOS tube outputs the level signal to the inverter INV2 or directly to the DELAY filter circuit DELAY, and the output voltage VOUT is 1 or 0. The access of the reset circuit can avoid abnormal operation when the system is started.
As shown in fig. 3, the inverter is a not gate formed by a PMOS transistor and an NMOS transistor, and in order to ensure that the output priority of the inverter INV1 is lower than the output of the input processing circuit NA1 … NAn in implementation, the output priority of the inverter INV2 is lower than the output of the input processing circuit NB1 … NBn, that is, when the output of the inverter INV1 is inconsistent with the output of the input processing circuit connected to the inverter INV1, the output information of the input processing circuit NA1 … NAn is preferentially output to the inverter INV2, and when the output of the inverter INV2 is inconsistent with the output of the input processing circuit NB1 … NBn connected to the inverter INV2, the output signal of the input processing circuit is preferentially regarded as the output of VOUT. The inverters with different driving strengths can be obtained by respectively setting the length-width ratio of the PMOS tube and the NMOS tube or connecting a resistor at the common output end of the PMOS tube and the NMOS tube. When the inverter INV1 outputs a high level and the input processing circuit NA1 outputs a low level, the input end of the inverter INV2 is entered to be at a low level; when the inverter INV2 outputs a high level, the input processing circuit NB1 outputs a low level, and VUOT outputs a low level.
The input processing circuit NA1 … NAn or NB1 … NBn of the invention can adopt two circuit structures shown in FIG. 4-1 and FIG. 4-2, wherein FIG. 4-1 is a circuit which consists of an NMOS tube NC1 and has a normal starting voltage threshold value, and the starting voltage is VTH; in order to avoid false triggering caused by low starting voltage of the NMOS transistor, the threshold voltage can be increased to avoid false triggering. As shown in fig. 4-2, an NMOS tube ND1 is connected in series under the NMOS tube NC1, and the sources of the NMOS tubes NC1 and ND1 are connected with each other, and the gates are connected with each other, so that the turn-on voltage is increased to above 2 x vth, and false triggering is effectively avoided.
As shown in fig. 5, the DELAY filter circuit DELAY BUFF of the present invention is composed of inverters INVA and INVB and a capacitor C2, the inverters INVA and INVB are connected in series, one end of the capacitor C2 is connected in series, and the other end of the capacitor C2 is grounded to realize DELAY and filtering of an input signal. In this circuit, the driving strength of the inverter INVA is weak, so that there is enough time to charge the capacitor C2, which plays a role of delay, and if the driving strength of the inverter INVA is strong, the capacitor C2 is charged fully instantaneously, which cannot play a role of delay. The driving strength of the inverter INVB is strong, so that when the output VOUT of the INVB is connected to the inverter INV1, the output of the inverter INVB is only accepted regardless of the original state of the inverter INV1, and the competition between the inverters INV1 and INVB is avoided. In the present invention, the inverters INV1, INV2 and INVA are all inverters with weaker driving strength, while the INVB has stronger driving strength.
The foregoing has been described schematically the invention and embodiments thereof, which are not limiting, but are capable of other specific forms of implementing the invention without departing from its spirit or essential characteristics. The drawings are also merely illustrative of one embodiment of the invention, the actual construction is not limited thereto, and any reference signs in the claims shall not be construed as limiting the scope of the claims concerned. Therefore, if one of ordinary skill in the art is informed by this disclosure, a structural manner and an embodiment similar to the technical scheme are not creatively designed without departing from the gist of the present invention, and all the structural manners and the embodiment are considered to be within the protection scope of the present patent. In addition, the word "comprising" does not exclude other elements or steps, and the word "a" or "an" preceding an element does not exclude the inclusion of a plurality of such elements. The various elements recited in the product claims may also be embodied in software or hardware. The terms first, second, etc. are used to denote a name, but not any particular order.
Claims (5)
1. An SOC multi-voltage domain input processing circuit, characterized in that: the system comprises a register unit, an input processing unit and a reset circuit, wherein the register unit comprises inverters INV1 and INV2 which are connected in series, the input processing unit comprises more than two input processing circuits, the output end of at least one input processing circuit is connected with the output end of the inverter INV1, the output ends of the other input processing circuits are connected with the output end of the inverter INV2, so that the output VOUT of the SOC multi-voltage domain input processing circuit is formed, and the VOUT is connected with the input end of the inverter INV 1;
The input processing circuit processes an input signal, and when the input signal is at a high level, the input processing circuit outputs a low level; the output priority of the inverters INV1 and INV2 is lower than that of the input processing circuit, when the output of the inverter INV1 is inconsistent with the output of the input processing circuit connected with the inverter INV1, the output information of the input processing circuit is preferentially output to the inverter INV2, and when the output of the inverter INV2 is inconsistent with the output of the input processing circuit connected with the inverter INV2, the output signal of the input processing circuit is preferentially output as VOUT;
The output end of the reset circuit is connected with the input end of one of the input processing circuits; the reset circuit comprises a resistor R1, a capacitor C1 and an inverting amplifier INV3, wherein one end of the resistor R1 is connected with voltage, the other end of the resistor R1 is connected with one end of the capacitor C1, the other end of the capacitor C1 is grounded, the connection part of the resistor R1 and the capacitor C1 is connected with the input end of the inverter INV3, and the output end of the inverter INV3 is connected with the input end of the input processing circuit;
The input processing circuit comprises two NMOS tubes NC1 and ND1 which are connected in series, wherein the sources of the NMOS tubes NC1 and ND1 are connected with each other and then grounded, the grid is connected with the grid, the drain electrode of the NMOS tube NC1 is the output end of the input processing circuit, and the grid electrode of the NMOS tube NC1 is the input end of the input processing circuit.
2. The SOC multi-voltage domain input processing circuit of claim 1, wherein: the register unit further comprises a delay filter circuit, wherein the input end of the delay filter circuit is connected with the output end of the inverter INV2, and the output end of the delay filter circuit is the output VOUT of the SOC multi-voltage-domain input processing circuit.
3. The SOC multi-voltage domain input processing circuit of claim 2, wherein: the delay filter circuit comprises inverters INVA and INVB and a capacitor C2, wherein the inverters INVA and INVB are sequentially connected in series, one end of the capacitor C1 is connected to the serial connection position of the inverters INVA and INVB, the other end of the capacitor C2 is grounded, the input end of the inverter INVA is connected with the output end of the inverter INV2, and the output end of the inverter INVB is used as the output VOUT of the SOC multi-voltage-domain input processing circuit.
4. The SOC multi-voltage domain input processing circuit of claim 1, wherein: the input processing circuit is an NMOS tube, the source electrode of the NMOS tube is grounded, the drain electrode of the NMOS tube is the output end of the input processing circuit, and the grid electrode of the NMOS tube is the input end of the input processing circuit.
5. The SOC multi-voltage domain input processing circuit of any of claims 1-4, wherein: the inverter is an NOT gate formed by a PMOS tube and an NMOS tube.
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| CN101394171B (en) * | 2008-10-24 | 2010-08-11 | 华中科技大学 | Static zero-consumption power-on resetting circuit |
| KR101623117B1 (en) * | 2009-03-16 | 2016-05-23 | 삼성전자주식회사 | Logic circuit capable of level shifting |
| CN102130492B (en) * | 2010-07-31 | 2015-05-27 | 华为技术有限公司 | Device and method for selecting power supply |
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| CN102594311A (en) * | 2011-01-11 | 2012-07-18 | 快捷韩国半导体有限公司 | Semiconductor device including power-on reset circuit |
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