CN109768711B - A synchronous rectification control circuit and method - Google Patents
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Abstract
Description
技术领域Technical Field
本发明涉及整流整流技术领域，尤其涉及一种同步整流控制电路及方法。The present invention relates to the field of rectification and correction technology, and in particular to a synchronous rectification control circuit and method.
背景技术Background technique
随着对电源效率要求的提高，同步整流技术越来越受到人们的关注，特别是DC/DC低压大电流场合，传统电源系统中副边二极管整流存在较大导通压降损耗，在副边采用MOSFET(即Meta l-Ox ide-Semiconductor Fie l d-Effect Trans i stor缩写，中文为金属氧化物半导体场效应晶体管)代替单纯的二极管整流来降低损耗，提高效率，已经越来越成为一种趋势。With the increasing requirements for power supply efficiency, synchronous rectification technology has attracted more and more attention, especially in DC/DC low-voltage and high-current applications. In traditional power supply systems, there is a large conduction voltage drop loss in the secondary side diode rectification. It has become more and more a trend to use MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) on the secondary side instead of simple diode rectification to reduce losses and improve efficiency.
现有同步整流技术存在以下缺陷：The existing synchronous rectification technology has the following defects:
(1)现有同步整流方式之一，是通过原边跟随副边控制技术，即副边驱动与原边驱动完全同步保持一致，在开关频率高于或等于谐振频率时，理论上可以同开同关即原副边同步实现。但是，当LLC谐振电路中谐振频率高于开关频率时，会存在副边电流较原边驱动提前到零而出现一段平台时间情况，若此时副边驱动还是与原边同步导通、不及时提前断开，会存在原边电流过大甚至损坏开关管的风险。(1) One of the existing synchronous rectification methods is to use the primary side following the secondary side control technology, that is, the secondary side drive is completely synchronized with the primary side drive. When the switching frequency is higher than or equal to the resonant frequency, the primary and secondary sides can be turned on and off at the same time in theory. However, when the resonant frequency in the LLC resonant circuit is higher than the switching frequency, the secondary side current will reach zero earlier than the primary side drive and a platform time will appear. If the secondary side drive is still turned on synchronously with the primary side and is not disconnected in advance, there will be a risk of excessive primary side current or even damage to the switch tube.
(2)现有同步整流方式之二，是采用雅达ORi ng场效应管(也叫MOS管)控制方式，通过电流流过整流二极管产生压降信号来拉通同步整流管的方式，如技术信息2018年第2期文章编号：1009-2552(2018)02-0055-04《G2 50A的LLC拓朴的同步整流电路》，其同步原理电路如图1所示。其工作原理和过程为：当有主回路电流从同步整流MOS管M1的S极(源极)通过体二极管流过D极(漏极)时，会产生VF(约0.7V)压降，这时M1的D极电压低于S极电压，则Q1的左边三极管导通，右边三极管截止，推挽电路输出高电平，M1导通，电流从体二极管转向M1内部RDS(on)[RDS(ON)是场效应管(也叫MOS管)漏极D与源极S之间导通时D、S之间的电阻]；当主回路电流过零反向后，M1的D极电压高于S极电压，这时Q1左边的三极管会截止，右边三极管导通，推挽输出低电平使M1截止，此电路简单，元器件少，成本便宜。(2) The second existing synchronous rectification method is to use the Yada ORi ng field effect tube (also called MOS tube) control method, which generates a voltage drop signal by the current flowing through the rectifier diode to pull through the synchronous rectifier tube, such as the technical information 2018 No. 2 article number: 1009-2552 (2018) 02-0055-04 "G2 50A LLC topology synchronous rectification circuit", and its synchronous principle circuit is shown in Figure 1. Its working principle and process are as follows: when the main circuit current flows from the S pole (source) of the synchronous rectifier MOS tube M1 through the body diode to the D pole (drain), a VF (about 0.7V) voltage drop will be generated. At this time, the D pole voltage of M1 is lower than the S pole voltage, then the left transistor of Q1 is turned on, the right transistor is turned off, the push-pull circuit outputs a high level, M1 is turned on, and the current is transferred from the body diode to the internal RDS (on) of M1 [RDS (ON) is the resistance between the drain D and the source S of the field effect tube (also called MOS tube) when it is turned on]; when the main circuit current passes through zero and reverses, the D pole voltage of M1 is higher than the S pole voltage, then the left transistor of Q1 will be turned off, the right transistor is turned on, and the push-pull output is a low level to turn off M1. This circuit is simple, with few components and low cost.
但是,该电路对保护三极管Q1和二极管D2内部对称模块一致性要求非常高，特别是温度变化不一致时引起Vd电压误导通，同时，由于M1导通时SD(源-漏)极间压降非常小，同步整流驱动控制电路里形成对管的两个三极管并不是彻底地一开一关，实际上当同步整流MOS管M1截止时右边三极管导通，左边完全截止，当同步整流MOS管M1导通时两个三极管都会导通流过电流。电流越大，同步整流MOS管D极电压越低，左边三极管流过的电流就越多，右边流过的电流越少，控制电路输出的驱动信号就越高；因此，存在电流上升时驱动电压高于电流下降时的驱动电压问题。即同步整流MOS管的驱动电压与流过MOS管的电流成正比，负载越大，驱动电压就越高；反之，驱动信号就越低。而驱动电压低，往往伴随着损耗大、效率低的问题。However, the circuit has very high requirements for the consistency of the internal symmetric modules of the protection transistor Q1 and the diode D2, especially when the temperature changes inconsistently, causing the Vd voltage to be mis-conducted. At the same time, since the voltage drop between the SD (source-drain) electrodes is very small when M1 is turned on, the two transistors forming a pair of tubes in the synchronous rectification drive control circuit are not completely turned on and off. In fact, when the synchronous rectification MOS tube M1 is turned off, the right transistor is turned on and the left is completely turned off. When the synchronous rectification MOS tube M1 is turned on, both transistors will be turned on and the current will flow. The larger the current, the lower the D-pole voltage of the synchronous rectification MOS tube, the more current flows through the left transistor, the less current flows through the right, and the higher the drive signal output by the control circuit; therefore, there is a problem that the drive voltage when the current rises is higher than the drive voltage when the current falls. That is, the drive voltage of the synchronous rectification MOS tube is proportional to the current flowing through the MOS tube. The larger the load, the higher the drive voltage; conversely, the lower the drive signal. Low drive voltage is often accompanied by problems of large loss and low efficiency.
另一方面，还由于MOS管封装寄生电感和PCB引线电感的作用，同步整流控制电路检测到的Vsd’(源-漏极)电压在电流增大(由S极往D极为正向流动)时高于理想的Vsd(即不考虑寄生电感和引线电感时)电压，而电流减小时小于理想的Vsd电压。加之由于漏感等寄生电感影响，Vsd'电压常常伴随振铃抖动问题而出现误触发同步整流MOS管导通的风险。On the other hand, due to the effects of the MOS tube package parasitic inductance and the PCB lead inductance, the Vsd' (source-drain) voltage detected by the synchronous rectification control circuit is higher than the ideal Vsd (i.e., when parasitic inductance and lead inductance are not considered) voltage when the current increases (flowing in the forward direction from the S pole to the D pole), and is lower than the ideal Vsd voltage when the current decreases. In addition, due to the influence of parasitic inductance such as leakage inductance, the Vsd' voltage is often accompanied by ringing jitter problems, which may cause the synchronous rectification MOS tube to be turned on by mistake.
因此，该同步整流检测电路存在元器件一致性要求较高问题，同时由于MOS管寄生电感和pcb引线电感而引起驱动电压时高时低造成MOS管导通程度不一致，效率受到较大影响。Therefore, the synchronous rectification detection circuit has the problem of high component consistency requirements. At the same time, due to the parasitic inductance of the MOS tube and the PCB lead inductance, the driving voltage is sometimes high and sometimes low, resulting in inconsistent conduction degree of the MOS tube, and the efficiency is greatly affected.
为了克服上述的不足，我们发明了一种同步整流控制电路及方法。In order to overcome the above-mentioned deficiencies, we have invented a synchronous rectification control circuit and method.
发明内容Summary of the invention
本发明的发明目的在于解决现有同步整流方式中当LLC谐振电路中谐振频率高于开关频率时，存在副边电流较原边驱动提前到零，若此时副边驱动还是与原边同步导通不及时提前断开，会存在原边电流过大甚至损坏开关管的风险，采用雅达ORi ng场效应管控制方式对电路内部对称模块以及元器件的要求非常高、由寄生电感和引线电感引起驱动电压时高时低造成MOS管导通程度不一致、效率受到较大影响的问题。其具体解决方案如下：The purpose of the present invention is to solve the problem that when the resonant frequency in the LLC resonant circuit is higher than the switching frequency, the secondary current reaches zero ahead of the primary drive in the existing synchronous rectification method. If the secondary drive is still synchronously turned on with the primary and is not disconnected in advance, there will be a risk of excessive primary current or even damage to the switch tube. The use of the Yada ORi ng field effect tube control method has very high requirements for the symmetrical modules and components inside the circuit, and the parasitic inductance and lead inductance cause the driving voltage to be high and low, resulting in inconsistent conduction of the MOS tube and a significant impact on efficiency. The specific solution is as follows:
一种同步整流控制电路，包括同步整流电路、第一驱动电路其输出与所述同步整流电路原边连接，第二驱动电路其输出与所述同步整流电路副边连接，CPU控制器与所述第一驱动电路输入连接。还包括一端与所述同步整流电路的原边连接，另一端与所述第二驱动电路的输入连接的同步整流控制器，所述同步整流控制器包括：A synchronous rectification control circuit includes a synchronous rectification circuit, a first drive circuit whose output is connected to the primary side of the synchronous rectification circuit, a second drive circuit whose output is connected to the secondary side of the synchronous rectification circuit, and a CPU controller connected to the input of the first drive circuit. It also includes a synchronous rectification controller having one end connected to the primary side of the synchronous rectification circuit and the other end connected to the input of the second drive circuit, and the synchronous rectification controller includes:
采样电路，其输入端分别与所述同步整流电路原边的谐振电感的两端连接；A sampling circuit, whose input end is respectively connected to the two ends of the resonant inductor of the primary side of the synchronous rectification circuit;
波形提取电路，其输入与所述采样电路输出连接；a waveform extraction circuit, the input of which is connected to the output of the sampling circuit;
整形锁存电路，其输入与所述波形提取电路输出连接；a shaping latch circuit, the input of which is connected to the output of the waveform extraction circuit;
数字逻辑电路，其输入与所述整形锁存电路输出连接，其输出与所述第二驱动电路的输入连接。A digital logic circuit has an input connected to the output of the shaping latch circuit and an output connected to the input of the second driving circuit.
进一步地，所述同步整流电路至少包括第一开关MOS管Q1、第二开关MOS管Q2、谐振电感Lr、第一谐振电容Cr1、第二谐振电容Cr2，位于开关变压器Tx原边的励磁电感Lm、开关变压器Tx、第一同步整流MOS管Q3、第二同步整流MOS管Q4、输出电容Co、输出负载RL。Furthermore, the synchronous rectification circuit at least includes a first switching MOS tube Q1, a second switching MOS tube Q2, a resonant inductor Lr, a first resonant capacitor Cr1, a second resonant capacitor Cr2, an excitation inductor Lm located on the primary side of the switching transformer Tx, a switching transformer Tx, a first synchronous rectification MOS tube Q3, a second synchronous rectification MOS tube Q4, an output capacitor Co, and an output load RL.
第一开关MOS管Q1漏极同时与输入电压源Vin正极和第一谐振电容Cr1一端连接，第一开关MOS管Q1源极同时与第二开关MOS管Q2漏极和谐振电感Lr一端连接，谐振电感Lr另一端同时与励磁电感Lm一端和开关变压器Tx初级同名端连接，励磁电感Lm另一端和开关变压器Tx初级异名端同时与第一谐振电容Cr1另一端和第二谐振电容Cr2一端连接，第二谐振电容Cr2另一端和第二开关MOS管Q2源极以及输入电压源Vin负极同时与原边的地连接。第一开关MOS管Q1栅极和第二开关MOS管Q2栅极分别与所述第一驱动电路的输出连接。The drain of the first switch MOS tube Q1 is connected to the positive electrode of the input voltage source Vin and one end of the first resonant capacitor Cr1 at the same time, the source of the first switch MOS tube Q1 is connected to the drain of the second switch MOS tube Q2 and one end of the resonant inductor Lr at the same time, the other end of the resonant inductor Lr is connected to one end of the excitation inductor Lm and the primary same-name end of the switch transformer Tx at the same time, the other end of the excitation inductor Lm and the primary opposite-name end of the switch transformer Tx are connected to the other end of the first resonant capacitor Cr1 and one end of the second resonant capacitor Cr2 at the same time, the other end of the second resonant capacitor Cr2 and the source of the second switch MOS tube Q2 and the negative electrode of the input voltage source Vin are connected to the primary ground at the same time. The gate of the first switch MOS tube Q1 and the gate of the second switch MOS tube Q2 are respectively connected to the output of the first drive circuit.
开关变压器Tx次级异名端与第一同步整流MOS管Q3漏极连接，开关变压器Tx次级同名端与第二同步整流MOS管Q4漏极连接，开关变压器Tx次级中间抽头同时与输出电容Co和输出负载RL的一端连接，第一同步整流MOS管Q3源极、第二同步整流MOS管Q4源极、输出电容Co和输出负载RL的另一端同时与副边的地连接；第一同步整流MOS管Q3栅极、第二同步整流MOS管Q4栅极分别与所述第二驱动电路的输出连接。The secondary opposite-name end of the switching transformer Tx is connected to the drain of the first synchronous rectifier MOS tube Q3, the secondary same-name end of the switching transformer Tx is connected to the drain of the second synchronous rectifier MOS tube Q4, the secondary middle tap of the switching transformer Tx is simultaneously connected to the output capacitor Co and one end of the output load RL, the source of the first synchronous rectifier MOS tube Q3, the source of the second synchronous rectifier MOS tube Q4, the output capacitor Co and the other end of the output load RL are simultaneously connected to the ground of the secondary side; the gate of the first synchronous rectifier MOS tube Q3 and the gate of the second synchronous rectifier MOS tube Q4 are respectively connected to the output of the second drive circuit.
进一步地，所述采样电路至少包括输入端的电阻R1和R2，电阻R1的另一端同时与运算放大器U1的3脚和电阻R3一端连接，电阻R2的另一端同时与运算放大器U1的4脚和电阻R4一端连接，电阻R4另一端接地，电阻R3另一端与运算放大器U1的输出1脚连接，运算放大器U1的5脚接供电VCC+，运算放大器U1的2脚接供电VCC-。Furthermore, the sampling circuit at least includes resistors R1 and R2 at the input end, the other end of the resistor R1 is connected to pin 3 of the operational amplifier U1 and one end of the resistor R3 at the same time, the other end of the resistor R2 is connected to pin 4 of the operational amplifier U1 and one end of the resistor R4 at the same time, the other end of the resistor R4 is grounded, the other end of the resistor R3 is connected to pin 1 of the output of the operational amplifier U1, pin 5 of the operational amplifier U1 is connected to the power supply VCC+, and pin 2 of the operational amplifier U1 is connected to the power supply VCC-.
进一步地，所述波形提取电路至少包括输入为电容Cf一端与运算放大器U1的输出1脚连接，电容Cf一端与电阻Rf一端连接，电阻Rf另一端接地；电容Cf与电阻Rf组成高通电路。所述高通电路可为一级或多级组成。Furthermore, the waveform extraction circuit at least includes an input, one end of a capacitor Cf is connected to the output 1 pin of the operational amplifier U1, one end of the capacitor Cf is connected to one end of a resistor Rf, and the other end of the resistor Rf is grounded; the capacitor Cf and the resistor Rf form a high-pass circuit. The high-pass circuit can be composed of one stage or multiple stages.
进一步地，所述整形锁存电路至少包括输入为比较器U2的3脚和比较器U3的4脚同时与电阻Rf输出连接，比较器U2的4脚、2脚接地，比较器U2的1脚为输出，比较器U3的3脚、2脚接地，比较器U3的1脚为输出；或者比较器U2和U3的1脚分别连接锁存芯片的输入，锁存芯片的输出连接数字逻辑电路的输入。Furthermore, the shaping latch circuit at least includes inputs of pin 3 of comparator U2 and pin 4 of comparator U3, which are simultaneously connected to the output of resistor Rf, pins 4 and 2 of comparator U2 are grounded, pin 1 of comparator U2 is the output, pins 3 and 2 of comparator U3 are grounded, and pin 1 of comparator U3 is the output; or pins 1 of comparator U2 and U3 are respectively connected to the input of the latch chip, and the output of the latch chip is connected to the input of the digital logic circuit.
进一步地，所述数字逻辑电路至少包括两个触发器U4、U5，输入为触发器U4、U5的3脚分别与比较器U2、U3的1脚连接，输出为触发器U4、U5的5脚。所述触发器为D触发器或JK触发器或异或与D触发器组合或同或与D触发器组合的一种。Furthermore, the digital logic circuit includes at least two triggers U4 and U5, the input of which is the 3rd pin of the triggers U4 and U5 connected to the 1st pin of the comparators U2 and U3 respectively, and the output of which is the 5th pin of the triggers U4 and U5. The trigger is a D trigger or a JK trigger or a combination of an XOR and a D trigger or a combination of an XOR and a D trigger.
一种同步整流控制方法，包括上述一种同步整流控制电路，按照以下步骤执行：A synchronous rectification control method includes the above-mentioned synchronous rectification control circuit and is performed according to the following steps:
步骤1，采样电路实时检测谐振电感Lr两端电压；Step 1, the sampling circuit detects the voltage across the resonant inductor Lr in real time;
步骤2，波形提取电路提取谐振电感Lr瞬态突变冲击波形；Step 2, the waveform extraction circuit extracts the transient sudden change impact waveform of the resonant inductor Lr;
步骤3，整形锁存电路整形锁存为上升沿信号；Step 3, the shaping latch circuit shapes and latches the rising edge signal;
步骤4，数字逻辑电路触发锁存上升沿信号为同步信号；Step 4, the digital logic circuit triggers the latch rising edge signal as a synchronization signal;
步骤5，第二驱动电路驱动放大同步信号，驱动对应同步整流。Step 5: The second driving circuit drives and amplifies the synchronous signal to drive the corresponding synchronous rectification.
综上所述，采用本发明的技术方案具有以下有益效果：In summary, the technical solution of the present invention has the following beneficial effects:
本方案解决了现有同步整流方式中当LLC谐振电路中谐振频率高于开关频率时，存在副边电流较原边驱动提前到零，若此时副边驱动还是与原边同步导通不及时提前断开，会存在原边电流过大甚至损坏开关管的风险，采用雅达ORi ng场效应管控制方式对电路内部对称模块以及元器件的要求非常高、由寄生电感和引线电感引起驱动电压时高时低造成MOS管导通程度不一致、效率受到较大影响的问题。This solution solves the problem that when the resonant frequency in the LLC resonant circuit is higher than the switching frequency in the existing synchronous rectification method, the secondary current reaches zero earlier than the primary drive. If the secondary drive is still synchronously turned on with the primary and is not disconnected in advance, there will be a risk of excessive primary current or even damage to the switch tube. The use of Yada ORi ng field effect tube control method has very high requirements on the symmetrical modules and components inside the circuit, and the driving voltage caused by parasitic inductance and lead inductance is sometimes high and sometimes low, resulting in inconsistent conduction degree of MOS tube and greatly affecting efficiency.
由于LLC谐振电路中，副边电流正比于谐振电流与励磁电流的差值，即输出电流开始和结束的时刻，便是谐振电流与励磁电流相等的时刻，而此时也是谐振电感两端电压发生翻转的时刻。谐振电感电压突变明显，检测可靠，不易引起其他杂散寄生影响，本发明通过提取谐振电感电压瞬态突变信号，作为对应同步整流管的开启和关闭信号；从而避免了采样微弱电流小信号的采样失真，也避免了MOS管脚杂散电感等寄生参数的影响，且本方案无需实时跟随原边驱动，能在全开关频率范围应用，不受开关频率影响，进行实时跟随输出电流的同步控制，实现提高转换效率。特别是在输出短路或轻载模式下优势更为明显。Since the secondary current in the LLC resonant circuit is proportional to the difference between the resonant current and the excitation current, that is, the moment when the output current starts and ends is the moment when the resonant current is equal to the excitation current, and this is also the moment when the voltage across the resonant inductor is reversed. The resonant inductor voltage mutation is obvious, the detection is reliable, and it is not easy to cause other stray parasitic influences. The present invention extracts the transient mutation signal of the resonant inductor voltage as the opening and closing signal of the corresponding synchronous rectifier; thereby avoiding the sampling distortion of the weak current small signal, and also avoiding the influence of parasitic parameters such as the stray inductance of the MOS pin. In addition, this solution does not need to follow the primary side drive in real time, and can be used in the full switching frequency range. It is not affected by the switching frequency, and performs real-time synchronous control of the output current to improve the conversion efficiency. The advantages are more obvious in output short circuit or light load mode.
附图说明BRIEF DESCRIPTION OF THE DRAWINGS
为了更清楚地说明本发明实施例的技术方案，下面将对本发明实施例的描述中所需要使用的附图作简单地介绍。显而易见地，下面描述中的附图仅仅是本发明的一部分实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还能够根据这些附图获得其他的附图。In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments of the present invention. Obviously, the drawings described below are only part of the embodiments of the present invention, and those skilled in the art can obtain other drawings based on these drawings without creative labor.
图1为背景技术中同步原理电路图；FIG1 is a circuit diagram of synchronization principle in the background technology;
图2为本发明一种同步整流控制电路的电路图；FIG2 is a circuit diagram of a synchronous rectification control circuit of the present invention;
图3为本发明的同步整流控制器的电路图；FIG3 is a circuit diagram of a synchronous rectification controller of the present invention;
图4为本发明一种同步整流控制方法的步骤图；FIG4 is a step diagram of a synchronous rectification control method of the present invention;
图5为本发明一种同步整流控制电路的波形图；FIG5 is a waveform diagram of a synchronous rectification control circuit of the present invention;
图6为本发明用于全桥结构的同步整流控制电路的电路图；6 is a circuit diagram of a synchronous rectification control circuit for a full-bridge structure according to the present invention;
图7为JK触发器的电路图；FIG7 is a circuit diagram of a JK flip-flop;
图8为异或与D触发器组合的电路图；FIG8 is a circuit diagram of an XOR and D flip-flop combination;
图9为D触发器的电路图；FIG9 is a circuit diagram of a D flip-flop;
图10为同或与D触发器组合的电路图。FIG10 is a circuit diagram of an XNOR D flip-flop combination.
附图标记说明：Description of reference numerals:
Vgs1-开关MOS管Q1驱动信号；Vgs1- switch MOS tube Q1 drive signal;
Vgs2-开关MOS管Q2驱动信号；Vgs2- switch MOS tube Q2 drive signal;
ILr-谐振电感Lr电流；ILr-resonant inductor Lr current;
ILm-励磁电感Lm电流；ILm-excitation inductance Lm current;
VLr_Samp-谐振电感Lr采样电压；VLr_Samp-resonant inductor Lr sampling voltage;
VLr_Pluse-谐振电感Lr瞬态冲击电压；VLr_Pluse-transient impulse voltage of resonant inductor Lr;
VLr_CP3-同步整流MOS管Q3瞬态冲击上升沿；VLr_CP3- synchronous rectifier MOS tube Q3 transient impact rising edge;
VLr_CP4-同步整流MOS管Q4瞬态冲击上升沿；VLr_CP4- synchronous rectifier MOS tube Q4 transient impact rising edge;
Vgs3-同步整流MOS管Q3驱动信号；Vgs3- synchronous rectifier MOS tube Q3 drive signal;
Vgs4-同步整流MOS管Q4驱动信号；Vgs4- synchronous rectifier MOS tube Q4 drive signal;
IQ3-同步整流MOS管Q3电流；IQ3- synchronous rectifier MOS tube Q3 current;
IQ4-同步整流MOS管Q4电流。IQ4- synchronous rectifier MOS tube Q4 current.
具体实施方式Detailed ways
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。The technical solutions in the embodiments of the present invention will be described clearly and completely below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.
如图2、3所示，一种同步整流控制电路，包括同步整流电路、第一驱动电路其输出与同步整流电路原边连接，第二驱动电路其输出与同步整流电路副边连接，CPU控制器与第一驱动电路输入连接。还包括一端与同步整流电路的原边连接，另一端与第二驱动电路的输入连接的同步整流控制器，同步整流控制器包括：As shown in Figures 2 and 3, a synchronous rectification control circuit includes a synchronous rectification circuit, a first drive circuit whose output is connected to the primary side of the synchronous rectification circuit, a second drive circuit whose output is connected to the secondary side of the synchronous rectification circuit, and a CPU controller connected to the input of the first drive circuit. It also includes a synchronous rectification controller with one end connected to the primary side of the synchronous rectification circuit and the other end connected to the input of the second drive circuit, and the synchronous rectification controller includes:
采样电路，其输入端分别与同步整流电路原边的谐振电感的两端连接；The sampling circuit has its input terminals connected to the two ends of the resonant inductor of the primary side of the synchronous rectification circuit respectively;
波形提取电路，其输入与采样电路输出连接；a waveform extraction circuit, the input of which is connected to the output of the sampling circuit;
整形锁存电路，其输入与波形提取电路输出连接；a shaping latch circuit, the input of which is connected to the output of the waveform extraction circuit;
数字逻辑电路，其输入与整形锁存电路输出连接，其输出与第二驱动电路的输入连接。The digital logic circuit has an input connected to the output of the shaping latch circuit and an output connected to the input of the second driving circuit.
进一步地，同步整流电路至少包括第一开关MOS管Q1、第二开关MOS管Q2、谐振电感Lr、第一谐振电容Cr1、第二谐振电容Cr2，位于开关变压器Tx原边的励磁电感Lm、开关变压器Tx、第一同步整流MOS管Q3、第二同步整流MOS管Q4、输出电容Co、输出负载RL。Furthermore, the synchronous rectification circuit at least includes a first switching MOS tube Q1, a second switching MOS tube Q2, a resonant inductor Lr, a first resonant capacitor Cr1, a second resonant capacitor Cr2, an excitation inductor Lm located on the primary side of the switching transformer Tx, the switching transformer Tx, a first synchronous rectification MOS tube Q3, a second synchronous rectification MOS tube Q4, an output capacitor Co, and an output load RL.
第一开关MOS管Q1漏极同时与输入电压源Vin正极和第一谐振电容Cr1一端连接，第一开关MOS管Q1源极同时与第二开关MOS管Q2漏极和谐振电感Lr一端连接，谐振电感Lr另一端同时与励磁电感Lm一端和开关变压器Tx初级同名端连接，励磁电感Lm另一端和开关变压器Tx初级异名端同时与第一谐振电容Cr1另一端和第二谐振电容Cr2一端连接，第二谐振电容Cr2另一端和第二开关MOS管Q2源极以及输入电压源Vin负极同时与原边的地连接。第一开关MOS管Q1栅极和第二开关MOS管Q2栅极分别与所述第一驱动电路的输出连接。The drain of the first switch MOS tube Q1 is connected to the positive electrode of the input voltage source Vin and one end of the first resonant capacitor Cr1 at the same time, the source of the first switch MOS tube Q1 is connected to the drain of the second switch MOS tube Q2 and one end of the resonant inductor Lr at the same time, the other end of the resonant inductor Lr is connected to one end of the excitation inductor Lm and the primary same-name end of the switch transformer Tx at the same time, the other end of the excitation inductor Lm and the primary opposite-name end of the switch transformer Tx are connected to the other end of the first resonant capacitor Cr1 and one end of the second resonant capacitor Cr2 at the same time, the other end of the second resonant capacitor Cr2 and the source of the second switch MOS tube Q2 and the negative electrode of the input voltage source Vin are connected to the primary ground at the same time. The gate of the first switch MOS tube Q1 and the gate of the second switch MOS tube Q2 are respectively connected to the output of the first drive circuit.
开关变压器Tx次级异名端与第一同步整流MOS管Q3漏极连接，开关变压器Tx次级同名端与第二同步整流MOS管Q4漏极连接，开关变压器Tx次级中间抽头同时与输出电容Co和输出负载RL的一端连接，第一同步整流MOS管Q3源极、第二同步整流MOS管Q4源极、输出电容Co和输出负载RL的另一端同时与副边的地连接；第一同步整流MOS管Q3栅极、第二同步整流MOS管Q4栅极分别与第二驱动电路的输出连接。The secondary opposite-name end of the switching transformer Tx is connected to the drain of the first synchronous rectifier MOS tube Q3, the secondary same-name end of the switching transformer Tx is connected to the drain of the second synchronous rectifier MOS tube Q4, the secondary middle tap of the switching transformer Tx is simultaneously connected to the output capacitor Co and one end of the output load RL, the source of the first synchronous rectifier MOS tube Q3, the source of the second synchronous rectifier MOS tube Q4, the output capacitor Co and the other end of the output load RL are simultaneously connected to the ground of the secondary side; the gate of the first synchronous rectifier MOS tube Q3 and the gate of the second synchronous rectifier MOS tube Q4 are respectively connected to the output of the second drive circuit.
进一步地，采样电路至少包括输入端的电阻R1和R2，电阻R1的另一端同时与运算放大器U1的3脚和电阻R3一端连接，电阻R2的另一端同时与运算放大器U1的4脚和电阻R4一端连接，电阻R4另一端接地，电阻R3另一端与运算放大器U1的输出1脚连接，运算放大器U1的5脚接供电VCC+，运算放大器U1的2脚接供电VCC-。运算放大器型号可以选择TLV271IDBVR等。Furthermore, the sampling circuit at least includes resistors R1 and R2 at the input end, the other end of resistor R1 is connected to pin 3 of operational amplifier U1 and one end of resistor R3, the other end of resistor R2 is connected to pin 4 of operational amplifier U1 and one end of resistor R4, the other end of resistor R4 is grounded, the other end of resistor R3 is connected to pin 1 of output of operational amplifier U1, pin 5 of operational amplifier U1 is connected to power supply VCC+, and pin 2 of operational amplifier U1 is connected to power supply VCC-. The operational amplifier model can be TLV271IDBVR, etc.
进一步地，波形提取电路至少包括输入为电容Cf一端与运算放大器U1的输出1脚连接，电容Cf一端与电阻Rf一端连接，电阻Rf另一端接地；电容Cf与电阻Rf组成高通电路。高通电路可为一级或多级组成。Furthermore, the waveform extraction circuit at least includes an input, one end of a capacitor Cf is connected to the output 1 pin of the operational amplifier U1, one end of the capacitor Cf is connected to one end of a resistor Rf, and the other end of the resistor Rf is grounded; the capacitor Cf and the resistor Rf form a high-pass circuit. The high-pass circuit can be composed of one or more stages.
进一步地，整形锁存电路至少包括输入为比较器U2的3脚和比较器U3的4脚同时与电阻Rf输出连接，比较器U2的4脚、2脚接地，比较器U2的1脚为输出，比较器U3的3脚、2脚接地，比较器U3的1脚为输出。作为另外一种选择，比较器U2和U3的1脚分别连接锁存芯片(图中未画出)的输入，锁存芯片的输出连接数字逻辑电路的输入。比较器型号可以选择LMV7239M5/NOPB等。Furthermore, the shaping latch circuit at least includes inputs of the 3rd pin of the comparator U2 and the 4th pin of the comparator U3, which are simultaneously connected to the output of the resistor Rf, the 4th pin and the 2nd pin of the comparator U2 are grounded, the 1st pin of the comparator U2 is the output, the 3rd pin and the 2nd pin of the comparator U3 are grounded, and the 1st pin of the comparator U3 is the output. As another option, the 1st pins of the comparators U2 and U3 are respectively connected to the input of the latch chip (not shown in the figure), and the output of the latch chip is connected to the input of the digital logic circuit. The comparator model can be selected from LMV7239M5/NOPB, etc.
进一步地，数字逻辑电路至少包括两个触发器U4、U5，输入为触发器U4、U5的3脚分别与比较器U2、U3的1脚连接，输出为触发器U4、U5的5脚。触发器为D触发器或JK触发器或异或与D触发器组合或同或与D触发器组合的一种。Furthermore, the digital logic circuit includes at least two triggers U4 and U5, the input of which is the pin 3 of the triggers U4 and U5 connected to the pin 1 of the comparators U2 and U3 respectively, and the output of which is the pin 5 of the triggers U4 and U5. The trigger is a D trigger or a JK trigger or a combination of an XOR and a D trigger or a combination of an XOR and a D trigger.
如图4所示，一种同步整流控制方法，包括上述一种同步整流控制电路，按照以下步骤执行：As shown in FIG4 , a synchronous rectification control method includes the above-mentioned synchronous rectification control circuit and is performed according to the following steps:
步骤1，采样电路实时检测谐振电感Lr两端电压；Step 1, the sampling circuit detects the voltage across the resonant inductor Lr in real time;
步骤2，波形提取电路提取谐振电感Lr瞬态突变冲击波形；Step 2, the waveform extraction circuit extracts the transient sudden change impact waveform of the resonant inductor Lr;
步骤3，整形锁存电路整形锁存为上升沿信号；Step 3, the shaping latch circuit shapes and latches the rising edge signal;
步骤4，数字逻辑电路触发锁存上升沿信号为同步信号；Step 4, the digital logic circuit triggers the latch rising edge signal as a synchronization signal;
步骤5，第二驱动电路驱动放大同步信号，驱动对应同步整流。Step 5: The second driving circuit drives and amplifies the synchronous signal to drive the corresponding synchronous rectification.
本发明一种同步整流控制电路的波形图如图5所示，从图中可以看出，同步整流MOS管Q3波形VLr_CP3中，第一个瞬态冲击上升沿t0时刻，对应同步整流MOS管Q3驱动信号的Vgs3导通，第二个瞬态冲击上升沿t1时刻，对应同步整流MOS管Q3驱动信号的Vgs3截止，第三个瞬态冲击上升沿t4时刻，对应同步整流MOS管Q3驱动信号的Vgs3导通，第四个瞬态冲击上升沿t5时刻，对应同步整流MOS管Q3驱动信号的Vgs3截止，……如此循环，同理，同步整流MOS管Q4波形VLr_CP4中，第一个瞬态冲击上升沿t2时刻，对应同步整流MOS管Q4驱动信号的Vgs4导通，第二个瞬态冲击上升沿t3时刻，对应同步整流MOS管Q4驱动信号的Vgs4截止，第三个瞬态冲击上升沿t6时刻，对应同步整流MOS管Q4驱动信号的Vgs4导通，第四个瞬态冲击上升沿t7时刻，对应同步整流MOS管Q4驱动信号的Vgs4截止，……如此循环。A waveform diagram of a synchronous rectification control circuit of the present invention is shown in FIG5 . It can be seen from the figure that in the waveform VLr_CP3 of the synchronous rectification MOS tube Q3, at the moment of the first transient impact rising edge t0, the Vgs3 of the corresponding synchronous rectification MOS tube Q3 drive signal is turned on, at the moment of the second transient impact rising edge t1, the Vgs3 of the corresponding synchronous rectification MOS tube Q3 drive signal is turned off, at the moment of the third transient impact rising edge t4, the Vgs3 of the corresponding synchronous rectification MOS tube Q3 drive signal is turned on, and at the moment of the fourth transient impact rising edge t5, the Vgs3 of the corresponding synchronous rectification MOS tube Q3 drive signal is turned off. Vgs3 is cut off, and so on and so forth. Similarly, in the synchronous rectifier MOS tube Q4 waveform VLr_CP4, at the first transient impact rising edge t2, Vgs4 corresponding to the synchronous rectifier MOS tube Q4 drive signal is turned on, at the second transient impact rising edge t3, Vgs4 corresponding to the synchronous rectifier MOS tube Q4 drive signal is cut off, at the third transient impact rising edge t6, Vgs4 corresponding to the synchronous rectifier MOS tube Q4 drive signal is turned on, at the fourth transient impact rising edge t7, Vgs4 corresponding to the synchronous rectifier MOS tube Q4 drive signal is cut off, and so on and so forth.
需要特别说明的是，本方案通过检测谐振电压Lr瞬态突变，判断副边电流开始和结束，来控制同步整流MOS管的导通与截止。采样衰减电路也可以用变压器、线性光耦等替代来实现。整形锁存电路将谐振电感瞬态冲击电压，转换为上升沿信号，可通过锁存芯片避免杂音抖动造成误触发。该电路包含2个阈值电压比较器，输出产生上升沿或下降沿电平。数字逻辑电路，可由与非门组合实现，也可用D触发器如SN74AHC74，或T’触发器，或CPLD可编程逻辑电路搭建而成实现同等功能和效果。如图7-10所示，为可选的触发器应用电路。具体原理属于现有技术，不再赘述。It should be noted that this solution controls the conduction and cutoff of the synchronous rectifier MOS tube by detecting the transient mutation of the resonant voltage Lr and judging the start and end of the secondary current. The sampling attenuation circuit can also be implemented by replacing a transformer, a linear optocoupler, etc. The shaping latch circuit converts the transient impact voltage of the resonant inductor into a rising edge signal, and the latch chip can be used to avoid false triggering caused by noise jitter. The circuit contains two threshold voltage comparators, and the output generates a rising edge or falling edge level. The digital logic circuit can be implemented by a combination of NAND gates, or it can be built with a D flip-flop such as SN74AHC74, or a T' flip-flop, or a CPLD programmable logic circuit to achieve the same function and effect. As shown in Figure 7-10, it is an optional trigger application circuit. The specific principle belongs to the prior art and will not be repeated.
本方案也可应用于其他形式LLC谐振电路，如原边全桥结构，或副边全桥结构，如图6所示。This solution can also be applied to other forms of LLC resonant circuits, such as a primary full-bridge structure or a secondary full-bridge structure, as shown in FIG6 .
综上所述，采用本发明的技术方案具有以下有益效果：In summary, the technical solution of the present invention has the following beneficial effects:
本方案解决了现有同步整流方式中当LLC谐振电路中谐振频率高于开关频率时，存在副边电流较原边驱动提前到零，若此时副边驱动还是与原边同步导通不及时提前断开，会存在原边电流过大甚至损坏开关管的风险，采用雅达ORing场效应管控制方式对电路内部对称模块以及元器件的要求非常高、由寄生电感和引线电感引起驱动电压时高时低造成MOS管导通程度不一致、效率受到较大影响的问题。This solution solves the problem that when the resonant frequency in the LLC resonant circuit is higher than the switching frequency in the existing synchronous rectification method, the secondary current reaches zero earlier than the primary drive. If the secondary drive is still synchronously turned on with the primary and is not disconnected in advance, there will be a risk of excessive primary current or even damage to the switch tube. The use of Yada ORing field effect tube control method has very high requirements on the symmetrical modules and components inside the circuit, and the driving voltage caused by parasitic inductance and lead inductance is sometimes high and sometimes low, resulting in inconsistent conduction degree of MOS tube and greatly affecting efficiency.
由于LLC谐振电路中，副边电流正比于谐振电流与励磁电流的差值，即输出电流开始和结束的时刻，便是谐振电流与励磁电流相等的时刻，而此时也是谐振电感两端电压发生翻转的时刻。谐振电感电压突变明显，检测可靠，不易引起其他杂散寄生影响，本发明通过提取谐振电感电压瞬态突变信号，作为对应同步整流管的开启和关闭信号；从而避免了采样微弱电流小信号的采样失真，也避免了MOS管脚杂散电感等寄生参数的影响，且本方案无需实时跟随原边驱动，能在全开关频率范围应用，不受开关频率影响，进行实时跟随输出电流的同步控制，实现提高转换效率。特别是在输出短路或轻载模式下优势更为明显。Since the secondary current in the LLC resonant circuit is proportional to the difference between the resonant current and the excitation current, that is, the moment when the output current starts and ends is the moment when the resonant current is equal to the excitation current, and this is also the moment when the voltage across the resonant inductor is reversed. The resonant inductor voltage mutation is obvious, the detection is reliable, and it is not easy to cause other stray parasitic influences. The present invention extracts the transient mutation signal of the resonant inductor voltage as the opening and closing signal of the corresponding synchronous rectifier; thereby avoiding the sampling distortion of the weak current small signal, and also avoiding the influence of parasitic parameters such as the stray inductance of the MOS pin. In addition, this solution does not need to follow the primary side drive in real time, and can be used in the full switching frequency range. It is not affected by the switching frequency, and performs real-time synchronous control of the output current to improve the conversion efficiency. The advantages are more obvious in output short circuit or light load mode.
以上所述的实施方式，并不构成对该技术方案保护范围的限定。任何在上述实施方式的精神和原则之内所作的修改、等同替换和改进等，均应包含在该技术方案的保护范围之内。The above-described implementation methods do not constitute a limitation on the protection scope of the technical solution. Any modification, equivalent replacement and improvement made within the spirit and principle of the above-described implementation methods shall be included in the protection scope of the technical solution.
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