CN1097314C - Semiconductor memory device - Google Patents
Semiconductor memory device Download PDFInfo
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- CN1097314C CN1097314C CN95100994.XA CN95100994A CN1097314C CN 1097314 C CN1097314 C CN 1097314C CN 95100994 A CN95100994 A CN 95100994A CN 1097314 C CN1097314 C CN 1097314C
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Abstract
A memory matrix-which comprises memory cells arranged in matrix, each made up of a ferroelectric capacitor and an address selection MOSFET-is divided for each word line into a plurality of memory blocks. Each of the memory blocks is provided with a mode storage circuit that stores a DRAM mode (volatile mode) or an NV mode (non-volatile mode) in one-to-one correspondence for each memory block, and with a refresh operation count circuit that counts for each memory block the number of times the refresh operations is performed consecutively. During an n-th refresh operation (where n is a predetermined number of times), a memory access is made to temporarily change the plate voltage of the ferroelectric capacitor from one voltage to another and at the same time the mode storage circuit is changed from the DRAM mode to the NV mode. When a read or write operation to and from a memory cell in the memory block is performed, the mode storage circuit is changed from the NV mode to the DRAM mode. The refresh operation is omitted for the memory block that was set to the NV mode according to the stored information in the mode storage circuit.
Description
The invention belongs to the semiconductor storage technical field.Specifically, the present invention releases a kind of not technology of storage device of partly leading that is applicable to that memory cell is made of ferroelectric condenser and address choice mos field effect transistor (being MOSFET).
With ferroelectric condenser as memory cell, can nonvolatile mode and easily between disabling mode back and forth some examples of the semiconductor storage of conversion in Japanese patent gazette NO.5996/1991,283097/1991 and 283176/1991, all disclose to some extent.
Inventor of the present invention had invented a kind of semiconductor storage of function uniqueness already.In this semiconductor storage, considered that most of electric current that DRAM (dynamically read-write memory) is consumed all is to be used for refresh operation and can to worsen this two shortcomings along with the increase of number of rewrites with the polarization characteristic of the ferroelectric memory of ferroelectric condenser, overcomes this two shortcomings by remedying mutually.
The purpose of this invention is to provide a kind of low in energy consumption, semiconductor storage that number of rewrites is not limit.
Can be clear that above-mentioned and other purpose of the present invention, the explanation of being done in conjunction with the accompanying drawings of characteristics below this specification.
Representational characteristics more of the present invention can briefly be summed up as follows.Storage matrix is made up of the memory cell that some are arranged in matrix, and each memory cell all contains a ferroelectric condenser and an address choice MOSFET.Storage matrix is divided into one group of memory block by every word line.Each memory block all should have one mutually, and to be used for storing this piece be to be in the pattern storage circuit of DRAM pattern (easily disabling mode) or NV pattern (nonvolatile mode) and one to be used for this memory block is subjected to the refresh operation counting circuit that the number of times of refresh operation is counted in succession.During the n time refresh operation of one or more countings in described refresh operation counting circuit (n is a predetermined times), carry out the primary memory visit, temporarily the polar plate voltage of ferroelectric condenser is changed into another voltage from a voltage, also the pattern storage circuit is changed into the NV pattern from the DRAM pattern simultaneously.When a memory cell of this memory block is carried out a read or write, again memory circuit is changed into the DRAM pattern from the NV pattern.Do not carry out refresh operation according to the pattern information that is stored in the pattern storage circuit for the memory block of being arranged to the NV pattern.This working method greatly reduces power consumption, and because the ability that only polarizes to the NV mode switch time is anti-phase, has so in fact eliminated the restriction to number of rewrites.
After adopting said method,, need not refresh, therefore greatly reduce power consumption because the memory block of not accepting the interview is arranged to the NV pattern.In addition, because polarization is only anti-phase to the NV mode switch time, therefore in fact just eliminated restriction to the rewrite operation number of times.
In the accompanying drawing of this explanation:
Fig. 1 is the functional-block diagram that illustrates as the semiconductor storage of one embodiment of the present of invention;
Fig. 2 is used for illustrating that the pattern of semiconductor storage of the present invention changes the state transition diagram of operation;
Fig. 3 is storage matrix and the continuous simple and clear block diagram of the embodiment of refresh operation number of times control circuit that is illustrated in the semiconductor storage of the present invention;
Fig. 4 is the block diagram of an embodiment of employing semiconductor storage of the present invention;
Fig. 5 is total block diagram of an embodiment of employing semiconductor storage of the present invention;
Fig. 6 is a circuit diagram that uses the memory cell of ferroelectric condenser in semiconductor storage of the present invention;
Fig. 7 is the operation waveform of changing to nonvolatile mode when cell stores shown in Figure 6 high level;
Fig. 8 A and 8B are the polarization situation with the corresponding ferroelectric film hysteresis characteristic of Fig. 7;
Fig. 9 is to the operation waveform of NV mode switch when cell stores shown in Figure 6 low level;
Figure 10 A and 10B are the polarization situation with the corresponding ferroelectric film hysteresis characteristic of Fig. 9;
Figure 11 is the block diagram of another embodiment of employing semiconductor storage of the present invention;
Figure 12 is the schematic diagram of the computer system of employing semiconductor storage of the present invention; And
Figure 13 is the schematic diagram of the cordless telephone system of employing semiconductor storage of the present invention.
Fig. 1 shows the functional-block diagram as the semiconductor storage of one embodiment of the present of invention.Each circuit block among the figure is integrated in respectively on independent semiconductor (as the monocrystalline silicon) substrate with well-known semiconductor integrated circuit manufacturing technology.As the semiconductor storage of this embodiment mainly comprise one have a storage matrix (or memory cell array), X decoder, Y decoder, Y switch, one refresh and enable the conventional dynamic ram (brief note is DRAM) that circuit, X addressing circuit and Y address are selected circuit, also comprise a continuous refresh operation number of times control circuit, a pattern changes circuit, a mode memory and a mode adjudging circuit.Ferroelectric condenser is as the information storage capacitor of memory cell.
Storage matrix adopts the capacitor of ferroelectric condenser as the stored information that constitutes memory cell.In addition, the configuration of this storage matrix is identical with the configuration of common dynamic ram storage matrix or storage array.Be appreciated that this storage matrix also comprises relevant sense amplifier and bit-line pre-charge circuit.
Ferroelectric condenser forms with a kind of known method, promptly at first deposits one deck ferroelectric on an electrode, as PZT, forms a memory node that constitutes the capacitor of dynamic storage cell, and then forms top electrode with for example Pt.Ferroelectric can be BaMgF
4The method that forms this ferroelectric layer the 122nd to 125 page of periodical " the semiconductor world " that phase of in December, 1991 (" Semicondnctor World " December issue, 1991, detailed description is arranged in PP.122-125).
The X addressing circuit is an X Address Register, and its reception and maintenance and rwo address strobe signals be the address signal of input synchronously.It is a Y address buffer that Y address is selected circuit, and its reception and maintenance and column address gating signal be the address signal of input synchronously.
The X decoder is decoded to the X address signal, selects a word line of storage matrix.The X decoder has a word driver that drives word line.The Y decoder is decoded to the Y address signal, forms the array selecting signal of the complementary data line (being bit line) of storage matrix, control Y switch.These complementary data lines that the Y switch is chosen array selecting signal are connected to imput output circuit IOB.
Timing control circuit is write, is read according to received rwo address strobe signals, column address gating signal and written allowance signal difference and refreshes these operator schemes, forms and the corresponding interior timing signal of operator scheme.Have refreshing of address counter enable circuit during refresh mode to X decoder output refresh address.
A kind of be not with an address multiloop loop system (as dynamic ram) but with an external interface from the storage device of input X of exterior terminal independently and Y address signal, timing control circuit receives chip selection signal, written allowance signal and output and allows signal.Refresh and enable circuit a timing circuit is housed, when the refresh control end remains on significant level, produce a series of pulses, periodically start refresh operation.This that is to say, this configuration with known to pseudo-static RAM (SRAM) similar, what storage matrix was used is dynamic storage cell, but is furnished with the external interface with the static RAM (SRAM) compatibility simultaneously.
In the structure semiconductor storage identical with above-mentioned dynamic ram that is pseudo-static RAM (SRAM), in fact eliminated the restriction that meeting is caused the number of times of the anti-phase rewrite operation of ferroelectric condenser polarization, and, therefore greatly reduce the current drain that carries out refresh operation because memory cell has been used ferroelectric condenser and disposed following each circuit.
By being arranged in matrix, comprising that the storage matrix that each memory cell of a ferroelectric condenser and an address choice MOS-FET constitutes is divided into one group of memory block respectively, each memory block has one or two word lines.These memory blocks respectively have a mode memory corresponding one by one with it.Two kinds of patterns are arranged: DRAM pattern (easily disabling mode) and NV pattern (nonvolatile mode).Therefore, each memory block is furnished with the information of its pattern of bit representation.Mode memory for example can be made of a static storage circuit.
Refresh operation number of times control circuit is counted the refresh operation of each memory block continuously.When a memory cell in the memory block is write or during read operation, the refresh operation count value of this memory block just be reset (zero clearing).In other words, refresh operation number of times control circuit has been write down the number of times that each memory block has been subjected to refresh operation in succession at any time.
When will be by refreshing when enabling circuit and carrying out refresh operation, the mode adjudging circuit be read the pattern information that is stored in the mode memory according to refreshing address signal, determines to contain the memory block of wanting refresh word line and is in the DRAM pattern or is in the NV pattern.If be in the DRAM pattern, then carry out refresh operation, the count value of refresh operation number of times control circuit adds 1 continuously.If be in the NV pattern, then save current refresh operation.That is to say, do not carry out X decoder word line selection operation, also do not enable sense amplifier.
When the X addressing circuit carries out the memory access of a write or read, the mode adjudging circuit resets to zero with the refresh operation time numerical value of in the continuous refresh operation number of times control circuit corresponding memory block being counted, and changes circuit by pattern simultaneously and changes mode memory into the DRAM pattern.If memory block has been to be in the DRAM pattern, then need not carries out pattern and change.As in the dynamic ram of routine or the pseudo-static RAM (SRAM), the memory access of write or read operation comprises: the word line of being chosen storage matrix by the X decoder, enable sense amplifier, select the Y switch by the Y decoder, and the ferroelectric condenser of the memory cell chosen is charged to corresponding high level or low level writing by input and output buffer IOB under the situation according to writing information, and the situation of reading next by input and output buffer IOB output through the sense amplifier amplifying signal.
When refresh operation had been carried out pre-determined number, refresh operation number of times control circuit changed circuit indication change pattern to pattern continuously.Pattern changes circuit and temporarily the polar plate voltage of storage matrix is elevated to high level (for example being supply voltage VCC) from low level (for example being the earth potential of circuit) when refresh operation, carries out the anti-phase write operation of polarization that once causes ferroelectric condenser.Then with the NV pattern storage in mode memory.For a memory block that contains one group of word line, during selecting all to carry out the word line of refresh operation, resemble above-mentioned temporary transient change polar plate voltage, all change all memory cell into the NV pattern.
Fig. 2 shows a state transition diagram, is used for illustrating that pattern changes the situation of operating in semiconductor storage of the present invention.Corresponding with i memory block of the memory block group of being divided in mode memory (if memory block identifies with word line, then for corresponding with the 2nd word line) pattern information FN (i) is set to " 1 " (high level) when this memory block is in the DRAM pattern, then be set to " 0 " (low level) when this memory block is in the NV pattern.
In the DRAM pattern, when carrying out once read-write (W/R) operation, refresh operation counting FT (i) zero clearing that resets continuously, and whenever carrying out when once refreshing (REF) operation, then refresh operation counting FT (i) adds 1 continuously.If there is no the R/W operation between refresh operation, then refresh operation counting FT (i) constantly increases continuously.During this period, because this memory block is in DRAM, so refresh operation is normally carried out.That is: select word line, information in the memory cell of choosing being stored in is added on the complementary data line, enable sense amplifier then the little potential difference between the complementary data line is amplified to voltage difference between supply voltage and the circuit earth potential, again the voltage through amplifying is stored in the holding capacitor again.
When continuous refresh operation counting FT (i) reached predetermined value N, pattern was changed into the NV pattern, and promptly pattern information FN (i) changes into 0 from 1.In this N time refresh operation, along with pattern is changed into the NV pattern, choose word line, this will be illustrated afterwards, enable sense amplifier again, the polar plate voltage of ferroelectric condenser is temporarily changed to supply voltage from the earth potential of circuit, be changed to high level and have the earthy low level of circuit, cause the anti-phase write operation of capacitor polarization thereby carry out one with supply voltage and the current potential of the complementary data line that is connected with each memory cell is corresponding.
After this, even i memory block (word line) started refresh operation, this memory block is not refreshed yet.That is to say, except upgrading refresh address, neither carry out word line and choose, also do not enable sense amplifier.Though in the drawings, the continuous refresh operation counting FT (i) that is in the NV pattern still is N, and what meaning is this count value do not have, as time goes by in fact may be with regard to zero clearing under as the situation of memory circuit with dynamic storage cell in memory block.
When i the memory block (or word line) that is placed in the NV pattern carried out the R/W memory access, need this memory block of visit just to be transformed into the DRAM pattern, refresh operation counting FT (i) resets to zero continuously.Then, carry out the read or write identical with the above.
Fig. 3 shows the storage matrix and the continuous simple and clear block diagram of refresh operation number of times control circuit in semiconductor storage of the present invention with an embodiment.In this embodiment, storage matrix shows the corresponding circuit with i root word line WLi typically by every word line piecemeal among the figure.
In this embodiment, refresh operation number of times control circuit has one group of dynamic storage cell continuously, is connected on the same word line WLi in the storage matrix, forms a continuous refresh operation counting according to memory circuit.For example, if the refresh operation supposition will be carried out three times in succession, that should dispose two memory cell M1i and M2i is used as the memory that a continuous refresh operation of storage is counted FT (i).Each is made up of these memory cell M1i, M2i an address choice MOSWFET and a holding capacitor.Because therefore capacitor C1i, C2i need not to be ferroelectric condenser as dynamic storage cell in this embodiment.But, because can utilize the manufacturing process of the holding capacitor of storage matrix, so also use ferroelectric condenser.
Memory cell M1i, M2i receive respectively on the first complementary data line DL1, the DL2.The first complementary data line DL1, DL2 be furnished with respectively the former corresponding second complementary data line/DL1 that be arranged in parallel with it ,/the DL2 (not shown).The FTRW circuit is a control circuit, is used for reading the count value that is stored among memory cell M1i, the M2i, again the result is stored in memory cell M1i, the M2i after adding 1.For this read operation, be furnished with on the complementary data line with storage matrix in used identical sense amplifier.
In detail, sense amplifier in the FTRW circuit during the refresh operation according to the selected state of word line WLi to reading small voltage on complementary data line DL1, the DL2 from memory cell M1i, M2i and detect and amplify, and second complementary data line/DL1 ,/charging voltage of partly giving of DL2 (not shown) is taken as reference voltage.This deposits memory cell M1i, M2i more again in after amplifying signal adds 1 by add circuit.On the other hand, if this word line is selected during read-write operation, what then the FTRW circuit read is that what signal is all incited somebody to action zero (low level) write storage unit M1i, M2i, and they are resetted.
When refresh operation for the third time, the information that is stored in memory cell M1i, the M2i is 1, thereby produce a commutator pulse φ VPL, be added to the input (what add on another input of G is the selection signal of word line WLi) of gate circuit G, thereby make the polar plate voltage VRLi with the corresponding ferroelectric condenser Cmi of word line WLi that refreshes temporarily remain on high level.As a result, when refresh operation for the third time in succession, the polarization of each memory cell that is connected with word line WLi is by determining at rewriting time institute's canned data.That is to say that the memory cell that is connected with word line MLi is write as FRAM.After this, as long as also be refresh operation,, therefore no longer carry out these refresh operations because pattern has been changed into nonvolatile mode.
Yet, behind three refresh operations in succession, changing to the NV pattern immediately and can make between DRAM pattern and NV pattern conversion too frequent, this will cause increasing to very important degree owing to carry out the anti-phase characteristic degradation that causes that polarizes when being transformed into the NV pattern.Therefore, in fact before the NV mode switch, allowing continuous refresh operation number of times to be decided to be 127,255 or 511 times.For example: when number of times was decided to be 127 times, FT (i) memory had 7 this memory cell; When being 255 times, 8 this memory cell are arranged; And when being 511 times, 9 this memory cell are arranged.
Fig. 4 shows the block diagram of an embodiment who adopts semiconductor storage of the present invention.In this embodiment, external interface and dynamic ram compatibility.
In this embodiment, storage matrix comprises four memory cell arrays, and the both sides of each memory cell array have all disposed a N-channel MOS FET (NMOS) and a P channel mosfet (PMOS) that constitutes sense amplifier respectively.These four memory cell arrays are divided into two groups, every group of two memory cell arrays.Between two memory cell of every group, public column decoder and driver have been disposed.With column decoder and driver adjacency be input/output bus, this bus can be understood as and contain the Y switch.
The row address buffer receives the address signal A0-A8 that imports synchronously with rwo address strobe signals/RAS, and these address signals are delivered to row decoder.There are four row decoders corresponding one by one with four memory cell arrays respectively.The address signal of delivering to decoder from the row address buffer is by passing the address bus (not shown) transmission of these four row decoders successively.Word driver drives the word line of being chosen by the output signal of row decoder.
The column address buffer receives the address signal A0-A8 that imports synchronously with column address gating signal/CAS, and these address signals are delivered to column decoder.Column decoder is received on the input/output bus by the complementary data line of the memory cell array that driver will be chosen by control Y switch.In write operation, chosen by each memory cell array by I/O buffer, input/output bus, Y switch and complementary data line from the write signal of exterior terminal I/O1-I/O4 input, write respective memory unit.In read operation, the information that is stored in the selected unit of each memory cell array is exported by complementary data line, sense amplifier, Y switch, input/output bus, I/O buffer and exterior terminal I/O1-I/O4.
According to control signal/RAS ,/CAS, written allowance signal/WE and output allow signal/OE, control circuit is determined operator scheme, for example is write operation, read operation or refresh operation, produces and the corresponding commutator pulse of determined pattern then.
Control circuit comprises refreshing enables circuit, mode adjudging circuit, continuous refresh operation number of times control circuit, mode memory and pattern change circuit.Word driver comprises the polar plate voltage drive circuit that changes circuit block as pattern.
Fig. 5 shows total block diagram of an embodiment of semiconductor storage of the present invention.Each circuit block is integrated in respectively on each semiconductor (for example monocrystalline silicon) substrate with the known semiconductor ic manufacturing technology among the figure, as among the last embodiment.
The memory capacity of storage matrix is 1024 * 1024 (about 1 megabits).That is to say that storage matrix has 1024 word lines and 1024 pairs of complementary data lines.1024 sense amplifiers respectively one by one with 1024 pairs of corresponding configurations of complementary data line.Y switch YSW chooses a pair of from 1024 pairs of complementary data lines, and it is received on the I/O buffer IOB.
Present embodiment has been equipped with a FT storage matrix at contiguous storage matrix place, is used for storing continuous refresh operation counting, as among the embodiment of prior figures 3.In the present embodiment, storage matrix is divided into corresponding each memory block by each row.Therefore disposed the FT memory of a continuous refresh operation counting of storage respectively for each root word line.In this embodiment, the FT memory has 8, and the pattern that makes is converted to the NV pattern when refresh operation has been carried out 255 times in succession.Therefore, the structure of FT storage matrix is 1024 * 8, be furnished with 8 resemble in storage matrix sense amplifier SA.
During refresh operation, deliver to control circuit FT-CONT from the signal that the FT storage matrix is read, this circuit adds the signal of being read and writes back identical memory cell after 1, thereby has upgraded continuous refresh operation counting.In write or read operating period, control circuit FTCONT will be stored in the whole zero clearings of information of respective memory unit.Being stored in 8 information in the memory cell is 1 o'clock entirely, just when having carried out 255 refresh operations in succession, control circuit FTCONT command mode judgement control circuit FNCONT (below will be illustrated) is the NV pattern with mode switch, and make X decoder XDEC produce a high level short pulse, temporarily the polar plate voltage with ferroelectric condenser remains on the such high level of supply voltage, carries out rewriteeing in the NV pattern.
Address signal that refresh address counter among the refresh control circuit REFCT produces and the output signal of X Address Register XAB that receives the X address signal from external circuit are by circuit in the multiplexer MPX input.That is to say, during common write/read operation, multiplexer MPX sends address signal from X Address Register XAB to X decoder XDEC, and multiplexer MPX then sends the refreshing address signal that refresh control circuit REFCT produces to X decoder XDEC during refresh operation.
In the present embodiment, be connected to the FN memory of the pattern information of the corresponding memory cell that is connected of storage on the output of multiplexer MPX with each word line.The used FN memory of present embodiment is made up of static storage cell (static flip-flop register).In order to set each word line corresponding state, the FN memory has i.e. 1024 memory cell that number equates with the word line number and selects circuit accordingly.
During refresh operation, the FN memory is the row decoding during to the address signal sent here by multiplexer MPX, after the readout mode information it is delivered to mode adjudging control circuit FN-CONT.Mode adjudging control circuit FNCONT the signal of reading for 0 o'clock of expression NV pattern to signal of forbidding enabling of X decoder output.This makes that can not carry out word line in the NV pattern selects, and can not enable sense amplifier.
When control circuit FTCONT ordered to the NV mode switch, mode adjudging control circuit FNCONT write selected FN memory with 0.In addition, when receiving from timing control circuit CONT will carry out the order of read or write the time, mode adjudging control circuit FN-CONT writes corresponding FN memory with 1, makes mode switch become the DRAM pattern.Except above-mentioned these operations, also determine operator scheme according to the control signal of importing from the external world by timing control circuit CONT, for example be reading and writing or refresh mode, and produce corresponding timing signal.
Y address buffer YAB receives the Y address signal, and this signal is delivered to Y decoder YDEC.Y decoder YDEC decodes to the Y address signal, and the Y that produces a control Y switch selects signal.Like this, write the memory cell of being chosen in the storage matrix writing signal that Q when operation just will write by the need of I/O buffer IOB input, the information in the memory cell of being stored in by the sense amplifier amplification of I/O buffer IOB output then when reading the Q operation through being chosen.
Below with reference to Fig. 6,7,8A, 8B, 9,10A and 10B to being illustrated from the situation of DRAM pattern to the NV mode switch.
Fig. 6 shows a circuit with the memory cell of ferroelectric condenser in semiconductor storage of the present invention.Shown in this memory cell, known to the information storage capacitor of dynamic storage cell be a ferroelectric condenser.Yet it should be noted that polar plate voltage VPL is not changeless, but change according to operator scheme.The polarised direction of ferroelectric condenser according to from the direction of switch MOS FET Qm side or storage-node side (as arrow institute the figure to) be that pros are always definite.
Fig. 7 shows and makes the operation waveform of memory cell when nonvolatile mode is changed of storing high level.Fig. 8 A and 8B show the polarization situation of ferroelectric film hysteresis characteristic.Because what be stored in memory cell is a high level, therefore when word line is selected, the small and weak stored information that appears on bit line (the being data wire) BL is amplified to the high level of 5V by sense amplifier, and this is identical with situation in refresh operation.Under this state, the polarization and the 5V of ferroelectric film are corresponding, shown in the state 1 of this performance plot of Fig. 8 A.
Remain on as described above at bit line BL under the situation of high level, when polar plate voltage VPL is changed into identical 5V high level (state 2),, therefore produces and polarize accordingly, shown in Fig. 8 B with voltage OV because the current potential on the ferroelectric film is identical.
When polar plate voltage VPL got back to low level, added voltage was 5V again on the ferroelectric film, thereby was created in the polarization shown in the state 3.This means, even eliminate and when becoming low level, the voltage that keeps on memory node produces identical polarization at word line WL.That is to say,, former polarization is remained unchanged, therefore can not make the reverse polarity of polarised direction anti-phase owing to be transformed into the NV pattern.
Be in this NV pattern, because after this do not carry out refresh operation, leakage current will make the current potential of memory node drop to low level, and shown in state 4, so no longer be added with voltage on the ferroelectric film, information has been preserved by remnant polarization, shown in the state 4 of Fig. 8 B.
Fig. 9 shows to make and is storing the operation waveform of low level memory cell when the NV mode switch.Figure 10 A and 10B show the polarization situation of ferroelectric film hysteresis characteristic.In operation to the memory cell that is in the DRAM pattern with positive polarization, because what be stored in memory cell is a low level, therefore when word line is selected, the small and weak stored information that appears on the bit line BL is amplified to the low level of OV by sense amplifier, and this is identical with situation in refresh operation.This state 1 time, because added voltage is OV on the ferroelectric film, so the polarization of ferroelectric film is corresponding with OV, shown in the state 1 of this performance plot of Figure 10 A.
Therefore remain on as described above under the low level situation at bit line BL, when polar plate voltage VPL is changed the high level of 5V (state 2), because added voltage is-5V on the ferroelectric film, it is anti-phase to polarize, corresponding with the voltage of-5V, shown in Figure 10 B.
When polar plate voltage VPL got back to low level, added voltage was OV on the ferroelectric film.Because polarization is anti-phase, therefore the polarization that forms is consistent with negative (rather than positive) remnant polarization, shown in state 3.This means that even eliminate at word line WL, when becoming low level, the OV voltage that keeps still produces identical polarization on memory node.Be in this NV pattern, because after this do not carry out refresh operation, leakage current will make the current potential of memory node drop to low level, shown in state 4, so no longer be added with voltage on the ferroelectric film, is keeping negative remnant polarization, shown in the state 4 of Figure 10 B.
Therefore, when word line is chosen by read operation, if memory state is a state 4 as shown in Figure 7, then have one with compare for 2.5 volts as half pre-charge voltage of reference voltage be very little, output on the bit line with the corresponding high level of remnant polarization.If memory state is a state 4 as shown in Figure 9, a very little low level output is arranged then.The high or low level of output writes ferroelectric condenser again after sense amplifier amplifies, so just can obtain the corresponding read output signal of polarised direction shown in the state 2 with the state 1 of Fig. 8 A or Figure 10 B.After this, operation is carried out as in the DRAM pattern.
In the DRAM pattern, because polar plate voltage VPL is fixed as the ground level of circuit, therefore by the high or low level information of plus or minus polarization storage.That is to say that the effect of ferroelectric condenser is the same with ordinary capacitor.
In this embodiment, if there is not the execute store visit in one section official hour, all word lines are all changed into aforesaid NV pattern so.Like this, even do not carry out refresh operation always, information can not lost yet.In fact this will use the current drain during the stand-by power supply almost to be reduced to zero.Do not make all word lines all change into NV pattern by in one section official hour, not carrying out read/write operation if resemble above-mentioned, though so when outage information can not lose yet.Also can dispose a kind of operator scheme, refresh operation week after date force mode switch to become the NV pattern so that cut off the electricity supply, do not waited for one section official hour with regard to not needing to resemble above-mentioned like this.
Figure 11 shows the block diagram of another embodiment that adopts semiconductor storage of the present invention.This embodiment is used for the pseudo-static RAM (SRAM) of external interface and static RAM (SRAM) compatibility.
In this embodiment, address signal A0-A10 is input to the address latch control circuit.Address signal A0-A10 forms word line selection signal as the X address signal row decoder of feeding by row decoder.After address signal A11-A18 is input to the address latch control circuit,, produce the selection signal, be input to row input/output circuitry with row switch by column decoder as Y address signal mixing column decoder.Like this, X and Y address signal are just provided with the external interface of static RAM (SRAM) compatibility from each separate outer terminal.
Identical among storage matrix and the embodiment in front also is made up of the information storage capacitor of some address choice MOS-FET and ferroelectric capacitor type.After the signal that writes from the need of I/O terminal I/O 0-I/O7 input is input to input data control circuit, write selected memory cell in the storage matrix by the row input/output circuitry.Export to exterior terminal I/O0-I/O7 by the signal that the row input/output circuitry is read by output state.
Control signal/OE*/RFSH that timing pulse generator circuit and read/write control circuit provide according to exterior terminal (output allow signal and refresh control signal) ,/CE (sheet permission signal) and/WE (written allowance signal) determines operator scheme and the corresponding commutator pulse of generation.Control signal/OE*/RFSH on an exterior terminal has output and allows two kinds of effects that signal and refresh control signal play.
Refresh control circuit can resemble as described as follows and constitute.The high level that comes selected state for the expression sheet as control signal/CE as the refresh control signal input /when the OE*RFSH signal remained on low level in one period short time, refresh control circuit increased refresh address, carries out refresh operation at this section in the short time; When/when the OE*/RFSH signal remained on low level a segment length in the time, refresh control circuit was carried out refresh operation this segment length in the time by the pulse enable that timing circuit produces.
Above-mentioned refresh control circuit and read/write control circuit be furnished with refresh enable circuit, mode adjudging circuit, refreshing frequency control circuit, mode memory and pattern change circuit continuously.The X decoder comprises a polar plate voltage drive circuit that changes the parts of circuit as pattern.Like this, this pseudo-static RAM (SRAM) is also changed into the NV pattern automatically after refresh operation has been carried out pre-determined number in succession, stops the refresh operation of word line.If all word lines all are arranged to the NV pattern, then almost have only refresh timing circuit and address counter in work.This means, when this pseudo-static RAM (SRAM) is arranged to the information hold mode, can reduce power consumption greatly.Also can when keeping pattern and NV pattern, configuration information stop timing circuit work itself.
Figure 12 shows and adopts semiconductor storage (D﹠amp of the present invention; The general structure of computer system FRAM).This computer system comprises: as the central processing unit CPU of information processor, be arranged on the I/O bus in the information processing system, bus unit, the memory control unit of execution to conducting interviews such as main storage and the such high-speed memory of extended menory is as the D﹠amp of main storage; FRAM, the ROM of storage primary control program (PCP), and the keyboard controller KBDC that is connected with keyboard KB.
Display adapter one terminates to the I/O bus, and the other end is received display.The I/O bus is with parallel port I/F, Genius mouse serial port I/F, floppy disk FDD and be used for becoming the HDD buffer of the cache controller of HDDI/F to be connected the data conversion from the I/O bus.Memory control unit and expansion RAM and as the D﹠amp of main storage; FRAM connects.
The working condition of this computer system will be described below.When connecting computer system power source, CPU at first by I/O bus access ROM, carries out initial diagnosis and initial setting up.Then, system program is packed into as the D﹠amp of main storage from auxilary unit; FRAM.Simultaneously, CPU conducts interviews to HDD by I/O bus starting HDD controller.When system program was packed into fully, CPU carried out according to customer requirements and handles.
The user carries out I/O control by keyboard controller KBDC and the display adapter that is connected on the I/O bus.Can use the input/output device that is connected with serial port I/F with parallel port I/F in case of necessity.
When main memory capacity is not enough, remedy D﹠amp as main storage with expansion RAM; The deficiency of the capacity of FRAM.When the user wants to read a file, user applies visit auxilary unit (HDD).Then, by D﹠amp of the present invention; The document storage system that FRAM constitutes is accepted this application, takes out the corresponding document data.
At main storage D﹠amp; Among the FRAM, be not all memory blocks of visit usually, often visit is the very small percentage of memory block, and other most of zones are visited hardly.In this case, because almost whole memory block all transfers the NV pattern automatically to and do not need to carry out refresh operation, therefore greatly reduce power consumption.If in the littler file memory of the possibility that receives visit, adopt D﹠amp; FRAM, then almost whole memory block all transfers the NV pattern that needn't refresh to, thereby greatly reduces current drain.
For battery-powered computer system (for example imported and palmtop computer of pen), adopt above-mentioned D﹠amp; FRAM can reduce power consumption greatly as memory, thereby has prolonged the life-span of battery.
Figure 13 shows and wherein adopts semiconductor storage (D﹠amp of the present invention; The overall block-diagram of cordless telephone system FRAM).Wireless receiving to radio wave carry out wave shape equalization and analog-to-digital conversion process by the feed digital modulation circuit of base band part of AFE (analog front end) portion.The output signal of digital modulation circuit is fed, and the chnnel coding circuit carries out the error calibration and frame decomposes.The output signal of the logical coding of the letter phone speech coder and decoder circuit of feeding carries out being added on the loud speaker of cordless telephone after digital to analog conversion and the voice expansion.
To illustrate below and adopt D﹠amp of the present invention; The cordless telephone system of FRAM sends the situation of voice.Enter the micropkonic voice of cordless telephone and feed after the speech coder and decoder circuit of base band part carries out analog to digital conversion and compress speech, by the chnnel coding circuit carry out error correction and frame integrated.The output signal of chnnel coding circuit sends antenna to by AFE (analog front end) portion after wave shape equalization and digital to analog conversion.
By microprocessor and D﹠amp of the present invention; In the control part that FRAM forms, microprocessor and D﹠amp; FRAM is interconnected to and is in bidirectional relationship.According to the signal from cordless telephone key input, microprocessor is controlled, with transfer to fast number and code write D﹠amp of the present invention; FRAM.Microprocessor is also read and is stored in D﹠amp of the present invention; Quick dial-out among the FRAM number and code.
Digital modulation circuit and speech coder and decoder circuit are controlled by microprocessor.Like this, because the control part at cordless telephone has adopted FRAM of the present invention, therefore can reduce the volume of control part, thereby reduce volume, weight and the power consumption of cordless telephone system, simultaneously can also read bulk information fast, improve the disposal ability of whole system.In addition, also can improve, thereby improve the reliability of cordless telephone system as the shock resistance of a basic index of portable phone.
More than the feature and advantage of each embodiment be summarized as follows.
(1) storage matrix is made up of the memory cell that some are arranged in matrix, and each memory cell all is made of a ferroelectric condenser and an address choice MOSFET.Storage matrix is divided into one group of memory block by every word line.Each memory block all should have one mutually, and to be used for storing this piece be to be in the pattern storage circuit of DRAM pattern or NV pattern and one to be used for this memory block is subjected to the refresh operation counting circuit that the number of times of refresh operation is counted in succession.During carrying out the n time refresh operation (n is a predetermined times), carry out the primary memory visit, temporarily the polar plate voltage of ferroelectric condenser is changed into another voltage from a voltage, the while is also changed into the NV pattern with the pattern storage circuit from the DRAM pattern.When a memory cell of this memory block is carried out a read or write, again the pattern storage circuit is changed into the DRAM pattern from the NV pattern.Do not carry out refresh operation according to the information that is stored in the pattern storage circuit for the memory block of being arranged to the NV pattern.This working method greatly reduces power consumption, and it is just anti-phase only to polarize to the NV mode switch time, has so in fact eliminated the restriction to number of rewrites.
(2) each memory block is divided according to every word line that is used for refresh operation.The pattern storage circuit constitutes with a static memory with some bank bits, and each is corresponding with a word line in the independent word line.This configuration can be provided with pattern for each refresh address, therefore greatly reduces power consumption.
(3) the refresh operation counting circuit comprises: one that constitute by one group of memory cell, with the memory circuit of storage matrix shared word line; And one will add the memory cell that deposits memory circuit after 1 again in from the data that memory circuit is read and be stored in the control circuit that the information the memory circuit resets being carried out to make when word line is selected by read/write operation at every turn being carried out by refresh operation at every turn when word line is selected.This makes the X decoding circuit to resemble and uses the routine, thereby can carry out the pattern setting for each word line with a quite simple structure.
(4) also pole plate is divided in the mode identical, made and having only the voltage of corresponding pole plate just temporarily to change to supply voltage during to the NV mode switch from the DRAM pattern with dividing memory block.This makes the polar plate voltage drive circuit to realize with a simple structure, and has reduced current drain.
It is above that the invention has been described in conjunction with each embodiment.It should be noted that the present invention is not limited to above these embodiment, but can make various modifications, this does not depart from spirit of the present invention.The storage array on the semiconductor chip or the geometry arrangement of storage matrix and configuration can be adopted various ways.For example, storage array or storage matrix are divided into memory block on how much, and word line then is divided into a series of groups physically.When storage array was divided into piece, attentiveness did not concentrate on the physical word line, and will concentrate on the word line that refresh operation chooses simultaneously, and these word lines of choosing are simultaneously got the least unit that work is divided into storage array memory block.The result does not carry out the working method of refresh operation during just can utilizing circuit to be implemented in effectively to be in the NV pattern, thereby reduces power consumption.Polar plate voltage can temporarily change to the earth potential of circuit from supply voltage to the NV mode switch time.
The present invention can be widely used in the occasion that storage device is made of some pseudo-static RAM (SRAM)s basically, these pseudo-static RAM (SRAM)s have adopted dynamic ram or dynamic storage cell, external interface with the static RAM (SRAM) compatibility is arranged, and in memory cell, used ferroelectric container.
Representative advantage of the present invention can be summarized as follows.Storage matrix is made up of the memory cell that some are arranged in matrix, and each memory cell all is made of a ferroelectric condenser and an address choice MOSFET.Storage matrix is divided into one group of memory block by every word line.Each memory block all should have one mutually, and to be used for storing this piece be to be in the pattern storage circuit of DRAM pattern or NV pattern and one to be used for this memory block is subjected to the refresh operation counting circuit that the number of times of refresh operation is counted in succession.During carrying out the n time refresh operation (n is a predetermined times), carry out the primary memory visit, temporarily the polar plate voltage of ferroelectric condenser is changed into another voltage from a voltage, the while is also changed into the NV pattern with the pattern storage circuit from the DRAM pattern.When a memory cell of this memory block is carried out a read or write, again the pattern storage circuit is changed into the DRAM pattern from the NV pattern.Do not carry out refresh operation according to the information that is stored in the pattern storage circuit for the memory block of being arranged to the NV pattern.This working method greatly reduces power consumption, and it is just anti-phase only to polarize to the NV mode switch time, has so in fact eliminated the restriction to number of rewrites.
Each memory block all is that refresh operation distributes an independently word line.The pattern storage circuit constitutes with a static memory with some bank bits, and each is corresponding with a word line in the independent word line.This configuration can be DRAM pattern or NV pattern for each refresh address is provided with pattern, therefore greatly reduces power consumption.
The refresh operation counting circuit comprises: one that constitute by one group of memory cell, with the memory circuit of storage matrix shared word line; And one at every turn by refresh operation carry out will add the memory cell that deposits memory circuit after 1 again in when word line is selected from the data that memory circuit is read and at every turn by this/write operation carries out to make when word line is selected and is stored in the control circuit that the information the memory circuit resets.This makes the X decoding circuit to resemble and uses the routine, thereby can be set to DRAM pattern or NV pattern for each word line pattern with a quite simple structure.
Also pole plate is divided in the mode identical, made and having only the voltage of corresponding pole plate just temporarily to change to supply voltage during to the NV mode switch from the DRAM pattern with dividing memory block.This makes the polar plate voltage drive circuit to realize with a simple structure, and has reduced current drain.
Claims (23)
1. semiconductor storage is characterized in that described device comprises:
One is arranged in the storage matrix that the memory cell of matrix constitutes by some, and each memory cell wherein all has a ferroelectric condenser and an address choice MOSFET;
One group of memory block of dividing described storage matrix according to every one or a few word line and obtaining;
With the pattern storage circuit of the corresponding one by one configuration of described memory block, the pattern that is used for storing respectively corresponding memory block is the easy disabling mode or the information of nonvolatile mode;
The refresh operation counting circuit is used for respectively the number of times of refresh operation that corresponding memory block is subjected in succession to count;
A pattern changes circuit, during the n time refresh operation of one or more countings in described refresh operation counting circuit, described circuit carries out the primary memory visit, temporarily the polar plate voltage of ferroelectric condenser is changed into another voltage and the pattern storage circuit is converted to nonvolatile mode from easy disabling mode from a voltage, and during a memory cell of described memory block is carried out a read or write, the pattern storage circuit is converted to easy disabling mode from nonvolatile mode; And
A refresh control circuit, described circuit is not carried out refresh operation to the described memory block that is converted to nonvolatile mode according to the information that is stored in the described pattern storage circuit.
2. one kind by semiconductor storage that claim 1 proposed, it is characterized in that: wherein said memory block is to divide by every word line that is used to refresh, and described pattern storage circuit is made of a static memory with some bank bits, and each is corresponding with a word line in the independent word line.
3. one kind by the semiconductor storage that claim 2 proposed, and it is characterized in that wherein said refresh operation counting circuit comprises: one that constitute by one group of memory cell, with the memory circuit of described storage matrix shared word line; And one will add the memory cell that deposits memory circuit after 1 again in from the data that memory circuit is read and carrying out the control circuit that the information that is stored in memory circuit is resetted by read/write operation at every turn being carried out by refresh operation at every turn when word line is selected.
4. one kind by the semiconductor storage that claim 3 proposed, and it is characterized in that described semiconductor storage also comprises an outer input interface made from the dynamic ram compatibility.
5. one kind by the semiconductor storage that claim 3 proposed, and it is characterized in that described semiconductor storage also comprises an outer input interface made from the static RAM (SRAM) compatibility.
6. one kind by semiconductor storage that claim 5 proposed, it is characterized in that wherein having a pole plate also to divide, make and when nonvolatile mode is changed, having only the voltage of corresponding pole plate just temporarily to change to supply voltage from easy disabling mode in the mode identical with dividing memory block.
7. semiconductor storage comprises:
One comprises a plurality of memory cell, each memory cell has the memory array of a ferroelectric condenser, described memory array works in a kind of easy disabling mode, in this pattern, described a plurality of memory cell has volatibility, perhaps work in a nonvolatile mode, in this pattern, described a plurality of memory cell have non-volatile; And
A control circuit, be used to control described storage array, when described memory array works in described easy disabling mode, it is not accessed that described memory array is listed in preset time, and the mode of operation of described memory array is changed to described nonvolatile mode from described easy disabling mode.
8. semiconductor storage according to claim 7, wherein said control circuit comprise a pattern information memory circuit, its storage first information or second information,
Wherein said memory array works in described easy disabling mode in response to the described pattern information memory circuit of the described first information of storage, works in described nonvolatile mode in response to the described pattern information memory circuit of storing described second information,
Wherein when described memory array worked in described easy disabling mode, it is not accessed that described memory array is listed in preset time, described control circuit with described second information setting at described pattern information memory circuit.
9. semiconductor storage according to claim 8, wherein said control circuit also comprise a circuit that is used for determining the described scheduled time.
10. semiconductor storage according to claim 8, wherein said control circuit also comprise a circuit that is used to calculate the described scheduled time.
11. semiconductor storage according to claim 8, wherein said control circuit also comprise a continuous refresh operation counting number circuit, are used for the inferior counting number to continuous refresh operation.
12. semiconductor storage according to claim 8, wherein said control circuit also comprise a refresh operation counting number circuit, are used for determining the described scheduled time according to the refresh operation number.
13. a semiconductor storage comprises:
One comprises a plurality of memory cell, each memory cell has the memory array of a ferroelectric condenser, described memory array works in a kind of easy disabling mode, in this pattern, described a plurality of memory cell need refresh, perhaps work in a nonvolatile mode, in this pattern, described a plurality of memory cell does not need to refresh, when described memory array works in described easy disabling mode, described memory array is carried out a write operation, a read operation or an individual refresh operation; And
A control circuit, be used to control described storage array, when described memory array works in described easy disabling mode, described memory array is listed in preset time and neither carries out write operation and also do not carry out read operation, and the mode of operation of described memory array is changed to described nonvolatile mode from described easy disabling mode.
14. semiconductor storage according to claim 13, when described memory array works in described nonvolatile mode, when described write operation or described read operation are made described memory array, wherein said control circuit is controlled described memory array, makes the operator scheme of described memory array change into described easy disabling mode from described nonvolatile mode.
15. semiconductor storage according to claim 13, wherein said control circuit comprise a pattern information memory circuit, its storage first information or second information,
Wherein said memory array works in described easy disabling mode in response to the described pattern information memory circuit of the described first information of storage, works in described nonvolatile mode in response to the described pattern information memory circuit of storing described second information,
Wherein when described memory array works in described easy disabling mode, described memory array is listed in preset time and neither carries out described write operation and also do not carry out read operation, described control circuit with described second information setting at described pattern information memory circuit.
16. semiconductor storage according to claim 15, wherein said control circuit also comprise a circuit that is used for determining the described scheduled time.
17. semiconductor storage according to claim 15, wherein said control circuit also comprise a circuit that is used to calculate the described scheduled time.
18. semiconductor storage according to claim 15, wherein said control circuit also comprise a continuous refresh operation counting number circuit, are used for the inferior counting number to continuous refresh operation.
19. semiconductor storage according to claim 15, wherein said control circuit also comprise a refresh operation counting number circuit, are used for determining the described scheduled time according to the refresh operation number.
20. a method of operating semiconductor storage, described storage device comprise a memory array, described memory array comprises a plurality of memory cell, and each memory cell has a ferroelectric condenser, and described method comprises the steps:
Make described memory array work in a kind of easy disabling mode, in this pattern, described a plurality of memory cell need refresh;
Make described memory array work in a nonvolatile mode, in this pattern, described a plurality of memory cell do not need to refresh;
When described memory array works in described easy disabling mode, make described memory array carry out a write operation; And
When described memory array works in described easy disabling mode, make described memory array carry out a read operation;
When described memory array works in described easy disabling mode, make described memory array carry out a refresh operation; And
When described memory array works in described easy disabling mode, described memory array is listed in preset time and neither carries out write operation and also do not carry out read operation, and the mode of operation of described memory array is changed to described nonvolatile mode from described easy disabling mode.
21. semiconductor storage method of operation according to claim 20 also comprises a following step:
When described memory array works in described nonvolatile mode, when described write operation or described read operation are made described memory array, the operator scheme of described memory array is changed into described easy disabling mode from described nonvolatile mode.
22. a method of operating semiconductor storage, described storage device comprise a memory array, described memory array comprises a plurality of memory cell, and each memory cell has a ferroelectric condenser, and described method comprises the steps:
(1) at least one in described a plurality of memory cell of the described memory array that works in a kind of easy disabling mode writes data, and in this pattern, described a plurality of cell stores have the data of volatibility;
(2) at least one sense data from described a plurality of memory cell of the described memory array that works in described easy disabling mode;
(3) at least one refresh data from described a plurality of memory cell of the described memory array that works in described easy disabling mode;
(4) at least one in described a plurality of memory cell of the described memory array that works in a kind of nonvolatile mode writes data, and in this pattern, described a plurality of cell stores have non-volatile data;
(5) at least one sense data from described a plurality of memory cell of the described memory array that works in described nonvolatile mode;
(6) when described memory array works in described easy disabling mode, described memory array is listed in preset time and neither carries out the described step (1) of writing and also do not carry out the described step (2) of reading, and the mode of operation of described memory array is changed to described nonvolatile mode from described easy disabling mode.
23. the method according to the operation semiconductor storage of claim 22 also comprises the steps:
When described memory array works in described nonvolatile mode, when the described step (4) or described when reading step (5) described memory array being made of writing, the operator scheme of described memory array is changed into described easy disabling mode from described nonvolatile mode.
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| JP06210894A JP3426693B2 (en) | 1994-03-07 | 1994-03-07 | Semiconductor storage device |
| JP062108/94 | 1994-03-07 |
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| JP2723386B2 (en) * | 1991-07-02 | 1998-03-09 | シャープ株式会社 | Non-volatile random access memory |
| JP2794138B2 (en) * | 1991-08-13 | 1998-09-03 | 三菱電機株式会社 | Semiconductor storage device |
| US5396461A (en) * | 1992-01-16 | 1995-03-07 | Sharp Kabushiki Kaisha | Non-volatile dynamic random access memory device |
| KR950009390B1 (en) * | 1992-04-22 | 1995-08-21 | 삼성전자주식회사 | Refresh address test circuit of semiconductor memory device |
| US5381379A (en) * | 1992-12-03 | 1995-01-10 | Sharp Kabushiki Kaisha | Non-volatile dynamic random access memory device; a page store device and a page recall device used in the same; and a page store method and a page recall method |
| JP3278981B2 (en) * | 1993-06-23 | 2002-04-30 | 株式会社日立製作所 | Semiconductor memory |
| JP3426693B2 (en) * | 1994-03-07 | 2003-07-14 | 株式会社日立製作所 | Semiconductor storage device |
| US5495437A (en) * | 1994-07-05 | 1996-02-27 | Motorola, Inc. | Non-volatile RAM transferring data between ferro-electric capacitors and a memory cell |
-
1994
- 1994-03-07 JP JP06210894A patent/JP3426693B2/en not_active Expired - Fee Related
-
1995
- 1995-02-14 TW TW084101310A patent/TW272315B/zh active
- 1995-02-23 DE DE69521159T patent/DE69521159T2/en not_active Expired - Fee Related
- 1995-02-23 EP EP95301192A patent/EP0671745B1/en not_active Expired - Lifetime
- 1995-03-07 US US08/399,511 patent/US5528535A/en not_active Expired - Lifetime
- 1995-03-07 CN CN95100994.XA patent/CN1097314C/en not_active Expired - Fee Related
-
1996
- 1996-06-04 US US08/658,081 patent/US5715190A/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| US5528535A (en) | 1996-06-18 |
| DE69521159T2 (en) | 2002-02-28 |
| TW272315B (en) | 1996-03-11 |
| EP0671745A3 (en) | 1997-02-19 |
| JP3426693B2 (en) | 2003-07-14 |
| CN1112729A (en) | 1995-11-29 |
| DE69521159D1 (en) | 2001-07-12 |
| JPH07244988A (en) | 1995-09-19 |
| EP0671745A2 (en) | 1995-09-13 |
| EP0671745B1 (en) | 2001-06-06 |
| US5715190A (en) | 1998-02-03 |
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