CN109728570B - Circuit for suppressing surge current - Google Patents

Abstract

The present invention discloses a circuit for suppressing surge current, comprising a switch unit, a feedback control unit, a voltage coupling unit and a reference signal generating unit. A first end of the switch unit is used to couple to a voltage source. A second end of the switch unit is used to couple to a first capacitor. An output end of the feedback control unit is coupled to a third end of the switch unit. An input port of the voltage coupling unit is coupled to the second end of the switch unit. An output port of the voltage coupling unit is coupled to a feedback signal input end of the feedback control unit. The reference signal generating unit is coupled to the reference signal input end of the feedback control unit.

Description

Circuit for Suppression of Surge Current

technical field

The present invention relates to a circuit for suppressing inrush current.

Background technique

Generally speaking, for most electronic equipment, the inner working circuit is powered by direct current. In order to obtain the stability of the DC power supply, the circuit needs to contain energy storage elements, and the most common energy storage element is the capacitor. When the power is turned on (or the power is turned on), since the initial voltage of the capacitor is zero, it is approximately short-circuited, so a large transient current, the so-called inrush current, will be generated. Inrush current may cause noise, and even lead to malfunction of internal circuits of electronic equipment or failure of internal components.

In the prior art, the rising slope of the gate-source voltage (Vgs) of the electronic load switch is controlled to reduce the speed at which the switch impedance changes from a maximum value to a near-zero value, so as to achieve the purpose of reducing the inrush current. However, due to the characteristics of semiconductor electronic switches, the switch impedance does not decrease linearly during the gate-source voltage rise. The waveform obtained by actually measuring the prior art circuit is shown in Figure 8. The arrow 1 on the left vertical axis indicates the gate-source voltage waveform of the electronic switch, the arrow 2 indicates the voltage waveform of the capacitor at the load end, and the arrow 4 indicates the current waveform of the capacitor at the load end. The horizontal axis is time, and a large scale is 20ms. For the gate-source voltage waveform of the electronic switch, the vertical axis coordinate is voltage, and a large scale is 2.5V. For the voltage waveform of the capacitor at the load end, the vertical axis is the voltage, and a large scale is 2V. For the current waveform of the capacitor at the load end, the vertical axis coordinate is the current, and a large scale is 10A.

As can be seen from the figure, when the initial gate-source voltage has not yet reached the threshold (Threshold), the impedance is almost maintained at a maximum value, so there is no current to charge the load capacitor during this period. When the gate-source voltage reaches the threshold, the gate-source voltage rises slightly (several millivolts to hundreds of millivolts), and the impedance drops sharply. At this time, it is the charging time for the main load capacitor, and the surge current occurs at this time. , the capacitor is usually charged in this time interval. The gate-source voltage exceeds the threshold, at which point the electronic switch impedance continues to drop to near zero. That is to say, the charging time of the capacitor in the prior art is very short, so the inrush current cannot be effectively suppressed (the peak value of the inrush current is as high as 48.2A).

In order to prolong the charging time of the capacitor, the overall circuit startup speed is usually slower. And because the threshold voltage of the electronic switch has an error value, the difficulty of circuit optimization design is increased.

Therefore, how to provide a circuit for suppressing the surge current is an important issue.

SUMMARY OF THE INVENTION

An embodiment of the present invention discloses a circuit for suppressing surge current, which includes a switch unit, a feedback control unit, a voltage coupling unit, and a reference signal generating unit. The switch unit has a first end, a second end and a third end. The first end of the switch unit is coupled to a voltage source. A second end of the switch unit is coupled to a first capacitor. The feedback control unit has a feedback signal input end, a reference signal input end and an output end. The output end of the feedback control unit is coupled to the third end of the switch unit. The voltage coupling unit has an input port and an output port. The input port of the voltage coupling unit is coupled to the second end of the switch unit. The output port of the voltage coupling unit is coupled to the feedback signal input end of the feedback control unit. The reference signal generating unit is coupled to the reference signal input terminal of the feedback control unit.

The present invention is described in detail below with reference to the accompanying drawings and specific embodiments, but is not intended to limit the present invention.

Description of drawings

FIG. 1 is a block diagram illustrating a circuit for suppressing inrush current according to a first embodiment of the present invention.

FIG. 2 is a block diagram of a circuit for suppressing inrush current according to a second embodiment of the present invention.

3 is a block diagram illustrating a circuit for suppressing inrush current according to a third embodiment of the present invention.

4 is a block diagram illustrating a circuit for suppressing inrush current according to a fourth embodiment of the present invention.

5 is a block diagram illustrating a circuit for suppressing inrush current according to a fifth embodiment of the present invention.

6 is a block diagram illustrating a circuit for suppressing inrush current according to a sixth embodiment of the present invention.

FIG. 7 is a measurement waveform diagram of a circuit for suppressing inrush current according to a third embodiment of the present invention.

FIG. 8 is a measurement waveform diagram of a circuit according to the prior art.

where the reference number

1a～1f: Circuit

12: Switch unit

14: Feedback control unit

16: Voltage coupling unit

18: Reference signal generation unit

Vs: voltage source

C1: first capacitor

C2: second capacitor

Q1n: N-type metal oxide semiconductor field effect transistor

Q1p: P-type metal oxide semiconductor field effect transistor

Q2: PNP type bipolar transistor

Q3: NPN type bipolar transistor

D1: Diode

R1: first resistor

R2: second resistor

R3: third resistor

R4: Fourth resistor

R5: Fifth resistor

R6: sixth resistor

R7: seventh resistor

Rs1: first divider resistor

Rs2: second voltage divider resistor

Rs3: The third voltage divider resistor

Rs4: Fourth divider resistor

VDD: driving voltage source

Voffset: offset voltage source

Is: current source

OP: Operational Amplifier

20: Switch protection unit

Rp: protection resistance

ZD1: First Zener Diode

ZD2: Second Zener Diode

Detailed ways

The technical solution of the present invention will be described in detail below in conjunction with the accompanying drawings and specific embodiments, so as to further understand the purpose, solution and effect of the present invention, but it is not intended to limit the protection scope of the appended claims of the present invention.

Please refer to FIG. 1 . FIG. 1 is a block diagram illustrating a circuit for suppressing inrush current according to a first embodiment of the present invention. The circuit 1 a includes a switch unit 12 , a feedback control unit 14 , a voltage coupling unit 16 and a reference signal generating unit 18 .

The switch unit 12 has a first terminal, a second terminal and a third terminal. The first end of the switch unit 12 is coupled to a voltage source Vs. The second end of the switch unit 12 is coupled to the first capacitor C1.

The feedback control unit 14 has a feedback signal input terminal, a reference signal input terminal and an output terminal. The output terminal of the feedback control unit 14 is coupled to the third terminal of the switch unit 12 to control the switch unit 12 to be turned on or off.

The voltage coupling unit 16 has an input port and an output port. The input port of the voltage coupling unit 16 is coupled to the second end of the switch unit 12 to obtain a feedback signal. The output port of the voltage coupling unit 16 is coupled to the feedback signal input terminal of the feedback control unit 14 to provide the feedback signal to the feedback control unit 14 .

The reference signal generating unit 18 is coupled to the reference signal input terminal of the feedback control unit 14 to provide the generated reference signal to the feedback control unit 14 .

In some embodiments, the voltage source Vs is, for example, an external power supply, and the circuit 1a is disposed in an electronic device, for example, to protect the electronic device connected to the external power supply. When the external power supply is turned on, the circuit 1a starts to operate to limit the peak value of the inrush current to prevent damage to the internal parts of the electronic device.

In other embodiments, the circuit 1a is disposed in a power supply, for example, to protect an electronic device coupled to the power supply. Similarly, when the power supply is turned on, the circuit 1a starts to operate to limit the peak value of the inrush current to prevent damage to the internal parts of the electronic device.

The operation principle of the circuit 1 a is to couple the voltage (terminal voltage value) of the first capacitor C1 to the feedback control unit 14 as a feedback signal through the voltage coupling unit 16 . The feedback control unit 14 outputs a control signal according to the feedback signal and the reference signal to control the switch unit 12 to be turned on or off. By controlling the switching unit 12 to be turned on or off, the rising slope of the voltage of the first capacitor C1 is controlled, so as to achieve the effect of suppressing the surge current.

Please refer to FIG. 2 , which is a block diagram of a circuit for suppressing inrush current according to a second embodiment of the present invention. The circuit 1b is similar to the circuit 1a, except that the input port of the voltage coupling unit 16 is further coupled to the first end of the switch unit 12 . In this embodiment, the voltage coupling unit 16 couples the voltage across the first terminal and the second terminal of the switch unit 12 (ie, the voltage difference) as a feedback signal to the feedback control unit 14 . However, the basic operation principles of the circuit 1b and the circuit 1a are still similar, and both control the switching unit 12 to control the voltage rising slope of the first capacitor C1 by obtaining the feedback signal. Several specific embodiments will be given below to further illustrate the principles and details of the present invention.

Please refer to FIG. 3 , which is a block diagram of a circuit for suppressing inrush current according to a third embodiment of the present invention. The circuit 1c is similar to the circuit 1a, and uses the voltage of the first capacitor C1 as the feedback signal.

The switch unit 12 includes an N-type MOS transistor Q1n and a diode D1. A drain of the NMOS transistor Q1n is used as the first terminal of the switch unit 12 to be coupled to the voltage source Vs. A source of the NMOS transistor Q1n serves as the second terminal of the switch unit 12 and is coupled to the first capacitor C1. A gate of the NMOS transistor Q1n serves as the third terminal of the switch unit 12 and is coupled to the feedback control unit 14 . The diode D1 is coupled between the drain electrode and the source electrode of the NMOS transistor Q1n to prevent the NMOS transistor Q1n from being damaged.

The reference signal generating unit 18 includes a second capacitor C2 and a first resistor R1. A first end of the second capacitor C2 is grounded, and a second end of the second capacitor C2 is coupled to the reference signal input end of the feedback control unit 14 . A first end of the first resistor R1 is coupled to a driving voltage source VDD, and a second end of the first resistor R1 is coupled to the second end of the second capacitor C2. In this embodiment, the reference signal generating unit 18 charges the second capacitor C2 with the driving voltage source VDD, and outputs the voltage of the second capacitor C2 as the reference signal. In other words, the reference signal is a voltage waveform with a positive slope.

The feedback control unit 14 includes a PNP type bipolar transistor Q2, an NPN type bipolar transistor Q3, a second resistor R2 and a third resistor R3.

An emitter of the PNP bipolar transistor Q2 is coupled to the driving voltage source VDD. A collector of the PNP bipolar transistor is coupled to the third terminal of the switch unit 12 through the second resistor R2. A base of the PNP bipolar transistor Q2 is coupled to a first end of the third resistor R3.

A collector of the NPN bipolar transistor Q3 is coupled to a second end of the third resistor R3. An emitter of the NPN bipolar transistor Q3 is coupled to the output port of the voltage coupling unit 16 . A base of the NPN bipolar transistor Q3 is coupled to the reference signal generating unit 18 .

The voltage coupling unit 16 is a wire, which directly couples the voltage of the first capacitor C1 to the feedback signal input terminal of the feedback control unit 14 .

The detailed operation principle of this embodiment is as follows.

Without loss of generality, it is assumed that the initial voltage of the first capacitor C1 is zero when the voltage source Vs is turned on. The reference signal generating unit 18 starts to output a voltage waveform with a positive slope, that is, a reference signal, due to the charging of the second capacitor C2 by the driving voltage source VDD. When the voltage value of the reference signal increases from zero, the NPN type bipolar transistor Q3 is turned on first, and the base voltage of the PNP type bipolar transistor Q2 drops, so that the PNP type bipolar transistor Q2 is turned on. The gate voltage of the N-type metal oxide semiconductor field effect transistor Q1n rises and is turned on together, that is, the switch unit 12 is turned on. The first capacitor C1 starts to be charged, so that the voltage of the first capacitor C1 increases.

When the rising slope of the voltage of the first capacitor C1 exceeds the rising slope of the reference signal, the PNP bipolar transistor Q3 will be turned off, and the NPN bipolar transistor Q2 will be turned off, thereby limiting the NMOS field The gate voltage of the effect transistor Q1n. Since the impedance of the NMOS transistor Q1n is affected by the voltage difference between the gate and the source (ie, the gate-source voltage), when the gate of the NMOS transistor Q1n is When the voltage rise of the first capacitor C1 is smaller than the voltage rise of the first capacitor C1 , the impedance of the NMOS transistor Q1n increases, and the voltage rise speed of the first capacitor C1 decreases. When the voltage value of the reference signal exceeds the voltage value of the voltage source Vs, the NPN bipolar transistor Q3, the PNP bipolar transistor Q2 and the NMOS field effect transistor Q1n will be completely turned on in succession.

Therefore, by feeding back the voltage of the first capacitor C1 to the feedback control unit 14 and comparing it with the voltage waveform of the reference signal generated by the reference signal generating unit 18 , the action of the switching unit 12 can be controlled, thereby controlling the voltage of the first capacitor C1 The rising slope can achieve the effect of suppressing the inrush current.

Please refer to FIG. 4 . FIG. 4 is a block diagram illustrating a circuit for suppressing inrush current according to a fourth embodiment of the present invention. The circuit 1d is similar to the circuit 1c except for the reference signal generating unit 18 .

In the fourth embodiment, the reference signal generating unit 18 includes a second capacitor C2 and a current source Is. A first end of the second capacitor C2 is grounded, and a second end of the second capacitor C2 is coupled to the reference signal input end of the feedback control unit 14 . The current source Is is coupled to the second end of the second capacitor C2. In other words, in this embodiment, the second capacitor C2 is charged by the current source Is to generate the reference signal.

Please refer to FIG. 5 , which is a block diagram of a circuit for suppressing inrush current according to a fifth embodiment of the present invention. The circuit 1e is similar to the circuit 1b, and uses the voltage across the first terminal and the second terminal of the switch unit 12 as the feedback signal. The fifth embodiment is a further specific embodiment of the second embodiment, the details of which are described below.

The reference signal generating unit 18 includes a second capacitor C2 and a first resistor R1. A first end of the second capacitor C2 is coupled to a driving voltage source VDD. A second end of the second capacitor C2 is coupled to a first end of the first resistor R1 and the reference signal input end of the feedback control unit 14 . A second end of the first resistor R1 is grounded.

The feedback control unit 14 includes a PNP type bipolar transistor Q2 and an NPN type bipolar transistor Q3. An emitter of the PNP bipolar transistor Q2 is coupled to the driving voltage source VDD. A collector of the PNP bipolar transistor Q2 is coupled to the third terminal of the switch unit 12 through a second resistor R2. A base of the PNP bipolar transistor Q2 is coupled to a first end of a third resistor R3.

A collector of the NPN bipolar transistor Q3 is coupled to a second end of the third resistor R3. An emitter of the NPN bipolar transistor Q3 is used as a reference signal input terminal of the feedback control unit 14 and is coupled to the reference signal generating unit 18 . A base of the NPN bipolar transistor Q3 is used as the feedback signal input terminal of the feedback control unit 14 and is coupled to the output port of the voltage coupling unit 16 .

The voltage coupling unit 16 includes an operational amplifier OP. A non-inverting input terminal of the operational amplifier OP is coupled to the first terminal of the switch unit 12 through a fourth resistor R4. An inverting input terminal of the operational amplifier OP is coupled to the second terminal of the switch unit 12 through a fifth resistor R5. An output terminal of the operational amplifier OP is coupled to the inverting input terminal of the operational amplifier OP through a sixth resistor R6. The output terminal of the operational amplifier OP serves as the output port of the voltage coupling unit 16 and is coupled to the base of the NPN bipolar transistor Q3 of the feedback control unit 14 . In addition, the non-inverting input terminal of the operational amplifier OP is further coupled to a compensation voltage source Voffset through a seventh resistor R7.

In the fifth embodiment, since the voltage difference between the first end and the second end of the switch unit 12 is large initially, the NPN bipolar transistor Q3 is turned on, thereby making the PNP bipolar transistor turn on. The crystal Q2 and the N-type metal-oxide-semiconductor field-effect transistor Q1n are jointly turned on. When the voltage of the first capacitor C1 rises, the voltage difference between the first terminal and the second terminal of the switch unit 12 decreases, so that the NPN bipolar transistor Q3 and the PNP bipolar transistor Q2 are turned off successively , thereby increasing the impedance of the N-type metal oxide semiconductor field effect transistor Q1n and suppressing the rising slope of the voltage of the first capacitor C1.

Please refer to FIG. 6 , which is a block diagram of a circuit for suppressing inrush current according to a sixth embodiment of the present invention. Compared with the above-mentioned embodiments, the circuit 1f has a similar working principle, but the switch unit 12 is realized by using a P-type metal-oxide-semiconductor field effect transistor. Therefore, the remaining unit components of the circuit 1f will be different from those of the above-mentioned embodiments, and the details will be described below.

The switch unit 12 includes a P-type MOS transistor Q1p and a diode D1. A source of the PMOS transistor Q1p is used as the first terminal of the switch unit 12 to be coupled to the voltage source Vs. A drain of the P-MOS transistor Q1p is used as the second terminal of the switch unit 12 to be coupled to the first capacitor C1. A gate of the PMOS transistor Q1p is used as the third terminal of the switch unit 12 and is coupled to the feedback control unit 14 . The diode D1 is coupled between the source electrode and the drain electrode of the PMOS transistor Q1p to prevent the PMOS transistor Q1p from being damaged.

The reference signal generating unit 18 includes a second capacitor C2, a first resistor R1, a first voltage dividing resistor Rs1 and a second voltage dividing resistor Rs2. A first end of the second capacitor C2 is grounded, and a second end of the second capacitor C2 is coupled to the reference signal input end of the feedback control unit 14 . A first end of the first resistor R1 is coupled to a first end of the first voltage dividing resistor Rs1 and a first end of the second voltage dividing resistor Rs2, and a second end of the first resistor R1 is coupled to the second The second terminal of capacitor C2. A second end of the first voltage dividing resistor Rs1 is coupled to the voltage source Vs. A second end of the second voltage dividing resistor Rs2 is grounded. In this embodiment, the reference signal generating unit 18 divides the voltage source Vs through the first voltage dividing resistor Rs1 and the second voltage dividing resistor Rs2 to charge the second capacitor C2, and uses the voltage of the second capacitor C2 output as a reference signal.

The feedback control unit includes a PNP type bipolar transistor Q2 and an NPN type bipolar transistor Q3. An emitter of the PNP bipolar transistor Q2 is coupled to the reference signal generating unit 18 as a reference signal input terminal of the feedback control unit 14 . A base of the PNP bipolar transistor Q2 is used as the feedback signal input end of the feedback control unit 14 and is coupled to the output port of the voltage coupling unit 16 . A collector of the PNP bipolar transistor Q2 is coupled to a first end of a second resistor R2.

One emitter of the NPN bipolar transistor Q3 is grounded. A base of the NPN bipolar transistor Q3 is coupled to a second end of the second resistor R2. A collector of the NPN bipolar transistor Q3 is used as the output end of the feedback control unit 14 to be coupled to the third end of the switching unit 12 through a first Zener diode ZD1, and the NPN bipolar transistor Q3 is The collector is coupled to the emitter of the NPN bipolar transistor Q3 through a third resistor R3 and is grounded.

The voltage coupling unit 16 includes a third voltage dividing resistor Rs3 and a fourth voltage dividing resistor Rs4. A first end of the third voltage dividing resistor Rs3 is coupled to the second end of the switch unit 12 as an input port of the voltage coupling unit 16 . A second end of the third voltage dividing resistor Rs3 serves as the output port of the voltage coupling unit 16 and is coupled to the feedback signal input end of the feedback control unit 14 . A first end of the fourth voltage dividing resistor Rs4 is coupled to a second end of the third voltage dividing resistor Rs3. A second end of the fourth voltage dividing resistor Rs4 is grounded. In other words, in this embodiment, the voltage coupling unit 16 is coupled to the feedback control unit 14 by dividing the voltage of the first capacitor C1 .

Generally speaking, the driving voltage of the P-type MOS transistor is lower than that of the N-type MOS transistor. Therefore, the sixth embodiment can make the circuit 1f operate normally without using a high-voltage driving voltage source (eg, the driving voltage source VDD). In other words, in the circuit 1f, the P-type MOS transistor Q1p can be turned on using a lower driving voltage.

In addition, in order to protect the switch unit 12 , the circuit 1f further includes a switch protection unit 20 . The switch protection unit 20 includes a second Zener diode ZD2 and a protection resistor Rp. The second Zener diode ZD2 is coupled between the first end and the third end of the switch unit 12 . The protection resistor Rp is coupled between the first terminal and the third terminal of the switch unit 12 .

Please refer to FIG. 7 . FIG. 7 is a measurement waveform diagram of a circuit for suppressing inrush current according to a third embodiment of the present invention. The arrow 1 on the left vertical axis indicates the gate-source voltage waveform of the N-type metal oxide semiconductor field effect transistor Q1n of the switching unit 12, the arrow 2 indicates the voltage waveform of the first capacitor C1, and the arrow 4 indicates is the current waveform of the first capacitor C1. The horizontal axis is time, and a large scale is 10ms. For the gate-source voltage waveform of the N-type metal oxide semiconductor field effect transistor Q1n of the switching unit 12, the vertical axis coordinate is the voltage, and the one-scale scale is 2.5V. For the voltage waveform of the first capacitor C1, the vertical axis coordinate is the voltage, and a large scale is 2V. For the current waveform of the first capacitor C1, the coordinate of the vertical axis is the current, and a large scale is 5A.

It can be seen from FIG. 7 that with the embodiment of the present invention, the gate-source voltage of the N-type metal oxide semiconductor field effect transistor Q1n of the switching unit 12 reaches full turn-on for 40ms (the middle plateau accounts for more than 95% of the voltage) the overall switch on-time). The charging time of the first capacitor C1 is effectively prolonged (ie, the voltage rising slope of the first capacitor C1 is controlled), and the peak value of the inrush current is suppressed to a maximum of 13.3A.

According to an embodiment of the present invention, the circuit for suppressing inrush current can feed back the voltage of the first capacitor or the voltage difference between the first terminal and the second terminal of the switch unit as a feedback signal to the feedback control unit. The feedback control unit controls the switching unit on and off according to the feedback signal and the reference signal generated by the reference signal generating unit, and adjusts the charging time of the first capacitor, thereby achieving the effect of suppressing the surge current.

Of course, the present invention can also have other various embodiments, without departing from the spirit and essence of the present invention, those skilled in the art can make various corresponding changes and modifications according to the present invention, but these corresponding Changes and deformations should belong to the protection scope of the appended claims of the present invention.

Claims (3)

1. A circuit for suppressing an inrush current, comprising:

the switch unit is provided with a first end, a second end and a third end, wherein the first end of the switch unit is used for being coupled to a voltage source, and the second end of the switch unit is used for being coupled to a first capacitor;

a feedback control unit having a feedback signal input terminal, a reference signal input terminal and an output terminal, the output terminal of the feedback control unit being coupled to the third terminal of the switch unit;

a voltage coupling unit having an input port and an output port, wherein the input port of the voltage coupling unit is coupled to the second terminal of the switch unit, and the output port of the voltage coupling unit is coupled to the feedback signal input terminal of the feedback control unit; and

a reference signal generating unit coupled to the reference signal input terminal of the feedback control unit;

wherein the switch unit comprises an NMOS transistor having a drain, a source and a gate, the drain of the NMOS transistor is coupled to the voltage source, the source of the NMOS transistor is coupled to the first capacitor, and the gate of the NMOS transistor is coupled to the output of the feedback control unit; and

the feedback control unit includes:

a PNP bipolar transistor, wherein an emitter of the PNP bipolar transistor is coupled to a driving voltage source, a collector of the PNP bipolar transistor is coupled to the third terminal of the switch unit through a second resistor, and a base of the PNP bipolar transistor is coupled to a first terminal of a third resistor; and

a collector of the NPN bipolar transistor is coupled to a second end of the third resistor, an emitter of the NPN bipolar transistor is coupled to the output port of the voltage coupling unit, and a base of the NPN bipolar transistor is coupled to the reference signal generating unit.

2. The circuit for suppressing an inrush current as claimed in claim 1, wherein the reference signal generating unit comprises:

a second capacitor, a first end of the second capacitor is grounded, and a second end of the second capacitor is coupled to the reference signal input end of the feedback control unit; and

a first resistor, a first end of which is coupled to the driving voltage source, and a second end of which is coupled to the second end of the second capacitor.

3. The circuit for suppressing an inrush current as claimed in claim 1, wherein the reference signal generating unit comprises:

a second capacitor, a first end of the second capacitor is grounded, and a second end of the second capacitor is coupled to the reference signal input end of the feedback control unit; and

a current source coupled to the second terminal of the second capacitor.

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