CN109728024A - A kind of phase change memory structure based on silicon-on-insulator process - Google Patents
A kind of phase change memory structure based on silicon-on-insulator process Download PDFInfo
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- 239000000377 silicon dioxide Substances 0.000 claims description 7
- FGBDHWCTPQKBDF-UHFFFAOYSA-N antimony scandium Chemical compound [Sc].[Sb] FGBDHWCTPQKBDF-UHFFFAOYSA-N 0.000 claims description 4
- 229910052714 tellurium Inorganic materials 0.000 claims description 4
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- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 claims 2
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Abstract
This hair provides a kind of phase change memory structure based on silicon-on-insulator process, belongs to technical field of semiconductors, comprising: insulator layer；Deposition substrate；Well region；Multiple memory cells are formed on N-shaped well region and constitute memory cell array, by shallow trench isolation between multiple memory cells of same a line, by deep trench isolation between multiple memory cells of adjacent rows；Memory cell is made of the storage section being located above and underlying gate unit, and gate unit includes that from top to bottom sequentially connected top electrodes, coating, phase-change material, electric heating electrode and contact hole, storage section are PN junction structure；Multiple wordline connect the memory cell with a line；Multiple bit lines connect the memory cell of same row.Beneficial effects of the present invention: phase change memory structure processing step and complexity based on silicon-on-insulator process are reduced.
Description
Technical field
The present invention relates to technical field of semiconductors more particularly to a kind of phase transition storage knots based on silicon-on-insulator process
Structure.
Background technique
Silicon-on-insulator (Silicon On Insulator, SOI) soi process refers in semiconductor fabrication
Traditional silicon substrate, especially microelectronics are replaced using layering silicon-on-insulator-silicon substrate, to reduce parasitic device capacitance, to mention
High-performance.Advantage is can be easier to promote clock pulse, and reduce IC of the current leakage as power saving, and portion can also be omitted in technique
Mask is divided to save cost, no matter therefore having its advantage in technique or on circuit.
Fully- depleted silicon-on-insulator (fully-depleted silicon-on-insulator, FD-SOI) is will to insulate
Silicon carries out the processing of fully- depleted channel on body, more optimizes the performance of the silicon-on-insulator including leakage current.
Phase transition storage (Phase-change memory, PCM) is a kind of non-volatile memory device.Stochastic parameter
It accesses memory (parameter random access memory, PRAM) and uses the glass containing one or more chalkogenides
(Chalcogenide glass) is made, and current mainstream is GeSbTe system alloy.The characteristic of chalcogen glass is, can via heating
To change its state, become crystal (Crystalline) or noncrystal (Amorphous).These different conditions have corresponding
Resistance value.Therefore PRAM can be used to store different numerical value.It is may to replace one of technology of flash memory in future.
The introduction cost of fully- depleted silicon-on-insulator process is lower than fin field effect pipe, while being capable of providing fine low function
Consumption and high-performance experience；At present, the design cost of fully- depleted silicon-on-insulator process is lower than fin field effect pipe；As penetrating
Frequently, embedded non-volatile memory is such will be more efficient using fully- depleted silicon-on-insulator process.
Summary of the invention
Aiming at the problems existing in the prior art, the present invention relates to a kind of phase transition storages based on silicon-on-insulator process
Structure.
The present invention adopts the following technical scheme:
A kind of phase change memory structure based on silicon-on-insulator process, comprising:
Wafer substrate；
Insulating layer, Yu Suoshu wafer substrate upper surface deposit megohmite insulant and generate the insulating layer；
Deposition substrate, Yu Suoshu insulating layer upper surface depositing n-type silicon generate the deposition substrate；
N-shaped well region, Yu Suoshu deposition substrate top doping p-type impurity forms the N-shaped well region, under the N-shaped well region
Surface is higher than the lower surface of the deposition substrate；
Multiple memory cells, the multiple memory cell be formed on the N-shaped well region and constitute have multirow and
The memory cell array of multiple row, by the upper table along the N-shaped well region between multiple memory cells of same a line
The shallow trench extended to inside the N-shaped well region downwards is isolated, positioned at multiple memory cells of adjacent rows
Between inside the insulating layer and be lower than the following table of the deposition substrate by extending downwardly into along the upper surface of the deposition substrate
The deep trench in face is isolated；
The memory cell is made of the storage section being located above and underlying gate unit, the strobe portion
Divide including from top to bottom sequentially connected top electrodes, coating, phase-change material, electric heating electrode and contact hole, the contact
Hole extends to the upper surface in the p-type doping area of the memory cell from top to bottom, and electric heating electrode one end connects the phase
Become material, the inner wall of the contact hole is arranged in the other end, and the storage section includes the p-type connecting with the contact hole
Doped region and the N-shaped well region below the p-type doping area, the p-type doping area is by being located at the adjacent institute with a line
It is formed after stating the top doped p type impurity of the N-shaped well region between shallow trench, the p-type doping area and the N-shaped well region structure
At PN junction diode；
Multiple wordline connection units, each wordline connection unit are respectively formed in the deposition substrate and are located at institute
State the outside of the memory cell of every a line outermost end of memory cell array；
Multiple wordline, each wordline is separately connected a wordline connection unit, and connects list by the wordline
Member connection is located at the deposition substrate of all memory cells of same row；
Multiple bit lines, each bit line are separately connected the top of all memory cells positioned at same row
Electrode.
Preferably, the doping concentration in the p-type doping area is greater than the doping concentration of the N-shaped well region.
Preferably, the shallow trench is formed by shallow trench processes.
Preferably, the wordline connection unit includes:
Two connection grooves, described two connection ditch slot positions are in the every a line outermost end for being located at the memory cell array
The outside of the memory cell lean on and by being extended downwardly into inside the N-shaped well region along the upper surface of the N-shaped well region
The connection groove of the nearly memory cell side is a shallow trench of the memory cell；
Substrate is connected, the connection substrate is located at the deposition substrate upper surface between the adjacent connection groove；
At least one connection through-hole, at least one described connection through-hole are sequentially connected from top to bottom, at least one described company
It connects between hole and is connected by conductive material, and the connection through-hole of bottommost extends to the connecting doped area from top to bottom
Upper surface, the connection through-hole of top connects with the corresponding wordline.
Preferably, the gate unit further include:
4th insulating layer, the bit line are arranged in the 4th insulating layer；
Third insulating layer, the third insulating layer are arranged below the 4th insulating layer, the third insulating layer it is upper
The following table face contact on surface and the 4th insulating layer, the top electrodes, the coating and phase-change material are arranged in institute
It states inside third insulating layer；
Second insulating layer, the second insulating layer are arranged below the third insulating layer, the second insulating layer it is upper
The following table face contact on surface and the third insulating layer, the electric heating electrode is through the second insulating layer and extends to described connect
In contact hole；
First insulating layer, first insulating layer are arranged below the second insulating layer, first insulating layer it is upper
The following table face contact on surface and the second insulating layer, the lower surface of first insulating layer and the p for stating memory cell
The contact of type doped region upper surface.
Preferably, first insulating layer, the third insulating layer and the 4th insulating layer are all made of silica
Material.
Preferably, the second insulating layer uses silicon nitride material.
Preferably, the electric heating electrode uses titanium nitride material.
Preferably, the phase-change material includes Ge-Sb-Te；And/or
The phase-change material includes Ge-Sb-Te scandium antimony tellurium phase-change material.
Preferably, silica material is filled in the shallow trench.
Beneficial effects of the present invention: existed using what gate diode replaced equally making in deposition substrate including metal-oxide-semiconductor
Interior transistor completes control action, and which reduces the phase change memory structure processing steps based on silicon-on-insulator process
And complexity, while can also complete corresponding function.
Detailed description of the invention
Fig. 1 is one resistance junction composition of a gate tube in a preferred embodiment of the present invention；
Fig. 2 is substrat structure schematic diagram in a preferred embodiment of the present invention；
Fig. 3 is former silicon on insulated substrate schematic diagram in the prior art；
Fig. 4 is former silicon-on-insulator contact portion schematic diagram in the prior art；
Fig. 5 is multiple gate tube schematic diagram in a preferred embodiment of the present invention；
Fig. 6 is multiple one electric resistance structure storage array of the gate tube signal in a preferred embodiment of the present invention
Figure；
Fig. 7 is the knot of the phase change memory structure based on silicon-on-insulator process in a preferred embodiment of the present invention
One of structure schematic diagram；
Fig. 8 is the knot of the phase change memory structure based on silicon-on-insulator process in a preferred embodiment of the present invention
The two of structure schematic diagram.
Specific embodiment
It should be noted that in the absence of conflict, following technical proposals be can be combined with each other between technical characteristic.
A specific embodiment of the invention is further described with reference to the accompanying drawing:
As shown in Fig. 1-2,5-8, a kind of phase change memory structure based on silicon-on-insulator process, comprising:
Wafer substrate, the material type (not shown) of script wafer；
Insulating layer 20, Yu Suoshu wafer substrate upper surface deposit megohmite insulant and generate the insulating layer 20, to serve as a contrast in wafer
The layer of silicon dioxide insulating layer of growth (or being expressed as depositing, under) on bottom；
Deposition substrate 1,20 upper surface depositing n-type silicon of Yu Suoshu insulating layer generate the deposition substrate 1, in insulating layer 20
The n-type silicon that upper deposit generates；
N-shaped well region 2,1 top of Yu Suoshu deposition substrate doping p-type impurity form the N-shaped well region 2, the N-shaped well region 2
Lower surface be higher than the deposition substrate 1 lower surface, be the area gate tube n, deposit substrate 1 on adulterate n type impurity of the same race
It is formed；
Multiple memory cells, above-mentioned multiple memory cells be formed on above-mentioned N-shaped well region 2 and constitute have multirow and
The memory cell array of multiple row, by the upper table along above-mentioned N-shaped well region 2 between multiple above-mentioned memory cells of same a line
The shallow trench 4 extended to inside above-mentioned N-shaped well region 2 downwards is isolated, positioned at multiple above-mentioned memory lists of adjacent rows
By extending downwardly into above-mentioned 20 inside of insulating layer along the upper surface of above-mentioned deposition substrate 1 and lower than above-mentioned deposition substrate 1 between member
The deep trench 15 of lower surface be isolated；
Above-mentioned memory cell is made of the storage section being located above and underlying gate unit, above-mentioned storage unit
Divide including from top to bottom sequentially connected top electrodes 6 (TEC), coating 7 (capping layer), phase-change material 8, electric heating
Electrode 9 and contact hole 10 (CT), above-mentioned contact hole 10 extend to the p-type doping area 3 of above-mentioned memory cell from top to bottom
Upper surface, above-mentioned 9 one end of electric heating electrode connect above-mentioned phase-change material 8, and the inner wall of above-mentioned contact hole 10 is arranged in the other end, above-mentioned
Gate unit includes the above-mentioned p-type doping area 3 connecting with above-mentioned 10 hole of contact and the above-mentioned n positioned at above-mentioned 3 lower section of p-type doping area
Type well region 2, above-mentioned p-type doping area 3 by be located at the above-mentioned N-shaped well region 2 between the adjacent above-mentioned shallow trench 4 of a line top into
It is formed after row transoid doping i.e. doped p type impurity, the upper surface in above-mentioned p-type doping area 3 and the upper surface of above-mentioned N-shaped well region 2 are neat
The upper surface in flat or above-mentioned p-type doping area 3 is ok lower than the upper surface of above-mentioned N-shaped well region 2, as long as contact hole 10 is mixed with p-type
Miscellaneous to go 3 to contact, above-mentioned p-type doping area 3 and above-mentioned N-shaped well region 2 constitute PN junction diode；
P-type doping area 3 is the area gate tube p, partially carries out transoid doping in the area the gate tube n, mixes p type dopant,
The area p is formed, the area n and the area p interface form pn-junction, and the area n and the area p constitute gate diode, doping type here, N-shaped and p-type
Cannot exchange because diode has unilateral conduction, can only p-type layer upper, n-layer is deposit under, below n-layer
Substrate 1, p-type impurity Chinese are known as donor-type impurities, and n-type doping is known as mixing donor impurity, and similarly, n-type impurity is known as acceptor type
Impurity, p-type doping are known as mixing acceptor-type impurities；
Multiple wordline connection units, each above-mentioned wordline connection unit are respectively formed in above-mentioned deposition substrate 1 and are located at
The outside of the above-mentioned memory cell of every a line outermost end of above-mentioned memory cell array；
Multiple wordline 19, each above-mentioned wordline 19 is separately connected an above-mentioned wordline connection unit, and is connected by above-mentioned wordline
The connection of order member is located at the above-mentioned deposition substrate 1 of all above-mentioned memory cells of same row, and wordline 19 is second layer metal；
Multiple bit lines 5, each above-mentioned bit line 5 are separately connected the above-mentioned of all above-mentioned memory cells positioned at same row
Top electrodes 6, bit line 5 are first layer metal, and first layer metal is located at below second layer metal.
As shown in Figure 3-4, former silicon on insulated substrate be use metal-oxide-semiconductor is made in deposition substrate 1, then realize the phase
The function of prestige and certain performance.It is to adulterate N-shaped ion, the second conduction type as doped p type ion to be using the first conduction type
Example, the present invention are that technical inject on N-shaped well region 2 without n of silicon on insulator is adulterated, and carry out p-type doping, n instead
Type well region 2 and p-type doping area constitute PN junction, form diode, and the diode of formation has gate action, that is, the gating can be used
The transistor including metal-oxide-semiconductor that diode in place equally makes in deposition substrate 1 completes control action, thus reduces
Processing step and complexity, while can also complete corresponding function.
Specifically, Fig. 1 is corresponding one resistance of a gate tube of phase change memory structure based on silicon-on-insulator process
Structural schematic diagram, memory cell are divided into storage section and gate unit, and top is divided into storage section structure, using phase-change material
8 serve as memory carrier, with amorphous state are connected to or block being connected up to pair for circuit using its phase-change material (such as N-GST) crystalline state
The function of read-write or the preservation of data, lower part are divided into the silicon on insulated substrate PN junction structure of the production in deposition substrate 1, make
Use diode as the gate unit of memory, to constitute one electric resistance structure of a gate diode.
Fig. 2 is partial structure diagram under specific Fig. 1, can see that in Fig. 2 and has carried out p-type on substrate N-shaped well region 2
Doping, thus just constitutes PN junction, surrounding is isolated with the insulating layer that shallow trench 4 is constituted, and electric current just can only be from upper and lower ends
It circulates.In conjunction with Fig. 2, when Fig. 1 carries out write-in data in the position, opening following gate tube by voltage control makes data
Pass through, then so that the phase-change material 8 of upper part is changed into low resistive state by heating means and data deposit is then powered off lower section
Gate tube and change phase-change material 8 property carry out data preservation.
As shown in figure 5, be the schematic diagram that the single-row layout for the PN junction to be formed only is adulterated to progress transoid on N-shaped well region 2,
It is separated between the PN junction of each formation with the isolation of shallow trench 4, the gate diode connected with a piece of substrate area is total
With one bit line control road of composition, adjacent substrate region carries out deep trench 15 and is isolated, as shown in fig. 6, being a multiple gating
The schematic diagram of the storage array of one electric resistance structure of pipe composition.
Various substrates region carries out the isolation of deep trench 15 on the basis of Fig. 5, it is ensured that a piece of substrate area only carries out accordingly
The control of gate tube constitutes wordline 19 both perpendicular to metal connecting line is carried out above the memory cell in the direction of substrate connection,
By the control of wordline 19 perpendicular to the memory cell in 5 direction of bit line, in this way, when needing to read specific memory cell
When write operation, controlled by wordline 19 between different layers and bit line 5, ensure that only to individual memory cell into
Row read-write only not can be achieved with read-write operation with diode and phase-change material 8 by transistor on silicon-on-insulator
Memory function.
In preferred embodiment, the doping concentration in above-mentioned p-type doping area 3 is greater than the doping concentration of above-mentioned N-shaped well region 2.
In preferred embodiment, above-mentioned shallow trench 4 is formed by shallow trench processes.
In preferred embodiment, above-mentioned wordline connection unit includes:
Two connection grooves 16, above-mentioned two connection groove 16 are located at every a line of above-mentioned memory cell array most
The outside of the above-mentioned memory cell of outer end, and by being extended downwardly into above-mentioned N-shaped well region 2 along the upper surface of above-mentioned N-shaped well region 2
Portion, the above-mentioned connection groove 16 close to above-mentioned memory cell side are an above-mentioned shallow trench 4 of above-mentioned memory cell；
Substrate 17 is connected, above-mentioned connection substrate 17 is located at 1 top of above-mentioned deposition substrate between adjacent above-mentioned connection groove 16,
It is identical as the connection of deposition substrate 1 and material to connect substrate 17；
At least one connection through-hole 18 (CT), it is above-mentioned at least one connection through-hole 18 be sequentially connected from top to bottom, it is above-mentioned extremely
It is extended to from top to bottom between few connection through-hole 18 by the above-mentioned connection through-hole 18 of conductive material connection and bottommost
The upper surface of connection substrate 17 is stated, the above-mentioned connection through-hole 18 of top is connected with corresponding above-mentioned wordline 19.
In the present embodiment, between the above-mentioned memory cell that same above-mentioned wordline 19 connects using shallow slot technique carry out every
From above-mentioned N-shaped well region 2 keeps connection；Between the above-mentioned memory cell that same above-mentioned bit line 5 connects using deep trench processes into
Row isolation, above-mentioned N-shaped well region 2 are not connected.
Above-mentioned bit line 5 is connected to above-mentioned 8 side of phase-change material, is not connected directly with above-mentioned gate diode；It is above-mentioned
Wordline 19 is connected by connecting through-hole 18 with above-mentioned deposition substrate 1, passes through above-mentioned N-shaped well region 2 and above-mentioned gate diode phase
Connection.
In preferred embodiment, above-mentioned gate unit further include:
4th insulating layer 14, above-mentioned bit line 5 are arranged in above-mentioned 4th insulating layer 14；
Third insulating layer 13, above-mentioned third insulating layer 13 are arranged below above-mentioned 4th insulating layer 14, above-mentioned third insulation
The upper surface of layer 13 and the following table face contact of above-mentioned 4th insulating layer 14, above-mentioned top electrodes 6, above-mentioned coating 7 and phase transformation
Material 8 is arranged inside above-mentioned third insulating layer 13；
Second insulating layer 12, above-mentioned second insulating layer 12 are arranged below above-mentioned third insulating layer 13, above-mentioned second insulation
The upper surface of layer 12 and the following table face contact of above-mentioned third insulating layer 13, above-mentioned electric heating electrode 9 run through above-mentioned second insulating layer 12
And it extends in above-mentioned contact hole 10；
First insulating layer 11, above-mentioned first insulating layer 11 are arranged below above-mentioned second insulating layer 12, above-mentioned first insulation
The upper surface of layer 11 and the following table face contact of above-mentioned second insulating layer 12, the lower surface of above-mentioned first insulating layer 11 and state memory
Above-mentioned 3 20 upper surface of p-type doping area of unit contacts, and above-mentioned contact hole 10 is simultaneously downward through above-mentioned contact hole 10 from top to bottom
Extend to the upper surface in above-mentioned p-type doping area 3.
In preferred embodiment, above-mentioned first insulating layer 11, above-mentioned third insulating layer 13 and above-mentioned 4th insulating layer 14
It is all made of silica material.
In preferred embodiment, above-mentioned second insulating layer 12 uses silicon nitride material.
In preferred embodiment, above-mentioned 7 material of coating can be GeCrN ZnS-SiO2；
Above-mentioned electric heating electrode 9 is all made of titanium nitride material.
In preferred embodiment, above-mentioned phase-change material 8 includes Ge-Sb-Te；And/or
Above-mentioned phase-change material 8 includes Ge-Sb-Te scandium antimony tellurium phase-change material 8.
In the present embodiment, phase-change material includes singly being not limited to Ge-Sb-Te and scandium antimony tellurium phase-change material.
In preferred embodiment, silica material is filled in above-mentioned shallow trench 4.
In preferred embodiment, bit line 5 and wordline 19 are all made of copper material.
By description and accompanying drawings, the exemplary embodiments of the specific structure of specific embodiment are given, based on present invention essence
Mind can also make other conversions.Although foregoing invention proposes existing preferred embodiment, however, these contents are not intended as
Limitation.
For a person skilled in the art, after reading above description, various changes and modifications undoubtedly be will be evident.
Therefore, appended claims should regard the whole variations and modifications for covering true intention and range of the invention as.It is weighing
The range and content of any and all equivalences, are all considered as still belonging to the intent and scope of the invention within the scope of sharp claim.
Claims (10)
1. a kind of phase change memory structure based on silicon-on-insulator process characterized by comprising
Wafer substrate；
Insulating layer, Yu Suoshu wafer substrate upper surface deposit megohmite insulant and generate the insulating layer；
Deposition substrate, Yu Suoshu insulating layer upper surface depositing n-type silicon generate the deposition substrate；
N-shaped well region, Yu Suoshu deposition substrate top doping p-type impurity form the N-shaped well region, the lower surface of the N-shaped well region
Higher than the lower surface of the deposition substrate；
Multiple memory cells, the multiple memory cell, which is formed on the N-shaped well region and constitutes, has rows and columns
Memory cell array, between multiple memory cells of same a line from the upper surface along the N-shaped well region to
Under the shallow trench that extends to inside the N-shaped well region be isolated, between multiple memory cells of adjacent rows
By extending downwardly into the lower surface inside the insulating layer and lower than the deposition substrate along the upper surface of the deposition substrate
Deep trench is isolated；
The memory cell is made of the storage section being located above and underlying gate unit, the storage unit subpackage
Include from top to bottom sequentially connected top electrodes, coating, phase-change material, electric heating electrode and contact hole, the contact hole by
Top to bottm extends to the upper surface in the p-type doping area of the memory cell, and electric heating electrode one end connects the phase transformation material
The inner wall of the contact hole is arranged in material, the other end, and the gate unit includes the p-type doping connecting with the contact hole
Area and the N-shaped well region below the p-type doping area, the p-type doping area is by being located at the adjacent described shallow of a line
It is formed after the top doped p type impurity of the N-shaped well region between groove, the p-type doping area and the N-shaped well region constitute PN
Junction diode；
Multiple wordline connection units, each wordline connection unit are respectively formed in the deposition substrate and are located at described deposit
The outside of the memory cell of every a line outermost end of memory cell array；
Multiple wordline, each wordline is separately connected a wordline connection unit, and is connected by the wordline connection unit
Connect the deposition substrate for being located at all memory cells with a line；
Multiple bit lines, each bit line are separately connected the top electricity of all memory cells positioned at same row
Pole.
2. phase change memory structure according to claim 1, which is characterized in that the doping concentration in the p-type doping area is big
In the doping concentration of the N-shaped well region.
3. phase change memory structure according to claim 1, which is characterized in that form the shallow ridges by shallow trench processes
Slot.
4. phase change memory structure according to claim 1, which is characterized in that the wordline connection unit includes:
Two connection grooves, described two connection ditch slot positions are in the institute for the every a line outermost end for being located at the memory cell array
The outside of memory cell is stated, and by extending downwardly into inside the N-shaped well region along the upper surface of the N-shaped well region, close to institute
The connection groove for stating memory cell side is a shallow trench of the memory cell；
Substrate is connected, the connection substrate is located at the deposition substrate upper surface between the connection groove；
At least one connection through-hole, at least one described connection through-hole are sequentially connected from top to bottom, at least one described connection is logical
It is connected between hole by conductive material, and the connection through-hole of bottommost extends to the upper table of the connection substrate from top to bottom
Face, the connection through-hole of top are connected with the corresponding wordline；.
5. phase change memory structure according to claim 1, which is characterized in that the gate unit further include:
4th insulating layer, the bit line are arranged in the 4th insulating layer；
Third insulating layer, the third insulating layer are arranged below the 4th insulating layer, the upper surface of the third insulating layer
With the following table face contact of the 4th insulating layer, the top electrodes, the coating and phase-change material setting are described the
Inside three insulating layers；
Second insulating layer, the second insulating layer are arranged below the third insulating layer, the upper surface of the second insulating layer
With the following table face contact of the third insulating layer, the electric heating electrode is through the second insulating layer and extends to the contact hole
It is interior；
First insulating layer, first insulating layer are arranged below the second insulating layer, the upper surface of first insulating layer
With the following table face contact of the second insulating layer, the lower surface of first insulating layer is mixed with the p-type for stating memory cell
The contact of the upper surface Za Qu.
6. phase change memory structure according to claim 5, which is characterized in that first insulating layer, the third are exhausted
Edge layer and the 4th insulating layer are all made of silica material.
7. phase change memory structure according to claim 15, which is characterized in that the second insulating layer uses silicon nitride
Material.
8. phase change memory structure according to claim 1, which is characterized in that the electric heating electrode is using nitridation titanium
Matter.
9. phase change memory structure according to claim 1, which is characterized in that the phase-change material includes Ge-Sb-Te；With/
Or
The phase-change material includes Ge-Sb-Te scandium antimony tellurium phase-change material.
10. phase change memory structure according to claim 1, which is characterized in that be filled with titanium dioxide in the shallow trench
Silicon material.
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