CN109727863A

CN109727863A - A kind of AlGan/GaN HEMT device structure and fabrication method based on self-alignment process

Info

Publication number: CN109727863A
Application number: CN201910002433.3A
Authority: CN
Inventors: 林信南; 钟皓天
Original assignee: Peking University Shenzhen Graduate School
Current assignee: Peking University Shenzhen Graduate School
Priority date: 2019-01-02
Filing date: 2019-01-02
Publication date: 2019-05-07

Abstract

The present invention provides a method for fabricating an AlGan/GaN HEMT device based on a self-alignment process, comprising the following steps: after cleaning the wafer, depositing an intermediate buffer layer and GaN, AlGaN and p-GaN on a silicon substrate by MOCVD; and LPCVD process to deposit Mo as gate metal, Ni and SiO _x as etching protection layer; deposit AlO _x as sidewall encapsulation gate metal Mo by PECVD; remove excess AlO by BCl ₃ /Ar ICP-RIE etching process _x ; Selectively etch p-GaN by ICP-RIE process of Cl ₂ /N ₂ /O ₂ ; PVD deposition and annealing process form ohmic contacts of source and drain, remove SiO _x and AlO _x by BOE, and The SiN _x dielectric layer is deposited by the PECVD method to complete the device fabrication. Because the technology and conditions used in the whole device fabrication method are compatible with the Si _CMOS technology, and the process complexity is low and the operability is strong, the contradiction between the device performance and the process complexity is well coordinated.

Description

A kind of AlGan/GaN HEMT device structure and production method based on self-registered technology

Technical field

The present invention relates to the manufacture crafts of semiconductor devices, more particularly to a kind of AlGaN/GaN based on self-registered technology HEMT device structure and production method.

Background technique

In power semiconductor field, GaN material has wide prospect, be highly suitable for preparing high-power, high speed, The power electronic devices of big voltage.AlGaN/GaN HEMT is the wherein most type of device of attraction, can between GaN/AlGaN To form the two-dimensional electron gas (2-DEG) of high electron concentration and high electron mobility, and AlGaN/GaN HEMT device technique Simply, it is suitably based on kinds of platform to be developed, the development cycle is short, at low cost.

It, need to be in the p-GaN of one layer thin of AlGaN layer one thickness of accumulation in AlGaN/GaN HEMT device technical process Layer, and barrier metal layer is prepared on p-GaN, meanwhile, the p-GaN outside area of grid can be removed by dry etching.Due to device The two-dimensional electron gas of part is related with the thickness of p-GaN thickness and AlGaN, and AlGaN layer needs are sufficiently thin, so etching Etching depth should be accurately controlled in during p-GaN, minimizes the influence to AlGaN layer that etching technics may cause, and maintained High electron concentration.

Summary of the invention

The present invention solves the technical problem of the self-registered technologies and correlation using a kind of selective etch p-GaN AlGaN/GaN HEMT device structure improves the selectivity and accuracy of etching p-GaN, optimization AlGaN/GaN HEMT device Grid structure solves the problems, such as that p-GaN grid grade HEMT device is influenced to cause by technique, and reduces processing step and process complexity.

In order to solve the above technical problems, the present invention proposes a kind of AlGan/GaN HEMT device system based on self-registered technology Make method, include the following steps: step 1: after cleaning wafer, GaN and intermediate buffer layer being deposited in silicon substrate by MOCVD AlGaN and p-GaN；Mo is deposited as grid metal, Ni and SiO by PVD and LPCVD process_xAs etch-protecting layer；Step 2: AlO is deposited by PECVD_xAs side wall package grid metal Mo；Step 3: passing through BCl₃The ICP-RIE etching technics removal of/Ar is more Remaining AlO_x；Step 4: passing through Cl₂/N₂/O₂ICP-RIE process selectivity etch p-GaN；Step 5:PVD deposit and it is annealed Journey forms the Ohmic contact of source electrode and drain electrode, removes SiO by BOE_xAnd AlO_x, and SiN is deposited using PECVD method_xMedium Layer completes element manufacturing.

Above-mentioned production method according to the present invention, the present invention also provides a kind of AlGan/GaN HEMT device structure, institutes State structure include substrate, it is buffer layer, intrinsic GaN layer, intrinsic AlGaN layer, p-GaN layer, barrier metal layer, source electrode, drain electrode, blunt Change layer；The p-GaN layer is located on intrinsic AlGaN layer, and source-drain electrode is located on intrinsic AlGaN layer, and barrier metal layer is located at On p-GaN layer；It is epitaxially grown on the substrate enhanced AlGaN/GaN heterojunction material, and is formed on the heterojunction material Source electrode and drain electrode, there are p-GaN epitaxial layers for barrier metal layer lower section, form enhancement device, finally deposit passivation layer and realize device Passivation.

A kind of AlGan/GaN HEMT device structure and production method based on self-registered technology of foundation above-described embodiment, The technique as used in entire device manufacture method and condition are and S_iCMOS technology is compatible, and process complexity is low, can Strong operability has coordinated the contradiction between device performance and process complexity well.

Detailed description of the invention

Fig. 1 is the deposit grid metal and etch-protecting layer step schematic diagram of a kind of embodiment；

Fig. 2 is a kind of deposit AlO of embodiment_xSide wall step schematic diagram；

Fig. 3 is a kind of extra AlO of removal of embodiment_xStep schematic diagram；

Fig. 4 is a kind of etching p-GaN step schematic diagram of embodiment；

Fig. 5 is a kind of completion device fabrication steps schematic diagram of embodiment.

Specific embodiment

Below by specific embodiment combination attached drawing, invention is further described in detail.Wherein different embodiments Middle similar component uses associated similar element numbers.In the following embodiments, many datail descriptions be in order to The application is better understood.However, those skilled in the art can recognize without lifting an eyebrow, part of feature It is dispensed, or can be substituted by other elements, material, method in varied situations.In some cases, this Shen Please it is relevant it is some operation there is no in the description show or describe, this is the core in order to avoid the application by mistake More descriptions are flooded, and to those skilled in the art, these relevant operations, which are described in detail, not to be necessary, they Relevant operation can be completely understood according to the general technology knowledge of description and this field in specification.

It is formed respectively in addition, feature described in this description, operation or feature can combine in any suitable way Kind embodiment.Meanwhile each step in method description or movement can also can be aobvious and easy according to those skilled in the art institute The mode carry out sequence exchange or adjustment seen.Therefore, the various sequences in the description and the appended drawings are intended merely to clearly describe a certain A embodiment is not meant to be necessary sequence, and wherein some sequentially must comply with unless otherwise indicated.

It is herein component institute serialization number itself, such as " first ", " second " etc., is only used for distinguishing described object, Without any sequence or art-recognized meanings.And " connection ", " connection " described in the application, unless otherwise instructed, include directly and It is indirectly connected with (connection).

The term definition used in the application:

1.HEMTs: high electron mobility transistor；

2.CMOS: compensated semiconductor's metal-oxide semiconductor (MOS)；

3.GaN: gallium nitride, a kind of wide bandgap semiconductor compound are the representatives of third generation semiconductor, are very suitable to big function The production of rate and microwave device；

4.PVD: full name Physical Vapor Deposition, physical vapour deposition (PVD) are the most frequently used in semiconductor technology Metal deposit mode；

5.LPCVD: full name Low Pressure Chemical Vapor Deposition, low-pressure chemical vapor deposition, It is one of the major way that high quality dielectric film deposits in semiconductor technology；

6.MOCVD: full name Metal-organic Chemical Vapor Deposition, metallo-organic compound Gaseous phase deposition, a kind of novel vapour phase epitaxy growing technology to grow up on the basis of vapor phase epitaxial growth (VPE), mainly Growth for compound semiconductors such as GaN/SiC；

7.PECVD: full name Plasma Enhanced Chemical Vapor Deposition, plasma enhancing Vapor deposition is learned, is one of the major way that high quality dielectric film deposits in semiconductor technology, is mainly used for last part technology sheath Deposition；

8.BOE: full name Buffered Oxide Etch, buffered oxide etch.

In embodiments of the present invention, using the self-registered technology of selective etch p-GaN a kind of and correlation AlGaN/GaN HEMT device structure improves the selectivity and accuracy of etching p-GaN, optimizes the grid structure of AlGaN/GaN HEMT device, solution Certainly p-GaN grid grade HEMT device is influenced the problem of causing by technique, and reduces processing step and process complexity.

Embodiment one: a kind of AlGan/GaN HEMT device production method based on self-registered technology includes the following steps:

Step 1: as shown in Figure 1, depositing GaN and intermediate buffer layer AlGaN in silicon substrate by MOCVD after cleaning wafer And p-GaN；Mo is deposited as grid metal, Ni and SiO by PVD and LPCVD process_xAs etch-protecting layer；

Step 2: as shown in Fig. 2, depositing AlO by PECVD_xAs side wall package grid metal Mo；

Step 3: as shown in figure 3, passing through BCl₃The ICP-RIE etching technics of/Ar removes extra AlO_x；

Step 4: as shown in figure 4, passing through Cl₂/N₂/O₂ICP-RIE process selectivity etch p-GaN；

Step 5: as shown in figure 5, PVD deposit and annealing process form the Ohmic contact of source electrode and drain electrode, being removed by BOE SiO_xAnd AlO_x, and SiN is deposited using PECVD method_xDielectric layer completes element manufacturing.

Wherein, in step 1 GaN layer with a thickness of 3.2 μm, AlGaN layer with a thickness of 12.5nm, p-GaN layer with a thickness of 80nm, Mo layers with a thickness of 100nm, Ni layers with a thickness of 20nm and SiO_xLayer with a thickness of 300nm.

AlO in step 2_xLayer with a thickness of 50nm.

Cl in step 4₂/N₂/O₂Gas flow is respectively 30,10,3sccm, etch period 5min.

SiN in step 5_xDielectric layer with a thickness of 100nm.

According to the production method of above-described embodiment, pass through Cl₂/N₂/O₂Mixed gas selective removal p-GaN and reduce Etch the influence to AlGaN layer.In self-registered technology, the grid metal of progress gate metal accumulation and p-GaN contact first is same When also as removal p-GaN exposure mask.For the reaction for avoiding grid metal and p-GaN, select Mo as grid metal.Due to Mo vulnerable to Cl₂/O₂Plasma influences, therefore needs in etching process by Mo package.

Completed using the AlGaN/GaN HEMT device of above-mentioned selective etch p-GaN self-registered technology, behind also Multilayer wiring can be carried out as needed.Entirely technique and condition used in device manufacture method are and Si CMOS technology is compatible, And process complexity is low, strong operability, has coordinated the contradiction between device performance and process complexity well.The technique There is higher accuracy, preferable selectivity is etched with to p-GaN, the etching depth of p-GaN can be preferably controlled, solve Problem caused by part p-GaN grid AlGaN/GaN HEMT device is influenced by technique.

Embodiment two:

It according to a kind of available AlGan/GaN HEMT device structure of production method of embodiment one, specifically includes: lining Bottom, buffer layer, intrinsic GaN layer, intrinsic AlGaN layer, p-GaN layer, barrier metal layer, source electrode, drain electrode, passivation layer；The p- GaN layer is located on intrinsic AlGaN layer, and source-drain electrode is located on intrinsic AlGaN layer, and barrier metal layer is located on p-GaN layer； It is epitaxially grown on the substrate enhanced AlGaN/GaN heterojunction material, and forms source electrode and drain electrode, grid on the heterojunction material There are p-GaN epitaxial layers below metal layer, form enhancement device, finally deposit the passivation that passivation layer realizes device.By upper Selectivity and accuracy that production method improves etching p-GaN are stated, the grid structure of AlGaN/GaN HEMT device is optimized, has Effect solves the problems, such as that p-GaN grid grade HEMT device is influenced to cause by technique, reduces processing step and process complexity, and Device possesses good electric property.

Use above specific case is illustrated the present invention, is merely used to help understand the present invention, not to limit The system present invention.For those skilled in the art, according to the thought of the present invention, can also make several simple It deduces, deform or replaces.

Claims

1. a method for making an AlGan/GaN HEMT device based on a self-alignment process, is characterized in that comprising the steps:

Step 1: After cleaning the wafer, deposit GaN and intermediate buffer layers AlGaN and p-GaN on the silicon substrate by MOCVD; deposit Mo as gate metal, Ni and SiO _x as etching protection layer by PVD and LPCVD processes;

Step 2: depositing AlO _x as the sidewall encapsulation gate metal Mo by PECVD;

Step 3: remove excess AlO _x by ICP-RIE etching process of BCl ₃ /Ar;

Step 4: Selectively etch p-GaN through Cl ₂ /N ₂ /O ₂ ICP-RIE process;

Step 5: PVD deposition and annealing process to form ohmic contacts between source and drain electrodes, remove SiO _x and AlO _x by BOE, and deposit SiN _x dielectric layer by PECVD method to complete device fabrication.

2 . The manufacturing method according to claim 1 , wherein in step 1, the thickness of the GaN layer is 3.2 μm, the thickness of the AlGaN layer is 12.5 nm, the thickness of the p-GaN layer is 80 nm, and the thickness of the Mo layer is 80 nm. 3 . is 100 nm, the thickness of the Ni layer is 20 nm, and the thickness of the _SiOx layer is 300 nm.

3 . The manufacturing method according to claim 1 , wherein the thickness of the AlO _x layer in step 2 is 50 nm. 4 .

4 . The manufacturing method according to claim 1 , wherein the Cl ₂ /N ₂ /O ₂ gas flows in step 4 are respectively 30, 10, and 3 sccm, and the etching time is 5 min. 5 .

5 . The manufacturing method of claim 1 , wherein the thickness of the SiN _x dielectric layer in step 5 is 100 nm. 6 .

6. The AlGan/GaN HEMT device structure prepared by the method according to claim 1, wherein the structure comprises a substrate, a buffer layer, an intrinsic GaN layer, an intrinsic AlGaN layer, a p-GaN layer, a gate metal layer, source electrode, drain electrode and passivation layer; the p-GaN layer is located on the intrinsic AlGaN layer, the source and drain electrodes are located on the intrinsic AlGaN layer, and the gate metal layer is located on the p-GaN layer; The enhancement mode AlGaN/GaN heterojunction material is epitaxially grown on the bottom, and the source and drain electrodes are formed on the heterojunction material. There is a p-GaN epitaxial layer under the gate metal layer to form an enhancement mode device, and finally passivation is deposited. layer to achieve passivation of the device.