CN109725249A - A kind of testing process dynamic adjustment method and adjustment system - Google Patents

Abstract

The present invention provides a kind of testing process dynamic adjusting method and adjustment system, including test-types adjustment；The test-types adjustment includes: to calculate test-types to the number summation that should be able to measure bad chip；The corresponding temporal summation of bad chip can be surveyed by calculating test-types；The weight of test-types is calculated according to number summation and temporal summation；It resequences by weight, obtains new test-types sequence.Compared with prior art, the embodiment of the present invention proposes a kind of method that classification dynamic adjusts test-types and test vector, and according to the test result of early period, dynamic adjusts test-types, the test-types of high quality are adjusted to foremost, bad circuit-under-test is allowed to test out earliest.Testing efficiency can be improved, reduce testing cost.

Description

A kind of testing process dynamic adjustment method and adjustment system

technical field

The invention relates to the technical field of integrated circuit testing, in particular to a dynamic adjustment method and adjustment system of a testing process.

Background technique

The traditional integrated circuit test process needs to run different types of tests such as DC test, functional test, I _ddq test, built-in self test, delay test and scan test. Each type of test needs to run multiple test vectors. The time is very long, and the proportion in the entire integrated circuit industry chain is increasing.

In a traditional integrated circuit testing process, the test type loaded for each chip is fixed, and the sequence of test vectors for each test type is also fixed. Without loss of generality, it is assumed that for the test of a certain integrated circuit, the required test types are: Y ₁ , Y ₂ , ..., Y _i , ..., Y _n ; for any test type, it contains several determinations , the loading order of the test vectors is also fixed, without loss of generality, let the test vectors contained in Y _i be: V _i1 , V _i2 , ..., V _ij , ..., V _im . where i, j, n, m are all integers.

The test of integrated circuits is mainly to pick out the bad chips, so the sooner the bad chips are found, the better the test effect will be. In the integrated circuit test before 7, the same process and the same test sequence were used for all the tested circuits, and the correlation between faults was not considered. For the specific circuit under test, high-quality test types and high-quality test vectors are not considered. The order of test types and the order of test vectors are static when testing the circuit under test and do not maximize the test efficiency.

In response to the above problems, the invention patent CN201110317892.4 proposes to dynamically adjust the test vector directly according to the previous test results. The adjustment method is to first record the running times a of a single test vector and the number b of faulty chips measured by the vector, and then pass the number of faulty chips. b/The value of the number of runs of the test vector a, i.e. The size of is used as a weight to adjust the order of the test vectors. There are two problems: 1. When testing an integrated circuit, the faulty integrated circuit is picked out. Therefore, when the integrated circuit is faulty, the testing of the integrated circuit will be stopped, and subsequent test vectors will not be added. Therefore, There may be cases where subsequent high-quality test vectors will never be loaded, that is, there is a possibility that the ordering of test vector quality may not be complete. 2. In the above invention, only the order adjustment between test vectors is considered, and the order of test types is not considered. As the complexity of integrated circuits increases, new test types need to be developed for different circuits, and it is obviously not optimal to just add this new test type to the end.

SUMMARY OF THE INVENTION

The technical problem to be solved by the present invention is to provide a dynamic adjustment method and adjustment system of the test flow, which can improve the test efficiency and reduce the test cost.

The present invention solves the above-mentioned technical problems through the following technical solutions:

A method for dynamic adjustment of test flow, including adjustment of test type;

The test type adjustment includes:

Calculate the total number of times that a single test type can detect bad chips;

Calculate the total time corresponding to a single test type that can detect bad chips;

Calculate the weight of a single test type based on the sum of times and time;

Reorder by weight to get a new sequence of test types.

Preferably, it also includes adjusting the test vector for each test type; each test type includes multiple test vectors; the test vector adjustment is specifically: calculating the weight of a single test vector, and sorting the test vector weights to obtain a new test vector. order of test vectors.

Preferably, the running times corresponding to the test vectors V _i1 , V _i2 , ..., V _ij , ..., V _im for determining the test type Y _i are respectively: T _i1 , T _i2 , ..., T _ij , ... ..., Y _im ; the weight of a single test vector V _ij W _j =N' _ij /T _ij , the value of the weight W _j when calculating j=1, 2, ..., m;

According to the test vectors V _i1 , V _i2 , ..., V _ij , ..., V _im corresponding to the value of the weight W _j , arrange the corresponding test vectors of W _j in descending order to obtain a new test vector V' _i1 , V' _i2 , ..., V' _ij , ..., V' _im .

Preferably, before sorting the test vector, initialize it, specifically:

51) set initialization parameter num, and described num is a positive integer;

52) judge whether the running times of all test vectors are all greater than mum, if not, select the first test vector as the current test vector, and jump to step 53); if so, jump to step 57);

53) advance the current test vector to the front of the test vector, jump to step 54);

54) judge whether there is the next test vector, if so, select the next test vector to be the current test vector, and jump to step 53); if not, jump to step 55);

55) Select the current test vector to test any untested integrated circuit, update the running times of the test vector, determine whether the integrated circuit is faulty, if the integrated circuit is faulty, update the number of faults measured by the test vector , jump to step 52); if the integrated circuit is not faulty, jump to step 56);

56) select the next test vector to be the current test vector, jump to step 55);

57) The initialization ends.

Preferably, it also includes dynamic combination adjustment, specifically:

51) Determine whether there are still integrated circuits that have not been tested, if all the tests have been completed, go to 48);

52) Optionally select a chip to be tested, load the test vectors in sequence according to the sorted test type and test vector, if the chip is tested without failure, repeat step 51); if the chip is tested with failure, go to step 53);

53) Record the corresponding test vectors and test types of integrated circuit failures tested, and accumulate the number of faulty integrated circuits tested by the test vectors;

54) Judging whether the current test vector V″ _ij needs to exchange the order with its previous test vector V″ _i(j-1) , the details are as follows: judging the number of times N″ _ij that the test vector V″ _ij tests to the faulty integrated circuit and the test The magnitude of the number of times N″ _i(j-1) that the vector V″ _i(j-1) tested to the faulty integrated circuit, if N″ _i(j-1) ≥ N″ _ij , there is no need to adjust the order of the vectors, go to Step 51); if N″ _i(j-1) < N″ _ij , exchange the order of the test vector V″ _ij with the test vector V″ _{i (j-1)} in front of it, and exchange the faulty integrated circuits that can be tested at the same time quantity;

55) Judging whether to switch to the previous test vector still needs to continue to be exchanged, specifically: update V″ _i(j-1) to the current test vector, repeat step 54), judge this test vector V″ _{i (j- 1)} Whether it is necessary to exchange with the previous test vector V″ _i(j-2) , if it is not necessary to exchange, go to step 56), if it is necessary to exchange, repeat step 55);

56) Determine whether the current test type Y _i ″ needs to exchange the order with its previous test type Y ″ _i-1 , specifically: calculate the weights of Y _i ″ and Y ″ _i-1 respectively and Compare and size, if Go to step 51), otherwise swap the order of test types Y _i " and Y" _i-1 , go to step 51);

57) Determine whether the switch to the previous test type should continue to switch forward. Update Y" _i-1 to the current test type, repeat step 56), and judge whether this test type Y" _i-1 needs to be with the previous test type Y"_i-2; if it does not need to be exchanged, go to step 56), If exchange is required, repeat step 57).

48) End the test.

Preferably, the weight calculation formula of the Y _i " and Y " _i-1 is: and in, is the sum of the times that the test type Y _i ″ can detect bad chips, It is the sum of the corresponding time of the test type Y _i ″ that can detect the bad chip, T″ _ij is the running time corresponding to the test vector V″ _ij in the test type _Yi ″, N″ _ij is running to a certain point in time, the statistics are bad The chip is due to the corresponding number of times measured by the test vector V″ _ij .

The present invention also provides a dynamic adjustment system for the test flow,

Including test type adjustment module;

The test type adjustment module includes:

Test type count calculation unit: Calculate the total number of times the bad chip can be detected corresponding to the test type;

Test type time weight calculation unit: calculate the sum of the corresponding time of the test type that can detect bad chips;

Test type weight calculation unit: calculate the weight of the test type according to the total number of times and the total time;

Test type sorting unit: Reorder by weight to get a new test type sequence.

Preferably, it also includes a test vector adjustment module for adjusting the test vector for each test type, and each test type includes multiple test vectors; the test vector adjustment module is used to calculate the weight of a single test vector, according to the single test vector The weights are sorted to get the new test vector order.

Preferably, it also includes an initialization module; the initialization module is used to set an initialization parameter num, and the num is a positive integer; then it is judged whether the running times of the current test vector is less than num, and if so, the current test vector is advanced to the front of the test vector , continue to run the next test vector; if not, the initialization ends.

Preferably, it also includes a dynamic combination adjustment module; the dynamic combination adjustment module is specifically:

51) Determine whether there are still integrated circuits that have not been tested, and if all the tests have been completed, go to step 48);

52) Select a chip to be tested, load the test vectors in sequence according to the sorted test type and test vector, if the test is successful, repeat step 51); if the test fails, go to step 53);

53) Record the corresponding test vectors and test types of integrated circuit failures tested, and accumulate the number of faulty integrated circuits tested by the test vectors;

54) Judging whether the current test vector V″ _ij needs to exchange the order with its previous test vector V″ _i(j-1) , the details are as follows: judging the number of times N″ _ij that the test vector V″ _ij tests to the faulty integrated circuit and the test The magnitude of the number of times N″ _i(j-1) that the vector V″ _i(j-1) tested to the faulty integrated circuit, if N″ _i(j-1) ≥ N″ _ij , there is no need to adjust the order of the vectors, go to Step 51); if N″ _i(j-1) < N″ _ij , exchange the order of the test vector V″ _ij with the test vector V″ _{i (j-1)} in front of it, and exchange the faulty integrated circuits that can be tested at the same time quantity;

55) Judging whether to switch to the previous test vector should continue to be exchanged, specifically: update V" _i(j-1) to the current test test vector, repeat step 54), and judge this test vector V" _{i(j -1)} Whether it is necessary to exchange with the previous test vector V″ _i(j-2) , if it is not necessary to exchange, go to step 56), if it is necessary to exchange, repeat step 55);

56) Determine whether the current test type Y _i ″ needs to exchange the order with its previous test type Y ″ _i-1 , specifically: calculate the weights of Y _i ″ and Y ″ _i-1 respectively and Compare and size, if Go to step 51), otherwise swap the order of test types Y _i " and Y" _i-1 , go to step 51);

57) Determine whether the switch to the previous test type should continue to switch forward. Y" _i-1 is updated to be the test type when testing, repeat step 56), judge whether this test vector Y" _i-1 needs to be with the previous test vector Y"_i-2; if no need to exchange, go to step 56) , if need to exchange, repeat step 57).

48) End the test.

Preferably, the weight calculation formula of the Y _i " and Y " _i-1 is: and in, is the sum of the times that the test type Y _i ″ can detect bad chips, It is the sum of the corresponding time of the test type Y _i ″ that can detect the bad chip, T″ _ij is the running time corresponding to the test vector V″ _ij in the test type _Yi ″, N″ _ij is running to a certain point in time, the statistics are bad The chip is due to the corresponding number of times measured by the test vector V″ _ij .

The advantages of the present invention are:

The embodiment of the present invention proposes a method for dynamically adjusting test types and test vectors in a hierarchical manner. The test types are dynamically adjusted according to the previous test results, and the high-quality test types are adjusted to the front, so that the bad circuit under test can be tested at the earliest. It can improve the test efficiency and reduce the test cost.

Further, it is also possible to dynamically adjust the order of the test vectors according to the previous test results and the current test situation, and adjust the high-quality test vectors to the front, so that the bad circuit under test can be tested at the earliest. It can improve the test efficiency and reduce the test cost. And by adding a judgment program, it can be ensured that all test vectors have been run, and high-quality test vectors will not be missed during dynamic adjustment.

The advantage of the present invention is that high-quality test vectors and test types are advanced in consideration of the quality of test vectors and test types. The innovation is that according to the test results of the previous integrated circuits, the test vectors and test types are sorted in a hierarchical order, and the test vectors and test types that are prone to failure are dynamically adjusted to the front. At the same time, combined with the current test situation, the order of test types and test vectors is dynamically adjusted, so that the sorted test types and test vectors are more suitable for actual integrated circuit testing. During actual testing, faulty integrated circuits can be found earlier, reducing testing time.

Description of drawings

FIG. 1 is a schematic flowchart of a method provided by an embodiment of the present invention.

Detailed ways

In order to have a further understanding and understanding of the structural features of the present invention and the effects achieved, the preferred embodiments and accompanying drawings are used in conjunction with detailed descriptions, and the descriptions are as follows:

A test flow dynamic adjustment method, which adjusts the order of the test types according to the test results of the test types.

Without loss of generality, assume that the test types are: Y ₁ , Y ₂ , ..., _{Yi , ..., Y n .} For any test type _{Yi, the test vectors are V i1 ,} V _i2 , ..., V _ij , ..., V _im , and the test times corresponding to the test vectors are: T _i1 , T _i2 , ..., T _ij , ..., _Yim . Running to the current time point, the chips that were damaged in the early stage were successfully tested due to the test vectors V _i1 , V _i2 , ..., V _ij , ..., V _im , and the corresponding times of successful test were respectively N _i1 , N _i2 , ... , N _ij , ..., N _im .

The test type adjustment method is as follows:

Step 11: Calculate the total number of times that the test type Y _i can detect bad chips:

Step 12: Calculate the total time corresponding to the defective _chips that can be detected by the test type Yi:

Step 13: _Calculate the weight of the test type Yi according to the sum of times and time:

Step 14: Reorder Y ₁ , Y ₂ , ..., Yi , ..., Y _n by weight W _Yi to obtain a new sequence of test types: Y ₁ ', Y ₂ ', ... _{, Yi} '... , Y _n '.

The above method only reorders the test types. In order to realize multi-level adjustment, it is also possible to further sequence multiple test vectors in each test type, specifically:

The main idea of this embodiment is to test a part of integrated circuits first, and initialize the sequence of test types and the sequence of test vectors according to the test results. Adjust the order of the test vectors while testing the circuit. When the accumulation reaches a certain level, adjust the order of the test types. The whole process is dynamically updated. The specific process is as follows:

1. Random test

First, randomly select different batches of integrated circuits from the integrated circuits under test, load them according to different test types, and load different test vectors, and run the tests of the integrated circuits in a certain order. This order can be required by the customer or optional. , even changed. Without loss of generality, the test types of the integrated circuit under test are: Y ₁ , Y ₂ , ..., Y _i , ..., Y _n ; for any test type, it contains several definite test vectors, let Y _i The test vectors contained in are: V _i1 , V _i2 , ..., V _ij , ..., V _im . where i, j, n, m are all integers. For a faulty integrated circuit, the information is counted, without loss of generality. It is assumed that the bad chip is counted due to the test vectors V _i1 , V _i2 , ..., V _ij , ..., V _im measured, the corresponding The times are N _i1 , N _i2 , ..., N _ij , ..., N _im , respectively.

The purpose of random testing is to allow samples of different batches of integrated circuits to be tested, which is more representative.

2. Initialization

Set the initialization parameter num, the minimum value is 1, and the maximum value is the number of actions when a bad integrated circuit can be tested by the test vector {V _i1 , V _i2 , ..., V _ij , ..., V _im } The maximum value of N _i1 , N _i2 , ..., N _ij , ..., N _im }. The value of Num determines the result of the final test vector adjustment order. The larger the value, the better the effect. Generally, take the maximum value of {N _i1 , N _i2 , ..., N _ij , ..., N _im }, and denote num=max {N _i1 , N _i2 , ..., N _ij , ..., N _im }, in general, num takes the maximum value.

51) set initialization parameter num, and described num is a positive integer;

52) judge whether the running times of all test vectors are all greater than mum, if not, select the first test vector as the current test vector, and jump to step 53); if so, jump to step 57);

53) advance the current test vector to the front of the test vector, jump to step 54);

54) judge whether there is the next test vector, if so, select the next test vector to be the current test vector, and jump to step 53); if not, jump to step 55);

55) Select the current test vector to test any untested integrated circuit, update the running times of the test vector, determine whether the integrated circuit is faulty, if the integrated circuit is faulty, update the fault measured by the test vector number, jump to step 52); if the integrated circuit has no fault, jump to step 56);

56) select the next test vector to be the current test vector, jump to step 55);

Without loss of generality, it is assumed that the bad chip counted at this time is due to the test vectors V _i1 , V _i2 , ..., V _ij , ..., V _im , and the corresponding times of the test are N' _i1 , N' _i2 , ..., N' _ij , ..., N' _im .

The purpose of initialization is to ensure that each test vector can be tested and avoid the situation where high-quality test vectors are not used. The initialization process is to select first and then test, that is, first mention all vectors less than num to the front, and then run the test, as long as not all vectors are less than num, keep looping.

3. Preliminary sorting

1) Test vector sorting

Without loss of generality, for the test vectors V _i1 , V _i2 , ..., V _ij , ..., V _im that determine the test type Y _i , the corresponding running times are: T _i1 , T _i2 , ..., T _ij , ..., _Yim .

Step 1: Set the weight W _j of V _ij =N' _ij /T _ij , and calculate the value of the weight W _j when j=1, 2, ..., m.

Step 2: According to the test _vectors V _i1 , V _i2 , _... , _{V ij} ,... V' _i1 , V' _i2 , ..., V' _ij , ..., V' _im .

The obtained test vectors V' _i1 , V' _i2 , ..., V' _ij , ..., V' _im are the dynamically adjusted test vectors.

2) Test type sorting

Step 1: Calculate the total number of times that the test type _Yi corresponds to the number of bad chips that can be tested:

Step 2: Calculate the total time corresponding to the defective chip that can be detected by the test type Y _i :

Step 3: _Calculate the weight of the test type Yi according to the sum of times and time:

Step 4: Reorder Y ₁ , Y ₂ , ..., Yi , ..., Y _n by weight W _Yi to get new test types: Y ₁ ', Y ₂ ', ... _{, Yi} '..., Y _n '.

The basic idea of the preliminary sorting is to put the high-quality test vectors and test types in the front according to the previous test results, which can make the integrated circuit failure occur earlier and reduce the test time of the faulty integrated circuit.

4. Dynamic combination adjustment

Without loss of generality, it is assumed that the current test types are in sequence: Y ₁ ", Y ₂ ", ..., Y _i ", ..., Y _n "; the test vector contained in Y _i " is: V" _i1 , V″ _i2 ,…,V″ _ij ,…,V″ _im . Bad chips are due to the test vectors V″ _i1 , V″ _i2 ,…,V″ _ij ,…,V″ _im which are The corresponding times of measurement are N″ _i1 , N″ _i2 , …, N″ _ij , …, N″ _im

At present, some integrated circuits have been tested, and there are still a large number of untested integrated circuits waiting to be tested. Since the test type and test vector are sorted, when adjusting dynamically, only the current test type and test vector need to be considered whether it will move forward. The specific test process is as follows.

Step 1: Determine whether there are still integrated circuits that have not been tested. If all the tests have been completed, go to Step 8.

Step 2: Choose a chip to be tested, load the test vectors in sequence according to the previously adjusted test type and test vector, if the test is successful, repeat step 1; if the test fails, go to step 3.

Step 3: Record the corresponding test vectors and test types of the integrated circuit failures tested by the test, and increase the number of faulty integrated circuits tested by the test vectors by 1 to the original number. Without loss of generality, it is assumed that there is a fault in the integrated circuit detected by the test vector V" _ij in the test type Y _i ", so far, the number of faults in the integrated circuit that can be detected by the test vector V" _ij is N" _ij , this , it is necessary to increase N″ _ij by 1, that is, N″ _ij =N″ _ij +1.

Step 4: Determine whether the current test vector V″ _ij needs to exchange the order with its previous test vector V″ _i(j-1) . The details are as follows: interpret the number of times N″ _ij that the test vector V″ _ij tests to the faulty integrated circuit and the number of times N″ _i (j-1) that the test vector V″ _i(j-1) tests to the faulty integrated circuit, if N " _i(j-1) ≥N" _ij , no need to adjust the order of the vectors, go to step 1. If N″ _i(j-1) < N″ _ij , swap the order of the test vector V″ _ij with the test vector V″ _i(j-1) in front of it, and at the same time swap the number of faulty integrated circuits that can be tested.

Step 5: Determine whether to continue to switch forward after switching to the previous test vector. Update V″ _i(j-1) to the current test vector, repeat step 4, and judge whether the test vector V″ _i(j-1) needs to be the same as the previous test vector V″ _i(j-2) . If not If you need to exchange, go to step 6, if you need to exchange, repeat step 5.

Step 6: Determine whether the current test type Y _i ″ needs to be swapped with its previous test type Y ″ _i-1 . Calculate the weights of Y _i ″ and Y″ _i-1 respectively and Compare and size, if Go to step 1, otherwise swap the order of test types Yi" and Y" _{i -1} . Go to step 1.

Step 7: Determine whether the switch to the previous test type should continue to switch forward. Update Y″ _i-1 to the current test type, repeat step 6 to determine whether the test vector Y″ _i-1 needs to be exchanged with the previous test vector Y″ _i-2 . If no exchange is required, go to step 6, if Swap is required, repeat step 7.

Step 8: End the test.

It should be pointed out that the adjustment of the test type and the adjustment of the test vector can be performed simultaneously or separately, and the calculation process is relatively independent. You can adjust the order of test types first, and then adjust the order of test vectors within the test type; you can also adjust the order of test vectors first, and then adjust the order of test types. The two algorithms are relatively independent, and the end result is the same.

This embodiment also provides a system for dynamic adjustment of a test flow, including a test type adjustment module, a test vector adjustment module, an initialization module, and a dynamic combination adjustment module.

The test type adjustment module includes:

Test type count calculation unit: Calculate the number of times that the test type corresponds to the number of bad chips that can be detected;

Test type time weight calculation unit: calculate the time weight corresponding to the test type that can detect bad chips;

Test type weight calculation unit: calculate the weight of the test type;

Test type sorting unit: Reorder by weight to get a new test type sequence.

It also includes a test vector adjustment module for adjusting the test vector for each test type, and each test type includes multiple test vectors; the test vector adjustment module is used to calculate the weight of a single test vector, and is sorted according to the weight of the single test vector , to get the new test vector order.

Described initialization module is used for setting initialization parameter num, and described num is a positive integer; Then judge whether the running times of current test vector is less than num, if yes, then advance current test vector to the front of test vector, and continue to run next test vector; If not, initialization ends.

The dynamic combination adjustment module is specifically:

51) Determine whether there are still integrated circuits that have not been tested, and if all the tests have been completed, go to step 48);

52) Select a chip to be tested, load the test vectors in sequence according to the sorted test type and test vector, if the test is successful, repeat step 51); if the test fails, go to step 53);

53) Record the corresponding test vector and test type of the fault of the integrated circuit, and accumulate the number of faulty integrated circuits tested by the test vector; 54) Determine whether the current test vector V″ _ij needs to be the same as its previous test vector V″ _{i (j -1)} The exchange sequence is as follows: judging the number of times N" _ij that the test vector V" _ij tested the faulty integrated circuit and the number of times N" _i (j-1) that the test vector V" _i(j-1) tested the faulty integrated circuit ₎ , if N″ _i(j-1) ≥ N″ _ij , there is no need to adjust the order of the vectors, go to step 51); if N″ _i(j-1) < N″ _ij , test the vector V″ _ij exchanges the order with the test vector V″ _i(j-1) in front of it, and at the same time exchanges the number of faulty integrated circuits that can be tested;

55) Judging whether to switch to the previous test vector should continue to be exchanged, specifically: update V" _i(j-1) to the current test test vector, repeat step 54), and judge this test vector V" _{i(j -1)} Whether it is necessary to exchange with the previous test vector V″ _i(j-2) , if it is not necessary to exchange, go to step 56), if it is necessary to exchange, repeat step 55);

56) Determine whether the current test type Y _i ″ needs to exchange the order with its previous test type Y ″ _i-1 , specifically: calculate the weights of Y _i ″ and Y ″ _i-1 respectively and Compare and size, if Go to step 51), otherwise swap the order of test types Y _i " and Y" _i-1 , go to step 51);

57) Determine whether the switch to the previous test type should continue to switch forward. Y" _i-1 is updated to be the test type when testing, repeat step 56), judge whether this test vector Y" _i-1 needs to be with the previous test vector Y"_i-2; if no need to exchange, go to step 56) , if need to exchange, repeat step 57).

48) End the test.

The weight calculation formula of the Y _i " and Y " _i-1 is: and in, is the sum of the times that the test type Y _i ″ can detect bad chips, It is the sum of the corresponding time of the test type Y _i ″ that can detect the bad chip, T″ _ij is the running time corresponding to the test vector V″ _ij in the test type _Yi ″, N″ _ij is running to a certain point in time, the statistics are bad The chip is due to the corresponding number of times measured by the test vector V″ _ij .

i, j, n, and m in this embodiment are all positive integers.

The foregoing has shown and described the basic principles, main features and advantages of the present invention. It should be understood by those skilled in the art that the present invention is not limited by the above-mentioned embodiments. The above-mentioned embodiments and descriptions describe only the principles of the present invention. Without departing from the spirit and scope of the present invention, there are various Variations and improvements are intended to fall within the scope of the claimed invention. The scope of protection claimed by the present invention is defined by the appended claims and their equivalents.

Claims (10)

1. a test flow dynamic adjustment method, is characterized in that: comprise test type adjustment; The test type adjustment includes: Calculate the total number of times that a single test type can detect bad chips; Calculate the total time corresponding to a single test type that can detect bad chips; Calculate the weight of a single test type based on the sum of times and time; Reorder by weight to get a new sequence of test types. 2. a kind of test flow dynamic adjustment method according to claim 1, is characterized in that: also comprise and carry out test vector adjustment for each test type; In each test type, comprise a plurality of test vectors; Described test vector adjustment concrete To: Calculate the weight of a single test vector, sort according to the weight of the test vector, and get a new test vector order. 3. a kind of test flow dynamic adjustment method according to claim 2 is characterized in that: for the test vectors V _i1 , V _i2 , ..., V _ij , ..., V _im corresponding to the test types Y _i are determined to run The times are: T _i1 , T _i2 , ..., T _ij , ..., Y _im ; the weight of a single test vector V _ij is W _j =N' _ij /T _ij , and the calculation j=1, 2, ..., m the value of the weight W _j ; According to the test vectors V _i1 , V _i2 , ..., V _ij , ..., V _im corresponding to the value of the weight W _j , arrange the corresponding test vectors of W _j in descending order to obtain a new test vector V' _i1 , V' _i2 , ..., V' _ij , ..., V' _im . 4. a kind of test flow dynamic adjustment method according to claim 2 and 3, is characterized in that: before the test vector is sorted, initialize first, be specifically: 51) set initialization parameter num, and described num is a positive integer; 52) judge whether the running times of all test vectors are all greater than mum, if not, select the first test vector to be the current test vector, and jump to step 43); if so, jump to step 57); 43) advance the current test vector to the front of the test vector, jump to step 54); 54) judge whether there is the next test vector, if so, select the next test vector to be the current test vector, and jump to step 43); if not, jump to step 55); 55) Select the current test vector to test any untested integrated circuit, update the running times of the test vector, determine whether the integrated circuit is faulty, and if the integrated circuit is faulty, update the fault measured by the test vector number, jump to step 52); if the integrated circuit has no fault, jump to step 56); 56) select the next test vector to be the current test vector, jump to step 55); 57) The initialization ends. 5. a kind of test flow dynamic adjustment method according to claim 2 or 3, is characterized in that: also comprise dynamic combination adjustment, be specially: 51) Determine whether there are still integrated circuits that have not been tested, if all the tests have been completed, go to 48); 52) Select a chip to be tested, load the test vectors in sequence according to the sorted test type and test vector, if the test is successful, repeat step 51); if the test fails, go to step 53); 53) Record the corresponding test vectors and test types of integrated circuit failures tested, and accumulate the number of faulty integrated circuits tested by the test vectors; 54) Judging whether the current test vector V" _ij needs to exchange the order with its previous test vector V" _i(j-1) , the details are as follows: Judging the number of times N" _ij that the test vector V" _ij tests to the faulty integrated circuit and the test The number of times N” _i(j-1) that the vector V” _{i(j-1) is} tested to the faulty integrated circuit, if N” _i(j-1) ≥ N” _ij , no need to adjust the order of the vectors, go to Step 51); if N” _i(j-1) < N” _ij , exchange the order of the test vector V” _ij with the test vector V” _i(j-1) in front of it, and exchange the faulty integrated circuits that can be tested at the same time quantity; 55) Judging whether to switch to the previous test vector should continue to be exchanged, specifically: update V" _i(j-1) to the test test vector, repeat step 54), judge this test vector V" _{i (j -1)} Whether it is necessary to exchange with the previous test vector V" _i(j-2) , if it is not necessary to exchange, go to step 56), if it is necessary to exchange, repeat step 55); 56) Determine whether the current test type Y" _i needs to exchange the order with its previous test type Y" _i-1 , specifically: calculate the weights of Y" _i and Y" _i-1 respectively and Compare and size, if Go to step 51), otherwise swap the order of test types Y" _i and Y" _i-1 , go to step 51); 57) judge whether to switch to the previous test type and continue to switch forward; Y" _i-1 is updated to be the test type when testing, repeat step 56), judge whether this test vector Y" _i-1 needs to be tested with the previous test Vector Y"_i-2; if need not exchange, go to step 56), if need exchange, repeat step 57); 48) End the test. 6. a kind of test flow dynamic adjustment method according to claim 5, is characterized in that: the weight calculation formula of described Y " _i and Y " _i-1 is and in, For the test type Y” _i corresponds to the sum of the times that the bad chip can be detected, Indicates the sum of the corresponding time for the test type Y” _i to detect the bad chip, T” _ij is to determine the running time corresponding to the test vector V” _ij in the test type Y” _i , N” _ij is the running time to a certain time point, the statistics are bad The chip is due to the corresponding number of times measured by the test vector V” _ij . 7. A test flow dynamic adjustment system is characterized in that: Including test type adjustment module; The test type adjustment module includes: Test type count calculation unit: Calculate the total number of times the bad chip can be detected corresponding to the test type; Test type time weight calculation unit: calculate the sum of the corresponding time of the test type that can detect bad chips; Test type weight calculation unit: calculate the weight of the test type according to the total number of times and the total time; Test type sorting unit: Reorder by weight to get a new test type sequence. 8. a kind of test flow dynamic adjustment system according to claim 7, is characterized in that: also comprises the test vector adjustment module that carries out test vector adjustment for each test type, comprises multiple test vectors in each test type; The test vector adjustment module is used to calculate the weight of a single test vector, and according to the weight order of the single test vector, a new test vector order is obtained. 9. A kind of test flow dynamic adjustment system according to claim 7, is characterized in that: also comprises initialization module; Described initialization module is used for setting initialization parameter num, and described num is positive integer; Then judge current test vector operation Whether the number of times is less than num, if so, advance the current test vector to the front of the test vector and continue to run the next test vector; if not, the initialization ends. 10. A test flow dynamic adjustment system according to claim 8, characterized in that: further comprising a dynamic combination adjustment module; the dynamic combination adjustment module is specifically: 51) Determine whether there are still integrated circuits that have not been tested, and if all the tests have been completed, go to step 48); 52) Select a chip to be tested, load the test vectors in sequence according to the sorted test type and test vector, if the test is successful, repeat step 51); if the test fails, go to step 53); 53) Record the corresponding test vectors and test types of integrated circuit failures tested, and accumulate the number of faulty integrated circuits tested by the test vectors; 54) Judging whether the current test vector V" _ij needs to exchange the order with its previous test vector V" _i(j-1) , the details are as follows: Judging the number of times N" _ij that the test vector V" _ij tests to the faulty integrated circuit and the test The number of times N” _i(j-1) that the vector V” _{i(j-1) is} tested to the faulty integrated circuit, if N” _i(j-1) ≥ N” _ij , no need to adjust the order of the vectors, go to Step 51); if N” _i(j-1) < N” _ij , exchange the order of the test vector V” _ij with the test vector V” _i(j-1) in front of it, and exchange the faulty integrated circuits that can be tested at the same time quantity; 55) Judging whether to switch to the previous test vector should continue to be exchanged, specifically: update V" _i(j-1) to the test test vector, repeat step 54), judge this test vector V" _{i (j -1)} Whether it is necessary to exchange with the previous test vector V" _i(j-2) , if it is not necessary to exchange, go to step 56), if it is necessary to exchange, repeat step 55); 56) Determine whether the current test type Y" _i needs to exchange the order with its previous test type Y" _i-1 , specifically: calculate the weights of Y" _i and Y" _i-1 respectively and Compare and size, if Go to step 51), otherwise swap the order of test types Y" _i and Y" _i-1 , go to step 51); 57) judge whether to switch to the previous test type and continue to switch forward; Y" _i-1 is updated to be the test type when testing, repeat step 56), judge whether this test vector Y" _i-1 needs to be tested with the previous test Vector Y"_i-2; if need not exchange, go to step 56), if need exchange, repeat step 57); 48) end test; the weight calculation formula of described Y" _i and Y" _i-1 is and in, For the test type Y” _i corresponds to the sum of the times that the bad chip can be detected, Indicates the sum of the corresponding time for the test type Y” _i to detect the bad chip, T” _ij is to determine the running time corresponding to the test vector V” _ij in the test type Y” _i , N” _ij is the running time to a certain time point, the statistics are bad The chips are due to the corresponding times measured by the test vector V” _ij .