CN109714031A - A kind of rail-to-rail high-performance comparator - Google Patents
A kind of rail-to-rail high-performance comparator Download PDFInfo
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- 101100428744 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) VPS60 gene Proteins 0.000 claims description 18
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- 101100402275 Arabidopsis thaliana MOS11 gene Proteins 0.000 claims description 16
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Abstract
The invention discloses a kind of rail-to-rail high-performance comparators, including the first primary differential amplification unit, the second primary differential amplification unit, integrate converting unit, rear class differential amplification unit, the input terminal of first primary differential amplification unit is connect to receive external signal to be compared and primary enhanced processing with the input terminal of the second primary differential amplification unit, first primary differential amplification unit is controlled by N type switch tube, and the second primary differential amplification unit is by p-type switch controlled；Integrate the amplified signal of primary of the primary differential amplification unit of converting unit integration first and the second primary differential amplification unit output；Signal after integration is compared amplification output by rear class differential amplification unit；The design improves common-mode rejection ratio by multistage amplification, reduce the deviation because of caused by asymmetry, reach good symmetry and amplify linear consistency, while integrating converting unit integration superposition to offset the deviation occurred in primary differential amplification, so that the comparison signal of final output is stablized.
Description
Technical field
The present invention relates to electronic circuit field, especially a kind of comparator circuit.
Background technique
Traditional comparator, especially a kind of CMOS differential comparator, as shown in Figure 1, CMOS differential comparator is by P-channel
Transistor MOS1 ', the transistor MOS2 ' of P-channel, the transistor MOS3 ' of N-channel and N-channel transistor MOS4 '；It is brilliant
The grid of body pipe MOS1 ' receives the input signal of one, and the grid of transistor MOS2 ' receives another input signal, transistor
The source electrode of MOS1 ' and the source electrode of transistor MOS2 ' access a constant-current source, the drain electrode of transistor MOS1 ' respectively with transistor
The grid of MOS3 ' and drain electrode, the grid connection of transistor MOS4 ', the source electrode ground connection of transistor MOS3 ', transistor MOS4's '
Source electrode ground connection, the drain electrode of transistor MOS2 ' connect and export with the drain electrode of transistor MOS4 '；
Since there are asymmetry for the circuit structure of this CMOS differential comparator, even if respectively from the grid of transistor MOS1 '
When pole, this both ends of the grid of transistor MOS2 ' input same signal, there are relatively large deviation, common mode suppressions between two output signals
Make relatively low, the signal for causing comparator to export is inaccurate, and in order to solve this problem, the applicant attempts using more poor linearity
Grade differential amplification circuit structure, although however improve common-mode rejection ratio to a certain extent, the wave of general input signal
Shape is opposite, and there are uppers and lower portion, when carrying out primary amplification, typically enter N type switch tube or p-type switch
In the differential amplifier circuit for managing system, due to the characteristic of switching tube, amplified signal leads to final output there are certain deviation
The upper of signal is relatively normal and lower portion deviation or lower portion are relatively more normal and the case where upper deviation,
Such as a kind of metal-oxide-semiconductor using N-channel as control pipe differential amplifier circuit, as shown in Fig. 2, the metal-oxide-semiconductor based on N-channel is put
Big characteristic, the signal of output reacts that upper is relatively good on waveform and corresponding amplitude is not achieved in lower portion, defeated
Linearly depth is poor out, and asymmetric, when then amplifying using next stage, this deviation can be then amplified, and influence comparator
Performance and application range.
Further, in the amplification process to signal, it is fluctuation that signal, which either rises or declines all, and is being put
During big, it is easy to be amplified to this fluctuation, the signal jitter for eventually leading to output is larger, ineffective.
Summary of the invention
In order to solve the above technical problems, the object of the present invention is to provide a kind of high-end amplitude that can be realized output signal and
The rail-to-rail linear consistent, symmetry of low side amplitude is good and comparator by multistage enlarged structure raising common-mode rejection ratio.
The technical solution adopted by the present invention is that:
A kind of rail-to-rail high-performance comparator, comprising:
First primary differential amplification unit and the second primary differential amplification unit, the first primary differential amplification unit it is defeated
Enter end connect with the input terminal of the second primary differential amplification unit to receive external input signal simultaneously primary enhanced processing, at the beginning of first
Grade differential amplification unit is controlled by N type switch tube, while the second primary differential amplification unit is by p-type switch controlled；
Integrate converting unit, respectively with the output end of the first primary differential amplification unit and the second primary differential amplification unit
Output end connection to integrate the primary amplification of the first primary differential amplification unit and the second primary differential amplification unit output
Signal afterwards；
Rear class differential amplification unit, amplification is defeated compared with connecting with the output end for integrating converting unit by the signal after integration
Out.
Further include sluggish processing unit, sluggish processing unit respectively with the output end of the first primary differential amplification unit and/
Or second primary differential amplification unit output end connection to the first primary differential amplification unit and the second primary differential amplification
The amplified signal hysteresis processing of the primary of unit output.
Described first primary differential amplification unit includes transistor MOS11, P ditch of the transistor MOS10 of N-channel, N-channel
The transistor MOS5 in the road and transistor MOS6 of P-channel；
The source electrode of transistor MOS10 is connect with the current source of the source electrode of transistor MOS11 and outside respectively；
The drain electrode of transistor MOS10 respectively with the drain electrode of transistor MOS5, the grid of transistor MOS5, sluggish processing unit
And integrate converting unit connection；
The drain electrode of transistor MOS11 respectively with the drain electrode of transistor MOS6, the grid of transistor MOS6, sluggish processing unit
And integrate converting unit connection；
The source electrode of transistor MOS5 and the source electrode of transistor MOS6 access external power supply；
The grid of transistor MOS10 and the grid of transistor MOS11 receive external signal to be compared respectively.
Described second primary differential amplification unit includes transistor MOS12, N ditch of the transistor MOS9 of P-channel, P-channel
The transistor MOS15 in the road and transistor MOS16 of N-channel；
The source electrode of transistor MOS9 is connect with the current source of the source electrode of transistor MOS12 and outside respectively；
The drain electrode of transistor MOS9 is single with the drain electrode of transistor MOS15, the grid of transistor MOS15, sluggish processing respectively
Member and integrate converting unit connection；
The drain electrode of transistor MOS12 is single with the drain electrode of transistor MOS16, the grid of transistor MOS16, sluggish processing respectively
Member and integrate converting unit connection；
The source electrode of transistor MOS15 and the source grounding of transistor MOS16；
The grid of transistor MOS9 is connect with the grid of transistor MOS10；The grid and transistor of transistor MOS12
The grid of MOS11 connects.
The converting unit of integrating includes the transistor MOS3 of the P-channel and transistor MOS8 of P-channel；
The grid of transistor MOS3 is connect with the grid of transistor MOS5；
The grid of transistor MOS8 is connect with the grid of transistor MOS6；
The source electrode of transistor MOS3 source electrode and transistor MOS8 are connect with external power supply；
The drain electrode of transistor MOS3 is inputted with the one of the drain electrode of transistor MOS16 and rear class differential amplification unit respectively
End connection；
The drain electrode of transistor MOS8 is another defeated with the drain electrode of transistor MOS15 and rear class differential amplification unit respectively
Enter end connection.
The sluggishness processing unit includes the transistor of the transistor MOS4 of P-channel, the transistor MOS7 of P-channel, N-channel
The transistor MOS17 of MOS14 and N-channel；
The grid of transistor MOS4 is connect with the drain electrode of the grid of transistor MOS5 and transistor MOS7 respectively；
The grid of transistor MOS7 is connect with the drain electrode of the grid of transistor MOS6 and transistor MOS4 respectively；
The source electrode of transistor MOS4, the source electrode of transistor MOS7 are connect with external power supply；
The grid of transistor MOS17 is connect with the drain electrode of the grid of transistor MOS16 and transistor MOS14 respectively；
The grid of transistor MOS14 is connect with the drain electrode of the grid of transistor MOS15, transistor MOS17 respectively；
The source electrode of transistor MOS14 and the source electrode ground connection of transistor MOS17.
The rear class differential amplification unit includes the crystalline substance of the transistor MOS1 of P-channel, the transistor MOS2 of P-channel, N-channel
The transistor MOS18 of body pipe MOS13 and N-channel；
The grid of transistor MOS13 is connect with the drain electrode of transistor MOS8；
The drain electrode of transistor MOS13 respectively with the drain electrode of transistor MOS1, the grid of transistor MOS1, transistor MOS2
Grid connection；
The grid of transistor MOS18 is connect with the drain electrode of transistor MOS13；
The source electrode of transistor MOS13 and the source grounding of transistor MOS18；
The source electrode of transistor MOS1 is connect with the source electrode of transistor MOS2 with external power supply；
Amplified signal compared with the drain electrode of transistor MOS2 is connected and exported with the drain electrode of transistor MOS18.
It further include phase inverter U1, the input terminal of phase inverter U1 is connect with the output end of rear class differential amplification unit.
Described first primary differential amplification unit is made of NPN type triode.
Described second primary differential amplification unit is made of PNP type triode.
Beneficial effects of the present invention:
Signal to be compared is input to the first primary differential amplification unit and the second primary difference is put by comparator of the present invention
Big unit, the first primary differential amplification unit is controlled by N type switch tube, according to the differential amplifier circuit of N type switch tube control
Characteristic, output amplified signal high end side have preferable amplification effect, and low side can then exist it is a degree of partially
To, and the second primary differential amplification unit has p-type switch controlled, it is then proper with the output effect of the first primary differential amplification unit
Well on the contrary, integrating converting unit receives the first primary differential amplification unit and the second amplified letter of primary differential amplification unit
Number, two signals are dexterously overlapped integration, to realize the effect of complementary counteracting, prevent from occurring in primary amplify inclined
Difference flows into next stage amplifying unit, so that keeping by the amplitude of the high end side of signal and low side of integrating converting unit integration
Unanimously, reach rail-to-rail linear consistent balance and symmetry amplification effect, meanwhile, the signal of output is put again through rear class difference
Big unit amplifies, and the design improves common-mode rejection ratio by multistage amplification, reduces because of conventional difference amplifying circuit not
Deviation caused by symmetrical reaches good symmetry, while offsetting primary difference by integrating converting unit integration superposition
The deviation occurred in amplification, so that the comparison signal of final output is stablized, simply low energy consumption for circuit.
Further, by sluggish processing unit come to the first primary differential amplification unit and the second primary differential amplification list
The signal of member output carries out lag processing, prevents the fluctuation of input signal from amplifying in amplifying unit, guarantees signal stabilization,
With stronger noiseproof feature.
Detailed description of the invention
A specific embodiment of the invention is described further with reference to the accompanying drawing.
Fig. 1 is traditional differential amplifier circuit schematic diagram.
Fig. 2 is the output waveform figure of the differential amplifier circuit of p-type switching tube input control.
Fig. 3 is the circuit diagram of comparator of the present invention.
Specific embodiment
As shown in figure 3, a kind of rail-to-rail high-performance comparator, comprising:
First primary differential amplification unit 1 and the second primary differential amplification unit 2, the first primary differential amplification unit 1
Input terminal connect with the input terminal of the second primary differential amplification unit 2 to receive external input signal and primary enhanced processing,
First primary differential amplification unit 1 is controlled by N type switch tube, while the second primary differential amplification unit 2 is switched by p-type and managed
System；
Integrate converting unit 3, respectively with the output end of the first primary differential amplification unit 1 and the second primary differential amplification list
The output end connection of member 2 is to integrate the primary that the first primary differential amplification unit 1 and the second primary differential amplification unit 2 export
Amplified signal；
Rear class differential amplification unit 4, amplification is defeated compared with connecting with the output end for integrating converting unit 3 by the signal after integration
Out.
Signal to be compared is input to the first primary differential amplification unit 1 and the second primary differential amplification unit by the design
2, the first primary differential amplification unit 1 is controlled by N type switch tube, according to the characteristic of the differential amplifier circuit of N type switch tube control,
There is preferable amplification effect in the high end side of the amplified signal of output, and low side can then have a degree of deviation, such as
Shown in Fig. 2, cause the amplitude of low side relatively narrow, and the second primary differential amplification unit 2 has p-type switch controlled, at the beginning of first
The output effect of grade differential amplification unit 1 is then just the opposite, defeated by the second primary differential amplification unit 2 of p-type switch controlled
The amplitude of signal low side out is relatively narrow, and high end side is generally relatively more normal.
Since the first primary differential amplification unit 1 and the second primary differential amplification unit 2 are to be compared with input terminal input
Signal, therefore according to the amplification characteristic of differential amplifier circuit, either N control system or P control system, the signal period base of output
Originally it matches, and integrates converting unit and receive the first primary differential amplification unit 1 and the second primary amplification of differential amplification unit 2
Two signals are dexterously overlapped integration, are i.e. are located at being overlapped for high end side in two signals, are located at low by signal afterwards
End side is overlapped, so that complementation is dexterously realized with simple circuit, both signal cancellations after reaching integration deviation
Effect prevents the deviation occurred in primary amplify from flowing into next stage amplifying unit, so that by integrating the integration of converting unit 3
The amplitude of the high end side of signal and low side is consistent, and reaches rail-to-rail linear consistent balance and symmetry amplification effect, meanwhile, it is defeated
Signal out is amplified again through rear class differential amplification unit 4, and the design improves common mode inhibition by multistage amplification
Than reducing the deviation because caused by conventional difference amplifying circuit is asymmetric, reaching good symmetry, while turning by integration
The integration superposition of unit 3 is changed to offset the deviation occurred in primary differential amplification, so that the comparison signal of final output is stablized, circuit
It is simple that low energy consumption.
It further include sluggish processing unit 5, sluggish processing unit 5 output end with the first primary differential amplification unit 1 respectively
And/or second primary differential amplification unit 2 output end connection to the first primary differential amplification unit 1 and the second primary difference
The amplified signal hysteresis processing of the primary that amplifying unit 2 exports.
Come here by sluggish processing unit 5 to the first primary differential amplification unit 1 and the second primary differential amplification unit 2
The signal of output carries out lag processing, prevents the fluctuation of input signal from amplifying in amplifying unit, guarantees signal stabilization, tool
There is stronger noiseproof feature.
The design is attached to the signal that lag function makes final output perfection stable, noise resistance strong antijamming capability, circuit
Simply, low energy consumption, can be widely used in various electronic products especially IC chip electronic product.
In the design, the first primary differential amplification unit 1 can be made of NPN type triode, the second primary differential amplification
Unit 2 can be made of PNP type triode, and as a preferred embodiment, the design is controlled at the beginning of first using N-channel MOS pipe
Grade differential amplification unit 1, and load-side of the P-channel metal-oxide-semiconductor as the first primary differential amplification unit 1, equally, using P-channel
Metal-oxide-semiconductor controls the second primary differential amplification unit 2, and load of the N-channel MOS pipe as the second primary differential amplification unit 2
Side in the selection of specific circuit arrangement mode and specific element, can be chosen and be repaired in conventional specification certainly
Just, as long as arranging by the thinking and principle of the design, belong to the protection scope of the design.
First primary differential amplification unit 1 includes transistor MOS11, the P-channel of the transistor MOS10 of N-channel, N-channel
Transistor MOS5 and P-channel transistor MOS6；
The source electrode of transistor MOS10 is connect with the current source of the source electrode of transistor MOS11 and outside respectively；
The drain electrode of transistor MOS10 respectively with the drain electrode of transistor MOS5, the grid of transistor MOS5, sluggish processing unit
5 and integrate converting unit 3 connection；
The drain electrode of transistor MOS11 respectively with the drain electrode of transistor MOS6, the grid of transistor MOS6, sluggish processing unit
5 and integrate converting unit 3 connection；
The source electrode of transistor MOS5 and the source electrode of transistor MOS6 access external power supply；
The grid of transistor MOS10 and the grid of transistor MOS11 receive external signal to be compared respectively.
Second primary differential amplification unit 2 includes the transistor MOS9 of P-channel, the transistor MOS12 of P-channel, N-channel
The transistor MOS16 of transistor MOS15 and N-channel；
The source electrode of transistor MOS9 is connect with the current source of the source electrode of transistor MOS12 and outside respectively；
The drain electrode of transistor MOS9 is single with the drain electrode of transistor MOS15, the grid of transistor MOS15, sluggish processing respectively
Member 5 and integrate converting unit 3 connection；
The drain electrode of transistor MOS12 is single with the drain electrode of transistor MOS16, the grid of transistor MOS16, sluggish processing respectively
Member 5 and integrate converting unit 3 connection；
The source electrode of transistor MOS15 and the source grounding of transistor MOS16；
The grid of transistor MOS9 is connect with the grid of transistor MOS10；The grid and transistor of transistor MOS12
The grid of MOS11 connects.
The converting unit 3 of integrating includes the transistor MOS3 of the P-channel and transistor MOS8 of P-channel；
The grid of transistor MOS3 is connect with the grid of transistor MOS5；
The grid of transistor MOS8 is connect with the grid of transistor MOS6；
The source electrode of transistor MOS3 source electrode and transistor MOS8 are connect with external power supply；
The drain electrode of transistor MOS3 is defeated with the one of the drain electrode of transistor MOS16 and rear class differential amplification unit 4 respectively
Enter end connection；
The drain electrode of transistor MOS8 is another with the drain electrode of transistor MOS15 and rear class differential amplification unit 4 respectively
Input terminal connection.
The sluggishness processing unit includes the transistor of the transistor MOS4 of P-channel, the transistor MOS7 of P-channel, N-channel
The transistor MOS17 of MOS14 and N-channel；
The grid of transistor MOS4 is connect with the drain electrode of the grid of transistor MOS5 and transistor MOS7 respectively；
The grid of transistor MOS7 is connect with the drain electrode of the grid of transistor MOS6 and transistor MOS4 respectively；
The source electrode of transistor MOS4, the source electrode of transistor MOS7 are connect with external power supply；
The grid of transistor MOS17 is connect with the drain electrode of the grid of transistor MOS16 and transistor MOS14 respectively；
The grid of transistor MOS14 is connect with the drain electrode of the grid of transistor MOS15, transistor MOS17 respectively；
The source electrode of transistor MOS14 and the source electrode ground connection of transistor MOS17.
The rear class differential amplification unit includes the crystalline substance of the transistor MOS1 of P-channel, the transistor MOS2 of P-channel, N-channel
The transistor MOS18 of body pipe MOS13 and N-channel；
The grid of transistor MOS13 is connect with the drain electrode of transistor MOS8；
The drain electrode of transistor MOS13 respectively with the drain electrode of transistor MOS1, the grid of transistor MOS1, transistor MOS2
Grid connection；
The grid of transistor MOS18 is connect with the drain electrode of transistor MOS13；
The source electrode of transistor MOS13 and the source grounding of transistor MOS18；
The source electrode of transistor MOS1 is connect with the source electrode of transistor MOS2 with external power supply；
Amplified signal compared with the drain electrode of transistor MOS2 is connected and exported with the drain electrode of transistor MOS18.
The workflow of the above circuit is, in the first primary differential amplifier circuit 1 and the second primary differential amplifier circuit 2
One input end VinA and another input terminal VinB input signal, it is subsequent to be illustrated with signal VinA with signal VinB, work as input
Common-mode signal, amplification quantity 0；When input difference mode signal, VinA is greater than VinB, the MOS10 in the first primary differential amplification unit 1
On-state rate be higher than MOS11, the electric current for flowing through MOS5, which is greater than, flows through the electric current of MOS6, due to MOS3 and MOS5 common gate, MOS6
With MOS8 common gate, then there is identical turn-on effect, be equivalent to herein by the amplified signal of the first primary differential amplification unit 1 to
To converting unit is integrated simultaneously, in the second primary differential amplification unit 2, the on-state rate of MOS9 is less than MOS12, MOS15, MOS14
Common gate, MOS17 and MOS16 common gate, then have identical turn-on effect, the electric current that thus MOS3 flows through be added to MOS17,
On MOS16, the electric current that MOS8 flows through is added on MOS15, MOS14, to be superimposed integration, complementation is realized, after reaching integration
The effect of both signal cancellations deviation, meanwhile, MOS17, MOS16 and MOS18 common gate output a signal to rear class differential amplification
The one input end of circuit, MOS14, MOS15 and MOS13 common gate output a signal to the another of rear class differential amplifier circuit 4
Input terminal, and at this point, the signal for being equivalent to one input end is higher than the signal of another input terminal, rear class differential amplifier circuit 4
Output signal is negative, and similarly, when VinA is less than VinB, then 4 output signal of rear class differential amplifier circuit is positive, and due to input
There is fluctuations for signal, by taking MOS7 as an example, fluctuate when VinA exists, the electric current for flowing through MOS10 can change, and electricity is had at MOS7
In stream compensation to the drain electrode of MOS10, to not interfere with the electric current for flowing through MOS5, and then the stagnant of sluggish processing unit 5 is realized
Post-processing, and the lag handling principle of MOS4, MOS14, MOS17 are the same as shown in MOS7.
It further, further include phase inverter U1, the input terminal of phase inverter U1 and the output end of rear class differential amplification unit connect
It connects, reverse phase is carried out to the signal of output by phase inverter U1, it is defeated when adjustment is so that the signal of the end VinA input is higher than the end VinB
Comparison signal out is positive.
The above description is only a preferred embodiment of the present invention, and the present invention is not limited to above embodiment, as long as with
Essentially identical means realize that the technical solution of the object of the invention belongs within protection scope of the present invention.
Claims (10)
1. a kind of rail-to-rail high-performance comparator characterized by comprising
First primary differential amplification unit and the second primary differential amplification unit, the input terminal of the first primary differential amplification unit
It is connect with the input terminal of the second primary differential amplification unit to receive external input signal and primary enhanced processing, first is just differential
Amplifying unit is divided to be controlled by N type switch tube, while the second primary differential amplification unit is by p-type switch controlled；
Converting unit is integrated, it is defeated with the output end of the first primary differential amplification unit and the second primary differential amplification unit respectively
Outlet connection is amplified with the primary for integrating the first primary differential amplification unit and the second primary differential amplification unit output
Signal；
Rear class differential amplification unit is amplified compared with connecting with the output end for integrating converting unit by the signal after integration and is exported.
2. a kind of rail-to-rail high-performance comparator according to claim 1, it is characterised in that: further include that sluggish processing is single
Member, sluggish processing unit respectively with the output end of the first primary differential amplification unit and/or the second primary differential amplification unit
Output end connection is with the amplified letter of primary to the first primary differential amplification unit and the second primary differential amplification unit output
Number sluggish processing.
3. a kind of rail-to-rail high-performance comparator according to claim 2, it is characterised in that: the described first primary difference is put
Big unit includes the transistor MOS5 and P-channel of the transistor MOS10 of N-channel, the transistor MOS11 of N-channel, P-channel
Transistor MOS6；
The source electrode of transistor MOS10 is connect with the current source of the source electrode of transistor MOS11 and outside respectively；
The drain electrode of transistor MOS10 respectively with the drain electrode of transistor MOS5, the grid of transistor MOS5, sluggish processing unit and
Integrate converting unit connection；
The drain electrode of transistor MOS11 respectively with the drain electrode of transistor MOS6, the grid of transistor MOS6, sluggish processing unit and
Integrate converting unit connection；
The source electrode of transistor MOS5 and the source electrode of transistor MOS6 access external power supply；
The grid of transistor MOS10 and the grid of transistor MOS11 receive external signal to be compared respectively.
4. a kind of rail-to-rail high-performance comparator according to claim 3, it is characterised in that: the described second primary difference is put
Big unit includes the transistor MOS15 and N-channel of the transistor MOS9 of P-channel, the transistor MOS12 of P-channel, N-channel
Transistor MOS16；
The source electrode of transistor MOS9 is connect with the current source of the source electrode of transistor MOS12 and outside respectively；
The drain electrode of transistor MOS9 respectively with the drain electrode of transistor MOS15, the grid of transistor MOS15, sluggish processing unit with
And integrate converting unit connection；
The drain electrode of transistor MOS12 respectively with the drain electrode of transistor MOS16, the grid of transistor MOS16, sluggish processing unit with
And integrate converting unit connection；
The source electrode of transistor MOS15 and the source grounding of transistor MOS16；
The grid of transistor MOS9 is connect with the grid of transistor MOS10；The grid of transistor MOS12 is with transistor MOS11's
Grid connection.
5. a kind of rail-to-rail high-performance comparator according to claim 4, it is characterised in that: described to integrate converting unit packet
Include the transistor MOS3 of the P-channel and transistor MOS8 of P-channel；The grid of transistor MOS3 and the grid of transistor MOS5 connect
It connects；
The grid of transistor MOS8 is connect with the grid of transistor MOS6；
The source electrode of transistor MOS3 source electrode and transistor MOS8 are connect with external power supply；
The drain electrode of transistor MOS3 connects with the one input end of the drain electrode of transistor MOS16 and rear class differential amplification unit respectively
It connects；
Another input terminal with the drain electrode of transistor MOS15 and rear class differential amplification unit respectively that drains of transistor MOS8
Connection.
6. a kind of rail-to-rail high-performance comparator according to claim 5, it is characterised in that: the sluggishness processing unit packet
Include the transistor MOS4 of P-channel, the transistor MOS7 of P-channel, the transistor MOS14 of N-channel and the transistor of N-channel
MOS17；
The grid of transistor MOS4 is connect with the drain electrode of the grid of transistor MOS5 and transistor MOS7 respectively；
The grid of transistor MOS7 is connect with the drain electrode of the grid of transistor MOS6 and transistor MOS4 respectively；
The source electrode of transistor MOS4, the source electrode of transistor MOS7 are connect with external power supply；
The grid of transistor MOS17 is connect with the drain electrode of the grid of transistor MOS16 and transistor MOS14 respectively；
The grid of transistor MOS14 is connect with the drain electrode of the grid of transistor MOS15, transistor MOS17 respectively；
The source electrode of transistor MOS14 and the source electrode ground connection of transistor MOS17.
7. a kind of rail-to-rail high-performance comparator according to claim 6, it is characterised in that: the rear class differential amplification list
Member includes the transistor MOS1 of P-channel, the transistor MOS2 of P-channel, the transistor MOS13 of N-channel and the transistor of N-channel
MOS18；
The grid of transistor MOS13 is connect with the drain electrode of transistor MOS8；
Transistor MOS13 drain electrode respectively with the drain electrode of transistor MOS1, the grid of transistor MOS1, transistor MOS2 grid
Connection；
The grid of transistor MOS18 is connect with the drain electrode of transistor MOS13；
The source electrode of transistor MOS13 and the source grounding of transistor MOS18；
The source electrode of transistor MOS1 is connect with the source electrode of transistor MOS2 with external power supply；
Amplified signal compared with the drain electrode of transistor MOS2 is connected and exported with the drain electrode of transistor MOS18.
8. a kind of rail-to-rail high-performance comparator according to claim 1, it is characterised in that: further include phase inverter U1, instead
The input terminal of phase device U1 is connect with the output end of rear class differential amplification unit.
9. a kind of rail-to-rail high-performance comparator according to claim 1, it is characterised in that: the described first primary difference is put
Big unit is made of NPN type triode.
10. a kind of rail-to-rail high-performance comparator according to claim 1, it is characterised in that: the described second primary difference
Amplifying unit is made of PNP type triode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811507731.XA CN109714031B (en) | 2018-12-11 | 2018-12-11 | Rail-to-rail high-performance comparator |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811507731.XA CN109714031B (en) | 2018-12-11 | 2018-12-11 | Rail-to-rail high-performance comparator |
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| Publication Number | Publication Date |
|---|---|
| CN109714031A true CN109714031A (en) | 2019-05-03 |
| CN109714031B CN109714031B (en) | 2023-03-17 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201811507731.XA Active CN109714031B (en) | 2018-12-11 | 2018-12-11 | Rail-to-rail high-performance comparator |
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Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1274171A1 (en) * | 2001-07-05 | 2003-01-08 | Telefonaktiebolaget L M Ericsson (Publ) | Differential line receiver |
| CN1845452A (en) * | 2005-04-07 | 2006-10-11 | 恩益禧电子股份有限公司 | Op Amps with Smaller Offset |
| CN101170299A (en) * | 2006-10-27 | 2008-04-30 | 恩益禧电子股份有限公司 | Operational Amplifiers and Display Devices |
| CN101557216A (en) * | 2009-03-05 | 2009-10-14 | 深圳市民展科技开发有限公司 | Comparator and D-class audio power amplifier comprising comparator |
| CN101645693A (en) * | 2008-08-05 | 2010-02-10 | 恩益禧电子股份有限公司 | Class AB amplifier circuit and display apparatus |
| CN108832916A (en) * | 2018-06-22 | 2018-11-16 | 安徽传矽微电子有限公司 | A kind of high-speed low-power-consumption comparator circuit of low dynamic imbalance |
-
2018
- 2018-12-11 CN CN201811507731.XA patent/CN109714031B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1274171A1 (en) * | 2001-07-05 | 2003-01-08 | Telefonaktiebolaget L M Ericsson (Publ) | Differential line receiver |
| CN1845452A (en) * | 2005-04-07 | 2006-10-11 | 恩益禧电子股份有限公司 | Op Amps with Smaller Offset |
| CN101170299A (en) * | 2006-10-27 | 2008-04-30 | 恩益禧电子股份有限公司 | Operational Amplifiers and Display Devices |
| CN101645693A (en) * | 2008-08-05 | 2010-02-10 | 恩益禧电子股份有限公司 | Class AB amplifier circuit and display apparatus |
| CN101557216A (en) * | 2009-03-05 | 2009-10-14 | 深圳市民展科技开发有限公司 | Comparator and D-class audio power amplifier comprising comparator |
| CN108832916A (en) * | 2018-06-22 | 2018-11-16 | 安徽传矽微电子有限公司 | A kind of high-speed low-power-consumption comparator circuit of low dynamic imbalance |
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| CN109714031B (en) | 2023-03-17 |
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