CN109710536A - A kind of system and method automatically extracting FPGA software verification result simulation waveform - Google Patents
A kind of system and method automatically extracting FPGA software verification result simulation waveform Download PDFInfo
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- CN109710536A CN109710536A CN201811644696.6A CN201811644696A CN109710536A CN 109710536 A CN109710536 A CN 109710536A CN 201811644696 A CN201811644696 A CN 201811644696A CN 109710536 A CN109710536 A CN 109710536A
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Abstract
The invention discloses a kind of system and methods for automatically extracting FPGA software verification result simulation waveform, it is related to FPGA software verification field, this method includes inputting the surveying range information of tested FPGA software, it is emulated using corresponding program of the EDA digital simulation tools to tested FPGA software, obtain simulation document, the emulation data for selecting respective bins in the simulation document according to the surveying range information, generate the surveying range simulation waveform.A kind of system and method automatically extracting FPGA software verification result simulation waveform provided by the invention, user is after input measurement block information, the emulation data of respective bins can be selected in simulation document, automatically generate surveying range simulation waveform, a large amount of manual operation is avoided, the degree of automation of verifying is improved.
Description
Technical field
The present invention relates to FPGA software verification fields, and in particular to one kind automatically extracts FPGA software verification result emulation wave
The system and method for shape.
Background technique
FPGA Digital Simulation is the important means of FPGA software testing and verification, is widely used in FPGA software test and IC
Verifying.Currently, evaluation and test mechanism and IC verifying department generally use expected result and quilt when carrying out the emulation of FPGA software digital
The mode of part reality output Comparative result is surveyed, to verify whether software function meets design requirement.
In entire verification process, generally requires verifying engineer and grab verifying moment correlation one by one by emulation tool
The waveform diagram of signal records in this, as verifying and tests evidence.This process is very complicated, and when needing to spend a large amount of
Between.Again with the continuous growth of FPGA software size and design complexity and regression test stage a large amount of test cases
It executes, and returns the substantial increase of round, the number of signals for needing to grab increases severely therewith, manually adds signal one by one and grabs
The working method for taking waveform has been unable to satisfy the demand of verifying work.
Currently, this makes there are no a kind of system and method for automatically extracting FPGA software verification result simulation waveform
The time cost of FPGA project verification and testing manpower is high, therefore is badly in need of design and automatically extracts FPGA software verification result emulation wave
The system and method for shape.
Summary of the invention
In view of the deficiencies in the prior art, the purpose of the present invention is to provide one kind to automatically extract FPGA software verification
As a result the system and method for simulation waveform, user can select respective bins after input measurement block information in simulation document
Emulation data, automatically generate surveying range simulation waveform, avoid a large amount of manual operation, improve the automation of verifying
Degree.
To achieve the above objectives, the technical solution adopted by the present invention is that:
Input the surveying range information of tested FPGA software；
It is emulated using corresponding program of the EDA digital simulation tools to tested FPGA software, obtains simulation document；
The emulation data for selecting respective bins in the simulation document according to the surveying range information, generate the survey
Measure section simulation waveform.
Based on the above technical solution, the surveying range information includes at least time range parameter.
Based on the above technical solution, the surveying range information further includes signal name and signal path.
Based on the above technical solution, the EDA digital simulation tools are one in QuestaSim or Modelsim
Kind.
Based on the above technical solution, after inputting the surveying range information of tested FPGA, by least one institute
Stating surveying range Information encapsulation is configuration file.
It based on the above technical solution, include multiple and different surveying range information in the configuration file,
Each surveying range information includes signal name, signal path and time range parameter.
Based on the above technical solution, respective area is selected in the simulation document according to the surveying range information
Between emulation data, generating the surveying range simulation waveform includes:
The configuration file is parsed, multiple surveying range information are obtained；
According to multiple surveying range information, the emulation data of respective bins are selected in the simulation document, according to
Multiple described surveying range simulation waveforms of the Generation of simulating data of the respective bins.
The invention also includes a kind of systems for automatically extracting FPGA software verification result simulation waveform comprising:
Input module is used to input the surveying range information of tested FPGA software；
Emulation module is used to be emulated using corresponding program of the EDA digital simulation tools to tested FPGA software, be obtained
To simulation document；
Graph generation module is used to select respective bins in the simulation document according to the surveying range information
Data are emulated, the surveying range simulation waveform is generated.
Based on the above technical solution, the input module be also used to be by multiple surveying range Information encapsulations
Configuration file, and each surveying range information includes signal name, signal path and time range parameter.
Based on the above technical solution, the graph generation module is also used to:
The configuration file is parsed, multiple surveying range information are obtained；
According to multiple surveying range information, the emulation data of respective bins are selected in the simulation document, according to
Multiple described surveying range simulation waveforms of the Generation of simulating data of the respective bins.
Compared with the prior art, the advantages of the present invention are as follows:
A kind of system and method automatically extracting FPGA software verification result simulation waveform provided by the invention, passes through input
After the surveying range information of tested FPGA, it is configuration file by surveying range Information encapsulation, emulation is analyzed according to configuration file
File, according to parameters such as the signal names, signal path and time range parameter recorded in surveying range information in simulation document
The emulation data of middle selection respective bins, automatically generate surveying range simulation waveform.This alleviates craft for verifying engineer
The workload for grabbing waveform diagram, substantially increases the verification efficiency of FPGA software, and it is low to solve reusability and working efficiency
Problem, has saved human time, and application prospect is good.
Detailed description of the invention
Fig. 1 is the flow chart of the method for automatically extracting FPGA software verification result simulation waveform in the embodiment of the present invention.
Specific embodiment
The embodiment of the present invention is described in further detail below in conjunction with attached drawing.
Shown in Figure 1, the embodiment of the present invention provides a kind of side for automatically extracting FPGA software verification result simulation waveform
Method, method includes inputting the surveying range information of tested FPGA software first, then using EDA digital simulation tools to tested
The corresponding program of FPGA software is emulated, and simulation document is obtained, and is finally selected in simulation document according to surveying range information
The emulation data of respective bins generate surveying range simulation waveform.
Wherein, surveying range information includes at least time range parameter, by the time range parameter of surveying range information,
When selecting the emulation data of respective bins in simulation document according to surveying range information in the later period, then as the mark of selection
Standard, i.e. emulation data in selection simulation document in same time range parameter, finally automatically generate surveying range simulation waveform
Figure.Operator according to demand, inputs corresponding surveying range information, corresponding surveying range simulation waveform is obtained, to make
For verifying record and test evidence, convenient and efficient, high degree of automation.Wherein, after the completion of each surveying range information input, behaviour
Making personnel can assign each surveying range information one ID number, when the later period it is corresponding generate surveying range simulation waveform when, it is right
The picture name for the surveying range simulation waveform answered is above-mentioned ID number, on the one hand can make the surveying range simulation waveform generated
On the other hand more preferable identification effectively accurately can identify each surveying range information by helper applications.
Further, generally comprise a plurality of signal inside surveying range information, a plurality of signal respectively include signal name and
Signal path.Due to emulating all information that obtained simulation document includes tested FPGA software, data volume is very huge, according to
The surveying range information of input selects the emulation data of respective bins in simulation document, generates surveying range simulation waveform.
However in entire simulation document, some signals have that title is identical, and then, surveying range information further comprises signal
Path can guarantee that the later period accurately selects the emulation data in corresponding correct section according to surveying range information in simulation document,
Ensure the accuracy of surveying range simulation waveform.
Further, EDA digital simulation tools are one of QuestaSim or Modelsim.Currently, the software of EDA
There are many kinds of, such as QuestaSim the and Modelsim simulation software of Mentor company, the VCS of Synopsys company, and here
Only for QuestaSim the and Modelsim simulation software of Mentor company, Modelsim is the classic language of industry
Emulator can provide friendly debugging enironment, be the first choice for the RTL level and gate level circuit emulation for making FPGA and ASIC design, and
QuestaSim is first measured monokaryon validation engine, is integrated with a HDL simulator, a constraint solver, one
A judgement engine and functional coverage and a general user interface.
Further, after inputting the surveying range information of tested FPGA software, by least one surveying range Information encapsulation
It may include one or more different surveying range information for configuration file, in configuration file.Specifically, according to the reality of user
Border demand can input multiple surveying range information in the incipient stage, and multiple surveying range information include signal name, signal
Path and time range parameter, are encapsulated as configuration file, and respective area is selected in simulation document further according to surveying range information
Between emulation data, each surveying range information can generate a surveying range simulation waveform.
Specifically, selecting phase in simulation document according to surveying range information when generating surveying range simulation waveform
The step of answering the emulation data in section, generating surveying range simulation waveform includes parsing configuration file first, obtaining multiple surveys
Amount block information then according to multiple surveying range information is analyzed simulation document, by it with multiple surveying ranges
The situation of change that information respectively corresponds the period extracts, and successively carries out figure respectively further according to the data extracted and draws
System obtains the surveying range simulation waveform of user's needs.
Further, simulation document is a kind of VCD file here, and VCD is a kind of general format, and VCD file is
In Verilog HDL language standard, a kind of ascii text file defined in IEEE1364 standard.VCD file mainly contains head letter
Breath, predefined and variate-value the change information of variable, exactly because it contains the change information of signal, then, just quite
In the information for having recorded entire simulation process, therefore, user can be with this file and by EDA digital simulation tools come again
Now emulate.
The present invention also provides a kind of system for automatically extracting FPGA software verification result simulation waveform, system includes input
Module, emulation module and graph generation module.
Specifically, input module is used to input the surveying range information of tested FPGA software, emulation module is used to use EDA
Digital simulation tools emulate the corresponding program of tested FPGA software, obtain simulation document, and graph generation module is then used for
The emulation data of respective bins are selected in simulation document according to surveying range information, generate surveying range simulation waveform.
Wherein, surveying range information includes at least time range parameter, by the time range parameter of surveying range information,
When graph generation module selects the emulation data of respective bins according to surveying range information in simulation document, as selection
Standard generates surveying range simulation waveform.
Further, input module is also used to multiple surveying range Information encapsulations be configuration file, and each measurement zone
Between information include signal name, signal path and time range parameter.Specifically, according to the actual demand of user, Ke Yi
Incipient stage, multiple surveying range information are inputted on input module, multiple surveying range information include signal name, signal
Path and time range parameter, are encapsulated as configuration file, emulation module to tested FPGA software emulation during formed it is imitative
True file, graph generation module select the emulation data of respective bins according to surveying range information in simulation document, each
Surveying range information can generate a surveying range simulation waveform.
After system is by inputting the surveying range information of tested FPGA software, surveying range information is encapsulated as configuration text
Part analyzes simulation document according to configuration file, according to the signal name, signal path and time recorded in surveying range information
The parameters such as range parameter select the emulation data of respective bins in simulation document, automatically generate surveying range simulation waveform.
This is the workload verified engineer and alleviate crawl waveform diagram by hand, substantially increases the verification efficiency of FPGA software, solves
Reusability and the low problem of working efficiency, have saved human time, application prospect is good.
The present invention is not only limited to above-mentioned preferred forms, anyone can show that other are each under the inspiration of the present invention
The product of kind form, however, make any variation in its shape or structure, it is all with identical or similar with the present invention
Technical solution, within its protection scope.
Claims (10)
1. a kind of method for automatically extracting FPGA software verification result simulation waveform, characterized in that it comprises:
Input the surveying range information of tested FPGA software；
It is emulated using corresponding program of the EDA digital simulation tools to tested FPGA software, obtains simulation document；
The emulation data for selecting respective bins in the simulation document according to the surveying range information, generate the measurement zone
Between simulation waveform.
2. a kind of method for automatically extracting FPGA software verification result simulation waveform as described in claim 1, it is characterised in that:
The surveying range information includes at least time range parameter.
3. a kind of method for automatically extracting FPGA software verification result simulation waveform as claimed in claim 2, it is characterised in that:
The surveying range information further includes signal name and signal path.
4. a kind of method for automatically extracting FPGA software verification result simulation waveform as claimed in claim 3, it is characterised in that:
The EDA digital simulation tools are one of QuestaSim or Modelsim.
5. a kind of method for automatically extracting FPGA software verification result simulation waveform as described in claim 1, it is characterised in that:
It is configuration file by least one described surveying range Information encapsulation after inputting the surveying range information of tested FPGA.
6. a kind of method for automatically extracting FPGA software verification result simulation waveform as claimed in claim 5, it is characterised in that:
It include multiple and different surveying range information in the configuration file, each surveying range information includes signal name
Title, signal path and time range parameter.
7. a kind of method for automatically extracting FPGA software verification result simulation waveform as claimed in claim 6, which is characterized in that
It is imitative to generate the surveying range for the emulation data for selecting respective bins in the simulation document according to the surveying range information
True waveform diagram includes:
The configuration file is parsed, multiple surveying range information are obtained；
According to multiple surveying range information, the emulation data of respective bins are selected in the simulation document, according to described
Multiple described surveying range simulation waveforms of the Generation of simulating data of respective bins.
8. a kind of system for automatically extracting FPGA software verification result simulation waveform, characterized in that it comprises:
Input module is used to input the surveying range information of tested FPGA software；
Emulation module is used to be emulated using corresponding program of the EDA digital simulation tools to tested FPGA software, be imitated
True file；
Graph generation module is used to select the emulation of respective bins in the simulation document according to the surveying range information
Data generate the surveying range simulation waveform.
9. a kind of system as claimed in claim 8, characterized in that it comprises: the input module is also used to multiple institutes
State surveying range Information encapsulation be configuration file, and each surveying range information include signal name, signal path and
Time range parameter.
10. a kind of system as claimed in claim 8, which is characterized in that it includes,
The graph generation module is also used to:
The configuration file is parsed, multiple surveying range information are obtained；
According to multiple surveying range information, the emulation data of respective bins are selected in the simulation document, according to described
Multiple described surveying range simulation waveforms of the Generation of simulating data of respective bins.
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN112949233A (en) * | 2021-03-08 | 2021-06-11 | 北京士昌鼎科技有限公司 | Automatic development method and device of FPGA chip and electronic equipment |
| CN114398217A (en) * | 2022-01-21 | 2022-04-26 | 湖南泛联新安信息科技有限公司 | A Massive Simulation Waveform Data Slicing Method for FPGA Parallel Simulation |
| CN114510902A (en) * | 2022-04-20 | 2022-05-17 | 北京芯愿景软件技术股份有限公司 | Simulation result verification method, device, equipment and computer storage medium |
| CN114519279A (en) * | 2022-04-20 | 2022-05-20 | 北京芯愿景软件技术股份有限公司 | Simulation result verification method, device, equipment and computer storage medium |
| CN114398217B (en) * | 2022-01-21 | 2025-04-11 | 湖南泛联新安信息科技有限公司 | A method for slicing massive simulation waveform data for FPGA parallel simulation |
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| Publication number | Priority date | Publication date | Assignee | Title |
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