CN109690783B - Method of forming P-type layer of light emitting device - Google Patents

Abstract

In a method according to an embodiment of the present invention, a semiconductor structure is grown, the semiconductor structure including a III-nitride light emitting layer disposed between a p-type region and an n-type region. The p-type region is buried within the semiconductor structure. A trench is formed in a semiconductor structure. The trench exposes the p-type region. After the trenches are formed, the semiconductor structure is annealed.

Description

Method of forming P-type layer of light-emitting device

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims priority from US Provisional Patent Application No. 62/339,448, filed on May 20, 2016, and European Patent Application No. 16179661.0, filed on July 15, 2016. US Provisional Patent Application No. 62/339,448 and European Patent Application No. 16179661.0 are incorporated herein.

Background technique

Semiconductor light-emitting devices, including light-emitting diodes (LEDs), resonant cavity light-emitting diodes (RCLEDs), vertical cavity laser diodes (VCSELs), and edge-emitting lasers, are among the most efficient light sources currently available. Materials systems of current interest in the fabrication of high-brightness light-emitting devices capable of operating across the visible spectrum include III-V semiconductors, particularly binary, ternary, and quaternary alloys of gallium, aluminum, indium, and nitrogen, also known as It is a group III nitride material. Typically, by metal organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE) or other epitaxy techniques, by epitaxial growth on sapphire, silicon carbide, III-nitride or other suitable substrates with different compositions and doping A group III nitride light-emitting device is fabricated by stacking semiconductor layers with dopant concentrations. The stack often includes one or more n-type layers doped with eg Si formed over a substrate, one or more light-emitting layers formed in an active region over the one or more n-type layers, and One or more p-type layers doped with eg Mg are formed over the active region. Electrical contacts are formed on the n-type and p-type regions.

In commercial Ill-nitride LEDs, semiconductor structures are typically grown by MOCVD. The nitrogen source used during MOCVD is typically ammonia. When ammonia dissociates, hydrogen is produced. Hydrogen forms a complex with magnesium, which is used as a p-type dopant during growth of the p-type material. The hydrogen complex deactivates the p-type characteristic of magnesium, effectively reducing the dopant concentration of the p-type material, which reduces the efficiency of the device. After the growth of the p-type material, the structure is annealed to destroy the hydrogen-magnesium complex by driving out hydrogen.

Description of drawings

FIG. 1 illustrates a portion of a semiconductor structure including a buried p-type region and a trench for activating the p-type region.

FIG. 2 illustrates a portion of the top surface of the structure illustrated in FIG. 1 .

3 is a method of forming a device having a buried p-type region in accordance with some embodiments of the invention.

4 illustrates an LED with a p-type region grown before an n-type region, according to some embodiments of the present invention.

Figure 5 illustrates an LED including a tunnel junction according to some embodiments of the present invention.

6 illustrates a device including two LEDs separated by a tunnel junction, according to some embodiments of the present invention.

7 illustrates a portion of a partially grown semiconductor device including segments of mask material.

8 illustrates a portion of a semiconductor device with embedded trenches.

9 illustrates a portion of a semiconductor device including a trench in which metal contacts are provided.

Detailed ways

The need for annealing in a hydrogen-free atmosphere to activate p-type layers in Ill-nitride devices limits device design. It has been experimentally demonstrated that hydrogen cannot diffuse through n-type III-nitride materials, and that hydrogen does not readily diffuse laterally through semiconductor materials over a distance corresponding to half the diameter of a typical device wafer. As a result, for activation annealing to be effective, the p-type layer cannot be covered by any other layer. Without effective annealing, the device has no p-type layer, or has a p-type layer with very low dopant concentrations, rendering it useless. Therefore, devices with buried p-type layers (such as devices with tunnel junctions or devices in which the p-type layer is grown before the n-type layer) cannot be formed by conventional processes, including growth by MOCVD followed by annealing.

In an embodiment of the invention, a device structure with a buried p-type layer is grown. A trench is formed in the device structure that exposes the portion of the buried p-type layer. The structure is then annealed so that hydrogen can diffuse laterally out of the buried p-type layer to the trenches where it can escape to the outside environment.

FIG. 1 illustrates a portion of a semiconductor device structure. The structure of FIG. 1 is grown on a growth substrate 30, which may be, for example, sapphire, SiC, Si, non-Ill-nitride materials, GaN, a composite substrate, or any other suitable substrate. The optional III-nitride film 102 may be grown before the p-type region 100, however the III-nitride film 102 is not required. The Ill-nitride film 102 may include, for example, a nucleation or buffer layer, a smoothing layer which may be GaN or any other Ill-nitride material, an n-type layer, an emissive or active layer, an undoped layer, a device's active regions, and/or any other suitable layers or materials.

The p-type region 100 includes at least one binary, ternary, quaternary, or pentaary Ill-nitride layer doped with a p-type dopant such as, for example, Mg or any other suitable material.

The III-nitride film 104 is grown after the p-type layer 100 so that the p-type layer 100 is buried by the III-nitride film 104 . Ill-nitride film 104 may include n-type layers, p-type layers, active regions of the device, light emitting layers, undoped layers, and/or any other suitable layers or materials.

After or during growth, trenches 106 are formed in the semiconductor structure. As illustrated in FIG. 1 , trench 106 may extend through the entire thickness of Group III-nitride film 104 such that the bottom of trench 106 is in p-type region 100 . Alternatively, trench 106 may extend through the entire thickness of both Ill-nitride film 104 and p-type region 100 such that the bottom of trench 106 is in Ill-nitride film 102 and is the surface of growth substrate 30 or into the growth substrate 30 .

The width 108 of the trench 106 may be, for example, at least 0.05 μm in some embodiments, no more than 50 μm in some embodiments, at least 0.5 μm in some embodiments, and no more than 15 μm in some embodiments. In some embodiments, the trenches are kept as small as possible to avoid loss of light emitting area.

The trenches 106 are separated such that all of the p-type regions 100 are separated from the trenches by a distance that does not exceed the maximum diffusion length of hydrogen during subsequent annealing. The maximum separation 110 between trenches 106 may be twice the average or maximum diffusion length of hydrogen during annealing. The spacing 110 may be determined by the conditions of the anneal, which may determine the maximum lateral diffusion length of hydrogen during the annealing (different anneals may have different maximum lateral diffusion lengths). The maximum separation 110 between nearest adjacent trenches may be at least 1 μm in some embodiments, no more than 500 μm in some embodiments, at least 5 μm in some embodiments, and no more than 250 μm in some embodiments .

The semiconductor structure illustrated in FIG. 1 may be annealed after the trenches 106 are formed. During the anneal, hydrogen is driven from the p-type region 100 into the trench 106 where it can escape from the semiconductor structure to the outside environment.

In some embodiments, after annealing, trenches 106 may be filled with insulating material 114 . The insulating material 114 allows metal contacts to be formed on surfaces with trenches without inadvertently causing short circuits. The insulating material 114 may be formed at any stage of processing after annealing, eg, in embodiments where the growth substrate is removed, the trenches 106 may be filled with insulating material 114 before or after removal of the growth substrate, or performed to expose In embodiments of etching of buried layers, trenches 106 may be filled with insulating material 114 before or after such etching.

In some embodiments, as illustrated in FIG. 9 , trenches 106 are used as vias in which metal contacts are formed to contact p-type regions in p-side down devices. In embodiments where metal contacts 134 are formed in trenches 106 in contact with p-type regions 100, a series of metal and insulators are deposited and patterned such that the metal contacts only contact the buried p-type regions 100 or other desired The layer is in direct contact (as illustrated in FIG. 9 , at the bottom of trench 132 ), but not with the layer above (Ill-nitride film 104 ). For example, insulating material 130 may be disposed on the sidewalls of the trench between the contact metal 134 and the semiconductor layer that is not in direct contact with the metal contact.

In some embodiments, trenches 106 are exposed to air or ambient gas, or are coated rather than filled with a thin passivation layer (eg, SiO ₂ ). Accordingly, in some embodiments, trench 106 may be partially or fully filled with insulating or passivation material.

FIG. 2 is a plan view of a portion of the top surface 112 of the structure of FIG. 1 . As illustrated in FIG. 2 , in some embodiments, the trenches 106 may be isolated from each other and surrounded by a portion of the semiconductor structure that is not interrupted by the trenches. Accordingly, in some embodiments, the semiconductor material is all electrically connected, and no electrically isolated islands of semiconductor material are formed by trenches 106 . In some embodiments, some or all of the trenches may be connected to each other to form isolated islands of semiconductor material, eg, in some embodiments, trenches 106 may define boundaries of individual devices that are subsequently separated from a wafer of semiconductor material. A single device formed on a wafer of devices may have trenches that connect to each other to define the boundaries of the device or isolated islands of semiconductor material within the device; and one or more other trenches that are isolated from each other and formed within isolated islands of semiconductor material.

3 illustrates a method of forming a device. In block 120, a III-nitride structure with buried p-type regions is grown on the growth substrate.

In block 122, trenches 106 are formed in the grown Ill-nitride structure. The trenches 106 are illustrated in FIGS. 1 and 2 . The trenches 106 may be formed by any suitable technique including, for example, dry etching, wet etching, or a combination of dry and wet etching. In some embodiments, the method of forming the trench can affect the diffusion of hydrogen from the exposed surface of the semiconductor material formed by etching the trench. For example, p-type GaN is known to convert to n-type GaN during dry etching. If the thickness of the surface of the p-type converted to n-type is too large, the diffusion of hydrogen may be blocked such that hydrogen accumulates at the type-converted surface and cannot escape. Accordingly, in some embodiments, after the dry etching used to form the trenches 106, wet etching may be used to clean the surface of the trenches to remove the converted n-type layer or the converted n-type The thickness of the layer is reduced to a thickness through which hydrogen can easily diffuse.

In some embodiments, as illustrated in Figures 7 and 8, semiconductor structures may be selectively grown to form trenches during growth. For example, as illustrated in FIG. 7 , an optional III-nitride film 102 and p-type region 100 are grown over substrate 30 . A mask material 120 (such as SiO ₂ ) may be disposed on the p-type region 100 and then patterned such that the mask material remains in the regions where the trenches are formed. The mask material is not limited to the positions illustrated in FIG. 7 . For example, in various embodiments, as illustrated, the masking material is formed directly on the growth substrate, on the surface of the partially grown Ill-nitride film 102, on the fully grown Ill-nitride film 102 on the surface of the partially grown p-type region 100 or on the surface of the fully grown p-type region 100 . The masking material may be formed in any layer of the device, on any surface (including directly on the growth substrate 30 ) at any thickness, and may extend through multiple layers, as long as the masking material is associated with at least a portion of the p-type region 100 direct contact.

Group III nitride film 104 is grown over mask material 120 . As illustrated in Figure 8, the growth will eventually cover the mask material via lateral overgrowth such that the regions 122 between adjacent mask regions are filled with the Ill-nitride material. When the die is singulated after growth, wet etching or other suitable techniques can be used to remove the masking material, creating embedded trenches 124 through which hydrogen can pass during the activation anneal escape. During the activation anneal, hydrogen escapes from the embedded trenches through the sides of the wafer, where the embedded trenches are exposed to the outside environment.

Returning to FIG. 3, in block 124, the Ill-nitride structure with trenches is annealed to activate the buried p-type region (eg, by driving off the p-type dopant that has formed a complex in the p-type region) of hydrogen).

FIGS. 4 , 5 and 6 illustrate devices including buried p-type regions that can be activated by trench formation and annealing, as illustrated in FIGS. 1 , 2 and 3 . Figure 4 illustrates a device with p-type regions grown before n-type regions. 5 and 6 illustrate a device including a tunnel junction. The trenches are omitted from FIGS. 4 , 5 and 6 for clarity. In particular, the devices illustrated in Figures 4, 5 and 6 can be, for example, on the order of 1 mm on one side, meaning that tens or even hundreds of trenches can be formed in a single device. In any of the devices illustrated in Figures 4, 5 and 6, one or more of the trenches may be used as vias in which metal contacts to buried layers of the device are provided , as described above.

In some embodiments, the p-type region of the Ill-nitride device is grown before the light-emitting layer and the n-type region.

In conventional III-nitride LEDs, the n-type region is grown on the substrate first, followed by the light-emitting layer and p-type semiconductor. The internal field of n-side down-grown Ill-nitride LEDs increases with increasing forward bias. As a result, as the device bias (current) increases, the internal electric field increases, reducing electron hole overlap and thus radiation efficiency. The device is grown in reverse order (where the p-type region is grown on the substrate first), inverting the internal field. In p-side down-grown Ill-nitride LEDs, the internal field is opposite to the built-in polarization field. As a result, the radiation efficiency of such a device can be increased when the forward bias (current) is increased.

Figure 4 illustrates one example of a device in which the p-type region is grown before the light-emitting layer and the n-type region. Such semiconductor structures may be incorporated into any suitable device; embodiments of the invention are not limited to the illustrated vertical devices. In embodiments where the initial growth substrate is removed (such as, for example, flip-chip devices), structures 102 may be completely removed to make electrical connections to the p-type regions, and/or holes/trenches may be etched through structures 102 The trenches expose a portion of the p-type region on which metal contacts may be formed. In substrate-retained embodiments, such as, for example, lateral die devices, one contact may be provided on the top surface of the semiconductor structure and the other contact may be provided on the etch through the etch to expose the p-type region. on exposed surfaces.

The device illustrated in FIG. 4 includes a semiconductor structure 10 grown on a growth substrate (not shown). The p-type region 12 is grown first, followed by the light-emitting or active region comprising at least one light-emitting layer 14, followed by the n-type region 16 .

The p-type region 12 corresponds to the buried p-type region 100 of FIG. 1; the active region 14 and the n-type region 16 correspond to the III-nitride film 104 of FIG. 1; the III-nitride film 102 of FIG. The core structure or buffer structure (not shown) may alternatively be omitted.

Metal p-contact 18 is provided on p-type region 12 ; metal n-contact 20 is provided on n-type region 16 .

The semiconductor structure 10 includes a light emitting or active region sandwiched between an n-type region and a p-type region. The n-type region 16 may include multiple layers with different compositions and dopant concentrations, including, for example, n-type device layers or even p-type device layers designed for specific optical, material, or electrical properties that are important for It is desirable to have the light-emitting region emit light efficiently. The light emitting layer 14 may be included in the light emitting region or the active region. Examples of suitable light emitting regions include a single thick or thin light emitting layer, or multiple quantum well light emitting regions comprising multiple thin or thick light emitting layers separated by barrier layers. p-type region 12 may include multiple layers of different compositions, thicknesses, and dopant concentrations, including preparation layers (such as buffer layers or nucleation layers) and/or layers designed to facilitate removal of the growth substrate ( It can be p-type, n-type or unintentionally doped) and unintentionally doped layers or n-type layers.

After growth, the semiconductor structure can be processed into any suitable device.

In some embodiments, the Ill-nitride device includes a tunnel junction. A tunnel junction (TJ) is a structure that allows electrons to tunnel from the valence band of the p-type layer to the conduction band of the n-type layer under reverse bias. When the electrons tunnel, holes remain in the p-type layer, so that carriers are generated in both layers. Thus, in electronic devices like diodes, where only small leakage currents flow under reverse bias, large currents can be carried across the tunnel junction under reverse bias. Tunnel junctions require specific alignment of conduction and valence bands at the p/n tunnel junction, which is already used in other material systems that use very high doping (eg, p++/n++ junctions in (Al)GaAs material systems) is typically implemented. Group III-nitride materials have inherent polarizations that create electric fields at heterointerfaces between different alloy components. This polarization field can be exploited to achieve the band alignment required for tunneling.

5 and 6 illustrate two devices including tunnel junctions.

In the device of Figure 5, a tunnel junction is provided between the p-type region and the metal contacts that inject current into the p-type region. The contact may be formed on an n-type layer, which may have better sheet resistance and thus better current spreading than p-type layers. In the device illustrated in Figure 5, the n-type layer is used as a contact layer for both the positive and negative terminals of the LED by converting holes from the p-type region to electrons in the n-type contact layer via a tunnel junction .

The device of FIG. 5 includes an n-type region 32 grown on a growth substrate, followed by a light-emitting layer 34 and p-type region 36 that may be disposed in the light-emitting region. The n-type region 32 , the light-emitting layer 34 , and the p-type region 36 are described above in the text accompanying FIG. 4 . Tunnel junction 38 is formed over p-type region 36 .

In some embodiments, tunnel junction 38 includes a highly doped p-type layer, also referred to as a p++ layer, in direct contact with p-type region 36; and a highly doped n-type layer, also referred to as an n++ layer, with The p++ layer is in direct contact. (In some embodiments, the p++ layer of tunnel junction 38 may be used as a p-type region in the device, so that a separate p-type region is not required.) In some embodiments, tunnel junction 38 includes a Layers of different compositions sandwiched between p++ and n++ layers. In some embodiments, the tunnel junction 38 includes an InGaN layer sandwiched between a p++ layer and an n++ layer. In some embodiments, tunnel junction 38 includes an AIN layer sandwiched between p++ and n++ layers. As described below, the tunnel junction 38 is in direct contact with the n-type layer 40 .

The p++ layer may be, for example, InGaN or GaN doped with an acceptor, such as Mg or Zn, at a concentration of about 10 ¹⁸ cm ⁻³ to about 5×10 ²⁰ cm ⁻³ . In some embodiments, the p++ layer is doped to a concentration of about 2×10 ²⁰ cm ⁻³ to about 4×10 ²⁰ cm ⁻³ . The n++ layer may be, for example, InGaN or GaN doped with an acceptor, such as Si or Ge, at a concentration of about 10 ¹⁸ cm ⁻³ to about 5×10 ²⁰ cm ⁻³ . In some embodiments, the n++ layer is doped to a concentration of about 7×10 ¹⁹ cm ⁻³ to about 9×10 ¹⁹ cm ⁻³ . The tunnel junction 38 is typically very thin, for example, the tunnel junction 38 may have an overall thickness ranging from about 2 nm to about 100 nm, and each of the p++ and n++ layers may have a thickness ranging from about 1 nm to about 50 nm thickness of. In some embodiments, each of the p++ layer and the n++ layer may have a thickness ranging from about 25 nm to about 35 nm. The p++ layer and the n++ layer may not necessarily be the same thickness. In one embodiment, the p++ layer is 15 nm of Mg-doped InGaN and the n++ layer is 30 nm of Si-doped GaN. The p++ and n++ layers may have progressively varying dopant concentrations. For example, a portion of the p++ layer adjacent to the underlying p-type region 36 may have a dopant concentration that varies from the dopant concentration of the underlying p-type region to the desired dopant concentration in the p++ layer . Similarly, the n++ layer may have a dopant concentration that ramps from a maximum value adjacent to the p++ layer to a minimum value adjacent to the n-type layer 40 formed over the tunnel junction 38 . The tunnel junction 38 is made sufficiently thin and sufficiently doped so that the tunnel junction 38 exhibits a low series voltage drop when conducting current in reverse biased mode. In some embodiments, the voltage drop across tunnel junction 38 is about 0.1V to about 1V.

Embodiments that include InGaN or AIN or other suitable layers between the p++ layer and the n++ layer may utilize the polarization field in the III-nitride to help align the bands for tunneling. This polarization effect can reduce doping requirements in the n++ and p++ layers and reduce the required tunneling distance (potentially allowing higher current flow). The composition of the layers between the p++ layer and the n++ layer may be different from the composition of the p++ layer and the n++ layer, and/or may be selected due to polarization charges that exist between the different materials in the III-nitride material system and realign the belt.

Examples of suitable tunnel junctions are described in US8039352 B2, which is incorporated herein by reference.

An n-type contact layer 40 is formed over the tunnel junction 38 in direct contact with the n++ layer.

In the device of FIG. 5, the p-type region 36 and the p++ layer of the tunnel junction 38 correspond to the p-type region 100 of FIG. 1; the n++ layer of the tunnel junction 38 and the n-type contact layer 40 correspond to the III-nitride film of FIG. 1 104 ; the n-type region 32 and the active region 34 correspond to the III-nitride film 102 of FIG. 1 .

First and second metal contacts 44 and 42 are formed on n-type contact layer 40 and on n-type region 32, respectively. The mesa may be etched to form a flip chip device, as illustrated in Figure 5, or any other suitable device structure may be used. The first and second metal contacts 44 and 42 may be the same material (such as aluminum), although this is not required; any suitable contact metal or metals may be used.

In the device of Figure 6, multiple LEDs are grown on top of each other and are connected in series via tunnel junctions. In the device of Figure 6, multiple LEDs are created within the footprint of a single LED, which can significantly increase the luminous flux generated per unit area. Additionally, by driving individual LEDs connected through a tunnel junction at lower drive currents, each LED can operate at its peak efficiency. In a single LED, this would result in a drop in light output, however, by having two or more LEDs in series in a given chip area, light output can be maintained while significantly improving efficiency. Thus, the tunnel junction device illustrated in Figure 6 can be used in applications requiring high efficiency and/or applications requiring high throughput per unit area.

The device of FIG. 6 includes an n-type region 32 grown on a growth substrate, followed by a light-emitting layer 34 that can be disposed in the light-emitting region, and a p-type region 36 (as described above, the p++ layer of the tunnel junction can be used as p-type region 36, so that a separate p-type region is not required). The n-type region 32 , the light-emitting layer 34 , and the p-type region 36 are described above in the text accompanying FIG. 4 . As described above, tunnel junction 38 is formed over p-type region 36 . A second device structure including a second n-type region 46 , a second light emitting layer 48 and a second p-type region 50 is formed over the tunnel junction 38 . The tunnel junction 38 is oriented such that the p++ layer is in direct contact with the p-type region 36 of the first LED and the n++ layer is in direct contact with the n-type region 46 of the second LED.

In the device of FIG. 6, p-type region 36 and the p++ layer of tunnel junction 38 correspond to p-type region 100 of FIG. 1; the n++ layer, n-type layer 46, active region 48, and p-type region 50 of tunnel junction 38 correspond to In the III-nitride film 104 of FIG. 1 (if the trench is in direct contact with the p-type region 50, the trench will also activate the p-type region 50, however the p-type region 50 can also be activated by conventional annealing (if it is The last grown layer)); the n-type region 32 and the active region 34 correspond to the III-nitride film 102 of FIG. 1 .

First and second metal contacts 54 and 52 are formed on the n-type region 32 of the first LED and on the p-type region 50 of the second LED, respectively. As illustrated in Figure 6, the mesas may be etched to form flip-chip devices, or any other suitable device structure may be used. In some embodiments, as illustrated in the device of FIG. 5, an additional tunnel junction and n-type layer may be formed over the p-type region 50 of the second LED to form a second metal contact on the n-type layer 52.

Although two active regions are illustrated in Figure 6, any number of active regions may be included between the two metal contacts illustrated, provided that the p-type region adjacent to each active region is tunneled The junction is separated from the n-type region adjacent to the next active region. Since the device of Figure 6 has only two contacts, both light emitting layers emit light at the same time and cannot be activated individually and independently. In other embodiments, individual LEDs in the stack can be activated independently by forming additional contacts. In some embodiments, the device may have sufficient junctions such that the device may operate at typical line voltages (such as, for example, 110 volts, 220 volts, etc.).

The two light-emitting layers can be prepared with the same composition such that they emit the same color of light, or with different compositions such that they emit light of different colors (ie, different peak wavelengths). For example, a three active area device with two contacts can be fabricated such that the first active area emits red light, the second active area emits blue light and the third active area emits green light. When activated, the device can produce white light. Since the active regions are stacked so that they appear to be emitting light from the same region, such a device can be avoided in devices that combine red, blue, and green light from adjacent active regions instead of stacked active regions There is a problem with color mixing. In devices where the active regions emit light of different wavelengths, the active region that generates the light of the shortest wavelength may be located closest to the surface from which the light is extracted (typically the sapphire, SiC or GaN growth substrate in LEDs). Placing the shortest wavelength active region close to the output surface can minimize losses due to absorption in the quantum well of another active region, and by positioning the longer wavelength active region closer to the heat sink formed by the contacts Instead, the thermal impact on the more sensitive longer wavelength quantum wells can be reduced. The quantum well layer can also be made thin enough so that the absorption of light in the quantum well layer is low. The color of the mixed light emitted from the device can be controlled by selecting the number of active regions that emit light of each color. For example, the human eye is very sensitive to green photons and not so sensitive to red and blue photons. To create balanced white light, a stacked active area device can have a single green active area and multiple blue and red active areas.

The devices of Figures 4, 5, and 6 are formed by growing a Group III-nitride semiconductor structure on a growth substrate 30, as is known in the art. The growth substrate is often sapphire, but can be any suitable substrate (such as, for example, SiC, Si, GaN, or a composite substrate (such as, for example, GaN on a sapphire template)). The surface of the growth substrate on which the III-nitride semiconductor structure is grown can be patterned, roughened, or textured prior to growth, which can improve light extraction from the device. The surface of the growth substrate opposite the growth surface (that is, the surface through which most of the light is extracted in a flip-chip configuration) can be patterned, roughened or textured before or after growth, which can improve the slave device light extraction.

Metal contacts often include multiple conductive layers, such as reflective metals and protective metals that can prevent or reduce electromigration of the reflective metals. The reflective metal is often silver, but any suitable material or materials can be used. The metal contacts are electrically isolated from each other by gaps, which may be filled with a dielectric such as an oxide of silicon or any other suitable material. Multiple vias may be formed to expose portions of n-type regions 32 ; the metal contacts are not limited to the arrangements illustrated in FIGS. 4 , 5 and 6 . The metal contacts can be redistributed to form pads with a dielectric/metal stack, as is known in the art.

To form electrical connections to the LEDs, one or more interconnects are formed on or electrically connected to the two metal contacts shown. The interconnects may be, for example, solder, bumps, gold layers, or any other suitable structure.

The substrate 30 may be thinned or completely removed. In some embodiments, the surface of substrate 30 exposed by thinning is patterned, textured, or roughened to improve light extraction.

Any of the devices described herein can be combined with wavelength converting structures. The wavelength converting structure may contain one or more wavelength converting materials. The wavelength converting structure may be directly connected to the LED, positioned in close proximity to the LED but not directly connected to the LED, or spaced apart from the LED. The wavelength converting structure can be any suitable structure. The wavelength conversion structure can be formed separately from the LED, or formed in situ with the LED.

Examples of wavelength-converting structures formed separately from LEDs include: ceramic wavelength-converting structures, which may be formed by sintering or any other suitable process; wavelength-converting materials (such as powder phosphors) disposed in transparent materials such as silicone or glass. body), the transparent material is rolled, cast, or otherwise formed into a sheet and then singulated into individual wavelength-converting structures; and wavelength-converting materials (such as powders) disposed in a transparent material such as silicone phosphor), the transparent material is formed as a flexible sheet that can be laminated or otherwise disposed over the LEDs.

Examples of in situ formed wavelength converting structures include wavelength converting materials (such as powdered phosphors) that are mixed with a transparent material such as silicone and dispensed, screen printed, stenciled, molded, or otherwise provided over the LED; and wavelength converting material coated on the LED by electrophoresis, evaporation, or any other suitable type of deposition.

Multiple forms of wavelength converting structures can be used in a single device. As just one example, a ceramic wavelength converting component may be combined with a molded wavelength converting component, having the same or different wavelength converting materials in the ceramic and molded component.

Wavelength converting structures may include, for example, conventional phosphors, organic phosphors, quantum dots, organic semiconductors, II-VI or III-V semiconductors, II-VI or III-V semiconductor quantum dots or nanocrystals, dyes, polymeric objects or other luminescent materials.

The wavelength converting material absorbs light emitted by the LED and emits light of one or more different wavelengths. The unconverted light emitted by the LED is often part of the final spectrum of light extracted from the structure, although this need not be the case. Examples of common combinations include blue emitting LEDs combined with yellow emitting wavelength converting materials, blue emitting LEDs combined with green and red emitting wavelength converting materials, UV emitting LEDs combined with blue and yellow emitting wavelength converting materials, and blue emitting LEDs combined with blue and yellow emitting wavelength converting materials. UV emitting LEDs with a combination of color, green and red emitting wavelength converting materials. Wavelength converting materials that emit light of other colors can be added to tune the spectrum of light extracted from the structure.

The embodiments described herein may be incorporated into any suitable light emitting device. Embodiments of the invention are not limited to the specific structures illustrated.

Some features of some embodiments may be omitted or implemented in other embodiments. Device elements and method elements described herein may be interchangeable and used or omitted from any of the examples or embodiments described herein.

Although in the examples and embodiments described above the semiconductor light emitting devices are Group III-nitride LEDs emitting blue or UV light, semiconductor light emitting devices other than LEDs, such as laser diodes, are also within the scope of the present invention. Additionally, the principles described herein may be applicable to semiconductor light emitting from other material systems such as other III-V materials, III-phosphides, III-arsenides, II-VI materials, ZnO, or Si-based materials device or other device.

The present invention has been described in detail, and those skilled in the art will recognize, given the present disclosure, that modifications may be made thereto without departing from the spirit of the inventive concepts described herein. Therefore, there is no intention to limit the scope of the invention to the specific embodiments shown and described.

Claims (18)

1. A method for selectively growing a semiconductor structure comprising at least one ill-nitride light emitting layer, at least one p-type region, and at least one n-type region, the method comprising:

forming a plurality of portions of a mask material on a surface;

growing the semiconductor structure around portions of a mask material;

after said growing said semiconductor structure around portions of a mask material, removing portions of said mask material to form a trench in said semiconductor structure that exposes a portion of said p-type region; and is

After the trenches are formed, the semiconductor structure is annealed so that hydrogen diffuses laterally out of the buried P-type layer into the trenches and then escapes to the ambient.

2. The method of claim 1, further comprising, after said annealing said semiconductor structure, filling said trench with an insulating material.

3. The method of claim 1, further comprising:

a metal is disposed in the trench, wherein the metal is in direct contact with a first portion of the semiconductor structure in the trench, and an insulating layer is disposed between the metal and a second portion of the semiconductor structure in the trench.

4. The method of claim 1, wherein the trench is a plurality of trenches.

5. The method of claim 4, wherein each trench is surrounded by a portion of the semiconductor structure that is not interrupted by the trench.

6. The method of claim 4, wherein nearest neighbor trenches are spaced less than twice a maximum diffusion length of hydrogen during annealing of the semiconductor structure.

7. The method of claim 1, wherein the semiconductor structure comprises a tunnel junction.

8. A method of forming a semiconductor device, the method comprising:

growing a p-type layer;

forming a mask layer in contact with at least a portion of the P-type layer, the mask layer comprising a trench exposing a portion of the P-type layer;

growing an n-type layer on the mask layer and the p-type layer; and is

The device is annealed so that hydrogen diffuses laterally out of the buried P-type layer into the trench and then escapes to the ambient.

9. The method of claim 8, further comprising:

forming at least one embedded trench by removing the mask layer, the at least one embedded trench exposing the at least a portion of the p-type layer to an ambient environment.

10. The method of claim 9, wherein the at least one embedded trench is a lateral embedded trench.

11. The method of claim 9, wherein the at least one embedded trench is a vertical embedded trench.

12. The method of claim 9, wherein the at least one embedded trench is a combination of a lateral embedded trench and a vertical embedded trench.

13. The method of claim 8, wherein the mask layer is a plurality of mask regions, each mask region in contact with a portion of the p-type layer.

14. The method of claim 9, further comprising:

the at least one trench is filled with an insulating material.

15. The method of claim 9, further comprising:

disposing a metal in the at least one trench, the metal in direct contact with a particular layer of the device; and is

An insulating layer is provided between the metal and other layers of the device to prevent contact between the metal and the other layers.

16. The method of claim 9, wherein the at least one embedded trench is surrounded by portions of at least one of the p-type layer or the n-type layer that are not interrupted by the at least one embedded trench.

17. The method of claim 9, wherein nearest neighbor trenches are spaced less than twice a maximum diffusion length of hydrogen during the annealing process.

18. The method of claim 8, further comprising:

and growing a tunnel junction on the p-type layer.

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