CN1096750C

CN1096750C - codec device

Info

Publication number: CN1096750C
Application number: CN 95104264
Authority: CN
Inventors: 陈永霖; 谢秋涼
Original assignee: Holtek Semiconductor Inc
Current assignee: Holtek Semiconductor Inc
Priority date: 1995-04-25
Filing date: 1995-04-25
Publication date: 2002-12-18
Anticipated expiration: 2015-04-25
Also published as: CN1134630A

Abstract

A high-efficient coding and decoding device is to use 2 positive integer power state number to achieve the purpose of increasing transmission capacity, reducing transmission data length and error rate and reducing number of pins representing data, the coding and decoding system includes two parts of coder and decoder, the coder part includes an oscillating circuit, a phase divider, an address array input device, a line scanner, a synchronizing circuit, a parallel to serial output device, the decoder includes an oscillating circuit, a frequency divider, an address array input device, a line scanner, a synchronizing signal for detecting data string, a counter decoding circuit, a comparison circuit, a 2ⁿThe decoder of the state data generator judges the data transmitted from the encoder and outputs parallel signals.

Description

Encoding/decoding device

The present invention relates to a kind of encoding/decoding device, refer in particular to a kind of can reaching and improve transmission capacity, reduce the encoding/decoding device that transmits data length and the pin count of error rate and minimizing representative data with a positive integer power status number of 2.

In the coding/decoding circuit that tradition becomes with integrated circuit (IC) design, have only two condition input and two kinds of code encoding/decoding modes of ternary input at present, and the circuit arrangement that technology constituted of this kind low state input mode has following shortcoming:

1. the two condition input needs [log when transmission N kind data are counted ₂N] individual input pin, more input pin causes higher cost on integrated circuit manufacturing and packing; Especially when the N value is big more, need the integrated circuit of high integration.

2. when ternary input mode is counted in transmission N kind data, need [log ₃N] individual input, though the input endpoint can be few than the two condition mode, can produce the problem that efficiency of transmission reduces, because data transmit with serial mode in transport process, three-state then needs two bits to represent so, so data transfer length will reach 2[log ₃N] individual bit, with 2[log4N] transmission length identical, this is because wasted the 4th kind of state institute extremely, and efficiency of transmission obviously reduces, and on identical transmission data number, also can improve because of transmitting the elongated probability that causes being disturbed of length.

Lift a simple case to above-mentioned defective to explanation: the input of two condition is to connect positive supply or ground connection to differentiate the state of its " 1 " or " 0 ".Ternary input is to connect positive supply, ground connection and do not meet (floating) differentiating its three kinds of states 11,00,10, and this moment, 01 state was not bright.The input of four attitudes is to connect positive supply, ground connection and clock, can differentiate its four kinds of states 11,00,10,01.

So the input of four attitudes will increase a pin.

Be the table of comparisons that different pins cooperates each state to produce below

The pin number	Two condition transmission number	Ternary transmission number	Four attitudes transmission number	Four attitudes/two condition compares number	Four attitudes/three-state compares number
The pin number	Two condition transmission number	Ternary transmission number	Four attitudes transmission number	Four attitudes/two condition compares number	Four attitudes/three-state compares number	6	64	729	1024	16.00	1.40
7	128	2187	4096	32.00	1.87	6	64	729	1024	16.00	1.40
7	128	2187	4096	32.00	1.87	8	256	6561	16384	64.00	2.50
9	512	19683	65536	128.00	3.33	8	256	6561	16384	64.00	2.50
9	512	19683	65536	128.00	3.33	10	1024	59049	262144	256.00	4.44
11	2048	177147	1048576	512.00	5.92	10	1024	59049	262144	256.00	4.44
11	2048	177147	1048576	512.00	5.92	12	4096	531441	4194304	1024.00	7.89
13	8192	1594323	16777216	2048.00	10.52	12	4096	531441	4194304	1024.00	7.89
13	8192	1594323	16777216	2048.00	10.52	14	16384	4782969	67108864	4096.00	14.03

The pin number	Two condition transmission number	Ternary transmission number	Four attitudes transmission number	Four attitudes/two condition compares number	Four attitudes/three-state compares number
The pin number	Two condition transmission number	Ternary transmission number	Four attitudes transmission number	Four attitudes/two condition compares number	Four attitudes/three-state compares number	15	32768	14348907	268435456	8192.00	18.71
16	65536	43046720	1073741824	16384.00	24.94	15	32768	14348907	268435456	8192.00	18.71
16	65536	43046720	1073741824	16384.00	24.94	17	131072	129140160	4294967296	32768.00	33.26
18	262144	387420480	17179869184	65536.00	44.34	17	131072	129140160	4294967296	32768.00	33.26
18	262144	387420480	17179869184	65536.00	44.34	19	524288	1162261594	68719476736	131072.00	59.13
20	104875	3486784256	274877906944	262144.00	78.83	19	524288	1162261594	68719476736	131072.00	59.13

Last example is when 6 identical pin counts, and total transmission number of two condition is 2 ⁶Ternary total transmission number is 3 ⁶Total transmission number of four attitudes is 4 ^6-1, subtract a pin and use for clock.

If total transmission number of four attitudes is compared with total transmission number of two condition and three-state respectively, can be found really that now the load mode of four attitudes has bigger transmission capacity at same pin count.In addition, under identical transmission length, four attitudes have the higher data transfer rate.Other lifts an example so that it to be described, each pin status data of ternary input needs [log2 ³]=2 bit; The input of four attitudes needs [log2 ⁴] also be 2 and compare number; The input of five attitudes then needs [log2 ⁵]=3 bit, if there is the serial data of one 12 bits (bit) to transmit, it transmits data and status number is listed as follows:

	Status data	The status data number that can transmit in 12 bits	The valid data number
	Status data	The status data number that can transmit in 12 bits	The valid data number	Ternary	[log2 ³]＝2	12/2＝6	3 ⁶＝729
Four attitudes	[log2 ⁴]＝2	12/2＝6	4 ⁶＝4096	Ternary	[log2 ³]＝2	12/2＝6	3 ⁶＝729
Four attitudes	[log2 ⁴]＝2	12/2＝6	4 ⁶＝4096	Five attitudes	[log2 ⁵]＝3	12/3＝4	5 ⁴＝625
Six attitudes	[log2 ⁶]＝3	12/3＝4	6 ⁴＝1296	Five attitudes	[log2 ⁵]＝3	12/3＝4	5 ⁴＝625
Six attitudes	[log2 ⁶]＝3	12/3＝4	6 ⁴＝1296	Seven attitudes	[log2 ⁷]＝3	12/3＝4	7 ⁴＝2401

The objective of the invention is for a kind of encoding/decoding device is provided, its positive integer power status number with 2 reaches the purpose that improves transmission capacity, reduces the IC bond number that transmits data length and error rate and minimizing representative data, described encoder can be encoded into 2 integer power kind status data of input and can be the parallel output signal that distant place decoder can be read, and the serial data that decoder can transmit the own coding device is differentiated and send parallel output signal.Encoding/decoding device of the present invention can be applicable to the design of integrated circuit and makes.

Fig. 1 is a coding circuit of the present invention;

Fig. 2 is among the coding embodiment of encoder of the present invention under two condition, the sequential chart that each is relevant;

Fig. 3 is among the coding embodiment of encoder of the present invention under four attitudes, the sequential chart that each is relevant;

Fig. 4 is the preferred embodiment of the quadraflop figure of address array loader shown in Figure 1;

Fig. 5 is for respectively importing the sequential chart of each row signal of pin among Fig. 4 embodiment;

Fig. 6 is among Fig. 4 embodiment, the input pin connect VSS, VDD, do not connect, and S-IN signal timing diagram during column signal S;

Fig. 7 is the preferred embodiment of eight attitude circuit diagrams of address array loader shown in Figure 1;

Fig. 8 is presented at respectively to import pin among Fig. 7 embodiment and connecting VSS, VDD, and S-IN signal timing diagram when column signal S1, S2, S3, S4, S5;

Fig. 9 to Figure 12 illustrative data format of the present invention;

Figure 13 is a decoding circuit of the present invention.

As shown in Figure 1, it is the block diagram of encoder circuit of the present invention, below will elaborate to concerning between the function of each circuit among Fig. 1 and each circuit.

Oscillating circuit 11, TE controls by the enable signal end, and to produce required fundamental frequency in the code device, its fundamental frequency is sent to phase divider 12 by this oscillating circuit 11 output CL.

Phase divider 12, its fundamental frequency pulse signal that output CL of oscillating circuit 11 is sent give frequency division and handle, and are sent by signal QM, the QN of its output after with frequency division.Phase divider 12 can cooperate rank scanning device 14, synchronous circuit 15, and sends serial data by the output Dout of parallel tandem follower 16.For example in the coding embodiment of two condition, formed by 1 bit (0,1), its each relevant in preface as shown in Figure 2.Under the coded system of four attitudes, by two bits (00,10,01,11) represent " 0 ", " 1 ", " open (OPEN), " the 4th attitude (FOURTH STATE) ", its sequential chart as shown in Figure 3.

Can learn by Fig. 2 and two condition shown in Figure 3 and the digital coding of four attitudes,,, by that analogy, encode 2 as long as form with three bits as the data of eight attitudes of will encoding ⁿThe coding of attitude needs the composition of n bit.

Address array loader 13 is by detecting 2 ⁿThe circuit of the input pin of individual state is formed, so it has the parallel input pin of AO-AM, as shown in Figure 1.For example, with regard to the embodiment circuit of four and eight states inputs pin, the quadraflop figure of its address array loader as shown in Figure 4, and its eight attitudes circuit diagram is as shown in Figure 7.The for example parallel input of 16 pins when the input pin of scan A O-A15, is to be selected by the capable signal of X1-X4.The sequential chart of respectively importing pin and each row signal among Fig. 4 embodiment as shown in Figure 5, wherein the signal of four attitudes (VDD as shown in FIG., VSS, OPEN, column signal S) to switching switch (4 TO, 1 a switch) switch path, is respectively imported pin and can deliver to via four shown in the dotted line.

In Fig. 4, as the signal of importing pin is during for " opening ", " 0 ", " 1 " of its data bit (Data bit) is that the signal by row signal XO decides, enter and walk in the tandem follower 16 by signal input part S-IN again, and input pin signal is not when being " opening ", and promptly the signal level by its input pin decides the S-IN signal.When for example meeting VSS, in the L of the capable signal of XO (low level) and any variation of H high level, S-IN is " low ".When meeting VDD, as long as among capable signal L of XO or H a variation is arranged, then S-IN is " height ".When meeting column signal S, as long as when the L of the capable signal of XO and H have one to change, S-IN is the anti-phase of XO signal, the input pin connect VSS, VDD, do not connect, and S-IN signal timing diagram during column signal S shown in figure six.

Eight attitude circuit diagrams of address array loader as shown in Figure 7 among Fig. 1.For example, with regard to the embodiment of 16 pins input, the signal of its eight attitude (i.e. VDD shown in the figure, VSS, S1, S2, S3, S4, S5, OPEN), can be delivered to and respectively import pin to switching switch (8 TO, 1 a switch) switch path via eight shown in the dotted line.When scanning input pin AO-A15, be to select by the capable signal of X4-X7, its sequential action is identical with four attitudes, with reference to shown in Figure 5.And the S-IN signal is made up of the XO-X3 signal, its sequential chart as shown in Figure 8, by Fig. 4 and shown in Figure 7, the mode of circuit can organize into groups 16,32 according to this ... 2 ⁿThe encoder of the state of kind.

Sequential chart shown in Figure 8 promptly is to be presented at respectively to import pin among Fig. 7 embodiment and connecting VSS, VDD, and S-I signal timing diagram when column signal S1, S2, S3, S4, S5.

Rank scanning device 14 is QM signals of being sent by phase divider 12 and produce row and the column signal XO-Xn that wants scan address array loader 13.At synchronous circuit 15, when and walk to serial follower 16 and sending (before the input of the AO～A15) data, this synchronous circuit 15 can be in the beginning of this serial data, connect a QM signal partly (output signal of phase divider) earlier, as bits of original (start bit), as shown in figure 10, one section blank time (1 bit or 2 bits) after these data is as synchronous usefulness.And this bits of original and a serial data add and the blank time are called a frame (Frame), as shown in Figure 9.

So when transmitting data, the beginning of each frame all has individual bits of original (start bit) shown in (+) among the figure, be encoder with first high level benchmark position of QM as the initial bit of decoder, and decoder is as the beginning that detects whole serial data in order to bits of original, so after detecting bits of original, whole serial data can move an OM, be signal " height " partly, and this serial data bit is when being " 0 ", its L: H is 1: 1, and bit is when being " 1 ", and its L: H is 1: 2, as Fig. 2 and Fig. 3 institute also.The serial data of being made up of bits of original and bit " 00 " or bit " 11 " is shown in (+) among the figure.

And to walk to serial follower 16 be that QM, QN signal with phase divider 12 is with the parallel input pin AO-Am of address array loader 13, with 2 ⁿKind of state encoding, eight kinds of state encodings for example, as shown in Figure 8.By three data bit 000-111,0 or 1 waveform of each data bit as shown in Figure 2.Add synchronous circuit 15, this parallel data is changed into serial data output.

Figure 13 is the circuit of decoder of the present invention.Wherein oscillating circuit 21, and in order to produce the required fundamental frequency of decoding circuit, the frequency signal that is produced will offer the use of frequency divider 22, data string detection synchronizing signal 25 and counter decode circuit 26.Frequency divider 22 is with the fundamental frequency frequency required with the column scan device that be divided into lines.

The address array input circuit 13 of address array loader 23 and row and the circuit function of column scan device 24 and aforementioned coding circuit, capable identical with column scan device 14 is so refuse repeated description.

Data string detection synchronizing signal 25, the data of coming through medium transmission by data input pin pin received code device, and detect the bits of original (as shown in figure 10) of these data, whole serial data is made Synchronous Processing, each rising edge place at serial data, get a pulse (as Figure 12), the serial data shown in the figure is 001.The signal that this data string detection synchronizing signal 25 is exported will be sent to counter decode circuit 26, cooperate frequency signal that oscillating circuit 21 sends here again and as the counting benchmark of counter.

Counter decode circuit 26 inside have a counter, at the rising edge that detects the pulse that the serial data synchronizing signal sent here, be about to counter reset, this action schedule shows the beginning of a bit of serial data, this counter is counted again, as the time of two clock signals of Fig. 2 or Fig. 3, data string detection is 0 or 1 to be the output of bit then, as shown in figure 11.

2 ⁿ Attitude data generator 27, its with address array loader 23 import 2 ⁿKind of status data is represented with N bit, and the data of decoding out with counter decode circuit 26 are made comparisons in comparison circuit 28 again, promptly finish signal VT by decoding as if compare OK and export.

Aforesaid encoder and decoder have constituted code device of the present invention, and it reaches the purpose that improves transmission capacity, reduces the pin count that transmits data length and error rate and minimizing representative data integrated circuit with a positive integer power status number of 2.Its encoder can be encoded into 2 integer power data of input the serial output signal that can be read by distant place decoder, and decoder can future the data of own coding device differentiated and produced the serial output signal.Coding and decoding device of the present invention can be applicable to the design of integrated circuit and makes, and has splendid characteristic.

Claims

1. A codec device comprising an encoder and a decoder, wherein the encoder includes:

- Oscillating circuit to generate the basic frequency required by the encoder;

-Phase divider, the basic frequency pulse signal sent by the output terminal of the oscillation circuit is used for phase frequency division processing, and the signal (QM, QN) after frequency division is sent out by its output terminal;

- The address array input device is made up of circuits of 2 ⁿ state parallel input pins to be detected;

- row and column scanner, the signal (QM) sent by the phase divider generates the row and column signals to scan the address array input device;

— Synchronization circuit, when the parallel to serial output device sends a string of input data, the synchronization circuit will add a phase divider signal (QM) to the last bit of the data string, plus a blank 1 or 2 bit time, used for synchronization;

-Parallel to serial output device, the parallel input pin of the address array input device is encoded in 2 ⁿ states by the signal (QM, QN) of the phase divider, and the synchronization signal of the synchronous circuit is added to parallelize this The data is converted into serial data output;

And the decoder includes:

- Oscillating circuit for generating the frequency required by the decoder;

— a frequency divider, which divides the basic frequency into the frequencies required by the row and column scanners;

- address array input device, in order to detect the parallel signal of 2 ⁿ state parallel input pins;

—Row and column scanner, used for scanning the row and column signals of the address array input device;

—Detect data string synchronization signal, receive the data transmitted by the encoder at the data input end and detect the initial bit of the data, and perform synchronous processing on the entire string of data;

—The counter decoding circuit has a counter inside, and resets the counter by detecting the rising edge of the pulse sent by the synchronous signal of the data string, and the last positive output of the counter is the output of the bit;

- comparison circuit;

-2 ⁿ -state data generators, which represent 2 ⁿ kinds of state data input by the address array input device with N bits, and then compare them with the data decoded by the counter decoding circuit in the comparison circuit, and the comparison is correct. The decoded signal is output from its signal output terminal.