CN109669620B - Memory management method, memory control circuit unit and memory storage device - Google Patents
Memory management method, memory control circuit unit and memory storage device Download PDFInfo
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- CN109669620B CN109669620B CN201710950619.2A CN201710950619A CN109669620B CN 109669620 B CN109669620 B CN 109669620B CN 201710950619 A CN201710950619 A CN 201710950619A CN 109669620 B CN109669620 B CN 109669620B
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- 238000007726 management method Methods 0.000 title claims abstract description 123
- 230000005055 memory storage Effects 0.000 title claims abstract description 56
- 239000002356 single layer Substances 0.000 claims abstract description 54
- 239000010410 layer Substances 0.000 claims abstract description 39
- 239000002365 multiple layer Substances 0.000 claims 14
- 238000000034 method Methods 0.000 abstract description 6
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- 238000013507 mapping Methods 0.000 description 11
- 230000005540 biological transmission Effects 0.000 description 9
- 239000000284 extract Substances 0.000 description 4
- 238000012545 processing Methods 0.000 description 4
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- 238000005516 engineering process Methods 0.000 description 3
- 238000012546 transfer Methods 0.000 description 3
- 238000012935 Averaging Methods 0.000 description 2
- 239000007787 solid Substances 0.000 description 2
- 108010001267 Protein Subunits Proteins 0.000 description 1
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/0614—Improving the reliability of storage systems
- G06F3/0616—Improving the reliability of storage systems in relation to life time, e.g. increasing Mean Time Between Failures [MTBF]
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0629—Configuration or reconfiguration of storage systems
- G06F3/0631—Configuration or reconfiguration of storage systems by allocating resources to storage systems
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0646—Horizontal data movement in storage systems, i.e. moving data in between storage devices or systems
- G06F3/0652—Erasing, e.g. deleting, data cleaning, moving of data to a wastebasket
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
- G06F3/0671—In-line storage system
- G06F3/0673—Single storage device
- G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
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Abstract
一种存储器管理方法、存储器控制电路单元及存储器储存装置。此方法包括对其中一个实体抹除单元执行单层抹除操作对另一实体抹除单元执行复数层抹除操作；对此其中一个实体抹除单元与此另一实体抹除单元执行平均损耗操作，其中此另一个实体抹除单元较此其中一个实体抹除单元优先执行平均损耗操作。
A memory management method, a memory control circuit unit and a memory storage device. The method includes performing a single-layer erase operation on one of the physical erase units and performing a plurality of layers of erase operations on the other physical erase unit; performing an average wear operation on the one physical erase unit and the other physical erase unit , wherein the other physical erasing unit performs the wear leveling operation preferentially over the one physical erasing unit.
Description
Technical Field
The present invention relates to a memory management method, and more particularly, to a memory management method for a rewritable nonvolatile memory module, a memory control circuit unit and a memory storage device.
Background
Digital cameras, mobile phones and MP3 players have grown rapidly over the years, resulting in a rapid increase in consumer demand for storage media. Since the rewritable non-volatile memory module (e.g., flash memory) has the characteristics of non-volatility, power saving, small volume, and no mechanical structure, it is very suitable for being built in various portable multimedia devices as described above.
Generally, to increase the lifetime of the rewritable nonvolatile memory, the physically erased cells in the rewritable nonvolatile memory are used as evenly as possible. For example, the physical erase units of the rewritable nonvolatile memory are divided into a data area and an idle area, and the conventional wear leveling (wear leveling) method is to swap the physical erase units in the data area and the physical erase units in the idle area after each time the rewritable nonvolatile memory is executed for a fixed time or at a specific time point, so that the physical erase units with less erase times in the data area can be swapped to the idle area for programming (or writing).
When the physical erase cells with less erase counts in the data area are swapped to the idle area, the physical erase cells with higher erase counts are usually selected from the idle area to be swapped to the data area, however, in the memory storage device in which the physical erase cells write data in a plurality of programming manners (e.g., Single layer memory Cell (SLC) programming mode, multiple Level Cell (TLC) programming mode), the wear of the physical erase cells with high erase counts is not necessarily higher. For example, the wear of one time TLC programming on the physical erase cell is larger than that of one time SLC programming on the physical erase cell. Therefore, how to effectively measure the wear level of the physically erased cells to perform the average wear operation is the objective of those skilled in the art.
Disclosure of Invention
The invention provides a memory management method, a memory control circuit unit and a memory storage device, which can effectively execute average wear operation and prolong the service life of the memory storage device.
An exemplary embodiment of the present invention provides a memory management method for a rewritable nonvolatile memory module, wherein the rewritable nonvolatile memory module has a plurality of physical erase units. The method comprises performing N single-layer erasing operations on one of the physically erased cells; performing a plurality of layer erasing operations on another entity erasing unit for N times; and performing wear leveling operation on the one physically erased cell and the other physically erased cell, wherein the other physically erased cell performs wear leveling operation preferentially over the one physically erased cell.
In an exemplary embodiment of the present invention, the memory management method includes recording a wear value for each physically erased cell; updating the wear level of the physical erase unit according to the type of the erase operation performed on the plurality of physical erase units; and performing an average wear-leveling operation according to the wear-leveling values of the erase units, wherein when a single-layer erase operation is performed on the first erase unit, the wear-leveling value corresponding to the first erase unit is updated according to a first parameter value corresponding to the single-layer erase operation, and when a plurality-layer erase operation is performed on the first erase unit, the wear-leveling value corresponding to the first erase unit is updated according to a second parameter value corresponding to the plurality-layer erase operation, and the second parameter value is greater than the first parameter value.
In an exemplary embodiment of the invention, the memory management method further includes creating a wear table, and recording a wear value of the physically erased cells in the wear table.
In an exemplary embodiment of the invention, the memory management method further includes recording a single-layer erase count for each physically erased cell; and recording a plurality of layer erasing times for each entity erasing unit.
In an exemplary embodiment of the present invention, the step of updating the wear level of the physically erased cells according to the type of erase operation performed on the physically erased cells comprises: calculating wear values of the plurality of physical erase units according to the single-layer erase counts and the plurality of-layer erase counts of the plurality of physical erase units, wherein the wear value of a first physical erase unit is obtained by summing a first sub-wear value and a second sub-wear value, the first sub-wear value is obtained by multiplying the single-layer erase counts of the first physical erase unit by a first parameter value, and the second sub-wear value is obtained by multiplying the plurality of-layer erase counts of the first physical erase unit by a second parameter value.
In an exemplary embodiment of the invention, the memory management method further includes dynamically adjusting a ratio of the second parameter value to the first parameter value according to the erase count of the physically erased cell.
In an exemplary embodiment of the invention, the memory management method further includes grouping the physically erased cells into at least a data area and an idle area.
In an exemplary embodiment of the present invention, the step of performing the average wear operation according to the wear value of the physically erased cells comprises: selecting a second entity erasing unit from the entity erasing units in the data area, selecting a third entity erasing unit from the entity erasing units in the idle area, copying the data in the second entity erasing unit into the third entity erasing unit, associating the third entity erasing unit to the data area, and associating the second entity erasing unit to the idle area, wherein the loss value of the second entity erasing unit is less than the loss values of other entity erasing units in the data area, and the loss value of the third entity erasing unit is greater than the loss values of other entity erasing units in the idle area.
An exemplary embodiment of the present invention provides a memory management method for a rewritable nonvolatile memory module, wherein the rewritable nonvolatile memory module has a plurality of physical erase units. The memory management method includes recording a wear value for each physically erased cell. The memory management method further includes performing an erase operation on the first physically erased cell, updating a wear level corresponding to the first physically erased cell using a first parameter value when the first physically erased cell stores a single bit, and updating a wear level corresponding to the first physically erased cell using a second parameter value when the first physically erased cell stores a plurality of bits.
In an exemplary embodiment of the invention, the step of updating the wear-out value corresponding to the first physically erased cell using a first parameter value when the first physically erased cell stores a single bit and using a second parameter value when the first physically erased cell stores a plurality of bits comprises: updating a single-layer erasing frequency corresponding to the first entity erasing unit when the first entity erasing unit stores a single bit after the erasing operation is carried out on the first entity unit; updating the plurality of layers of erasing times corresponding to the first entity erasing unit when the first entity erasing unit stores a plurality of bits after the erasing operation is carried out on the first entity unit; and calculating a wear value of the first physical erase unit according to the single-layer erase count and the plurality of layer erase counts of the first physical erase unit, wherein the wear value of the first physical erase unit is obtained by summing a first sub-wear value and a second sub-wear value, the first sub-wear value is obtained by multiplying the single-layer erase count of the first physical erase unit by a first parameter value, and the second sub-wear value is obtained by multiplying the plurality of layer erase counts of the first physical erase unit by a second parameter value.
An exemplary embodiment of the present invention provides a memory control circuit unit for controlling a rewritable nonvolatile memory module, wherein the rewritable nonvolatile memory module has a plurality of physical erase units. The memory control circuit unit comprises a host interface, a memory interface and a memory management circuit. The host interface is used for electrically connecting to a host system. The memory interface is electrically connected to the rewritable nonvolatile memory module. The memory management circuit is electrically connected to the host interface and the memory interface. The memory management circuit performs a single layer erase operation for one of the plurality of erase operations for N times, performs a plurality of layer erase operations for another of the plurality of erase operations for N times, and performs a wear leveling operation for the one of the plurality of erase operations and the another one of the plurality of erase operations, wherein the another one of the plurality of erase operations performs a wear leveling operation prior to the one of the plurality of erase operations.
In an exemplary embodiment of the invention, the memory management circuit is configured to record a wear value for each physically erased cell. The memory management circuit is further configured to update the wear value of the physical erase unit according to a type of an erase operation performed on the physical erase unit, wherein when a single-layer erase operation is performed on the first physical erase unit, the wear value corresponding to the first physical erase unit is updated according to a first parameter value corresponding to the single-layer erase operation, and when a plurality of layers of erase operations are performed on the first physical erase unit, the wear value corresponding to the first physical erase unit is updated according to a second parameter value corresponding to the plurality of layers of erase operations, and the second parameter value is greater than the first parameter value. Furthermore, the memory management circuit is further configured to perform an average wear operation according to the wear value of the physically erased cells.
In an exemplary embodiment of the invention, the memory management circuit is further configured to establish a wear table, and record a wear value of the physically erased cell in the wear table.
In an exemplary embodiment of the invention, the memory management circuit is further configured to record a single layer of erase count for each physically erased cell, and record a plurality of layer of erase counts for each physically erased cell.
In an exemplary embodiment of the present invention, in the operation of updating the wear value of the physical erase unit according to the type of erase operation performed on the physical erase unit, the memory management circuit calculates the wear value of the physical erase unit according to a single-layer erase count and a plurality of-layer erase count of the physical erase unit, wherein the wear value of the first physical erase unit is obtained by summing a first sub-wear value and a second sub-wear value, the first sub-wear value is obtained by multiplying the single-layer erase count of the first physical erase unit by a first parameter value, and the second sub-wear value is obtained by multiplying the plurality of-layer erase count of the first physical erase unit by a second parameter value.
In an exemplary embodiment of the invention, the memory management circuit is further configured to dynamically adjust a ratio of the second parameter value to the first parameter value according to the erase count of the physically erased cell.
In an exemplary embodiment of the invention, the memory management circuit is further configured to group the physically erased cells into at least a data area and an idle area.
In an exemplary embodiment of the invention, in the operation of performing the wear leveling operation according to the wear values of the physical erase units, the memory management circuit selects a second physical erase unit from the physical erase units in the data area, selects a third physical erase unit from the physical erase units in the data area, copies the data in the second physical erase unit into the third physical erase unit, associates the third physical erase unit with the data area, and associates the second physical erase unit with the idle area, wherein the wear value of the second physical erase unit is less than the wear values of the other physical erase units in the data area and the wear value of the third physical erase unit is greater than the wear values of the other physical erase units in the idle area.
An exemplary embodiment of the present invention provides a memory storage device, which includes a connection interface unit, a rewritable nonvolatile memory module, and a memory control circuit unit. The connection interface unit is used for electrically connecting to a host system. The rewritable nonvolatile memory module comprises a plurality of entity erasing units. The memory control circuit unit is electrically connected to the connection interface unit and the rewritable nonvolatile memory module. The memory control circuit unit executes a single-layer erasing operation for N times on one entity erasing unit, executes a plurality of-layer erasing operations for N times on the other entity erasing unit, and executes a wear leveling operation on the one entity erasing unit and the other entity erasing unit, wherein the other entity erasing unit executes the wear leveling operation preferentially than the one entity erasing unit.
In an exemplary embodiment of the invention, the memory control circuit unit is further configured to record a wear value for each of the physically erased cells. The memory control circuit unit is further configured to update the wear level of the physical erase unit according to a type of an erase operation performed on the physical erase unit, wherein when a single-layer erase operation is performed on the first physical erase unit, the wear level corresponding to the first physical erase unit is updated according to a first parameter value corresponding to the single-layer erase operation, and when a plurality of-layer erase operations are performed on the first physical erase unit, the wear level corresponding to the first physical erase unit is updated according to a second parameter value corresponding to the plurality of-layer erase operations, and the second parameter value is greater than the first parameter value. Furthermore, the memory control circuit unit is further configured to perform an average wear operation according to the wear value of the physically erased cell.
In an exemplary embodiment of the invention, the memory control circuit unit is further configured to establish a wear table, and record a wear value of the physically erased unit in the wear table.
In an exemplary embodiment of the invention, the memory control circuit unit is further configured to record a single layer of erase count for each of the physically erased cells, and record a plurality of layer of erase counts for each of the physically erased cells.
In an exemplary embodiment of the invention, in the operation of updating the wear value of the physical erase unit according to the type of erase operation performed on the physical erase unit, the memory control circuit unit calculates the wear value of the physical erase unit according to a single-layer erase count and a plurality of-layer erase count of the physical erase unit, wherein the wear value of the first physical erase unit is obtained by summing a first sub-wear value and a second sub-wear value, the first sub-wear value is obtained by multiplying the single-layer erase count of the first physical erase unit by a first parameter value, and the second sub-wear value is obtained by multiplying the plurality of-layer erase count of the first physical erase unit by a second parameter value.
In an exemplary embodiment of the invention, the memory control circuit unit is further configured to dynamically adjust a ratio of the second parameter value to the first parameter value according to the erase count of the physically erased cell.
In an exemplary embodiment of the invention, the memory control circuit unit is further configured to group the physically erased cells into at least a data area and an idle area.
In an exemplary embodiment of the invention, in the operation of performing the wear leveling operation according to the wear values of the physical erase units, the memory control circuit unit selects a second physical erase unit from the physical erase units in the data area, selects a third physical erase unit from the physical erase units in the data area, copies the data in the second physical erase unit into the third physical erase unit, associates the third physical erase unit with the data area, and associates the second physical erase unit with the idle area, wherein the wear value of the second physical erase unit is smaller than the wear values of the other physical erase units in the data area and the wear value of the third physical erase unit is larger than the wear values of the other physical erase units in the idle area.
Based on the above, the memory management method, the memory control circuit unit and the memory storage device according to the exemplary embodiment can estimate the wear-out value of the physically erased cells according to the wear-out of the memory cells in different programming modes, and perform the wear-leveling operation according to the estimated wear-out value, thereby averaging the usage of each physically erased cell and effectively improving the lifetime of the memory storage device.
In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below.
Drawings
FIG. 1 is a diagram illustrating a host system, a memory storage device, and an input/output (I/O) device according to an example embodiment.
FIG. 2 is a diagram illustrating a host system, a memory storage device, and an input/output (I/O) device according to another example embodiment.
FIG. 3 is a diagram illustrating a host system and a memory storage device according to another example embodiment.
FIG. 4 is a schematic block diagram of a host system and a memory storage device according to an example embodiment.
FIG. 5 is a schematic block diagram of a memory control circuit unit according to an example embodiment.
FIGS. 6 and 7 are schematic diagrams of exemplary managing physical erase units according to an exemplary embodiment.
FIG. 8 is a diagram illustrating an erasure count table according to an exemplary embodiment.
FIG. 9 is a diagram of a loss table according to an example embodiment.
FIG. 10 is a flowchart illustrating a memory management method according to an example embodiment.
FIG. 11 is a flowchart illustrating an operation for performing an average loss operation, according to an example embodiment.
Description of the symbols
10: a memory storage device;
11: a host system;
12: input/output (I/O) devices;
110: a system bus;
111: a processor;
112: random Access Memory (RAM);
113: read Only Memory (ROM);
114: a data transmission interface;
20: a main board;
201: a carry-on disk;
202: a memory card;
203: a solid state disk;
204: a wireless memory storage device;
205: a global positioning system module;
206: a network interface card;
207: a wireless transmission device;
208: a keyboard;
209: a screen;
210: a horn;
30: a memory storage device;
31: a host system;
32: an SD card;
33: a CF card;
34: an embedded storage device;
341: an embedded multimedia card;
342: an embedded multi-chip package storage device;
402: a connection interface unit;
404: a memory control circuit unit;
406: a rewritable non-volatile memory module;
410(0) to 410 (N): a physical erase unit;
502: a memory management circuit;
504: a host interface;
506: a memory interface;
508: a buffer memory;
510: a power management circuit;
512: an error checking and correcting circuit;
602: a data area;
604: an idle area;
606: a system area;
608: a substitution region;
LBA (0) to LBA (h): a logic unit;
LZ (0) to LZ (M): a logical area;
800: erasing the order table;
900: a loss meter;
s1001: separately recording the wear values for the physical erase units;
s1003: updating the wear level of the physical erase unit according to the type of erase operation performed on the physical erase unit;
s1005: performing an average wear operation according to the wear value of the physically erased cells;
s1101: continuously judging whether to start the average loss operation;
s1103: selecting a physical erase unit (hereinafter referred to as a second physical erase unit) having the lowest wear level from the data area according to the wear table;
s1105: selecting a physical erase unit (hereinafter referred to as a third physical erase unit) having the highest wear-out value from the idle area according to the wear-out table;
s1107: copying the valid data on the second entity erasing unit to a third entity erasing unit, associating the second entity erasing unit to the idle area, and associating the third entity erasing unit to the data area.
Detailed Description
Generally, a memory storage device (also referred to as a memory storage system) includes a rewritable nonvolatile memory module and a controller (also referred to as a control circuit unit). Memory storage devices are typically used with a host system so that the host system can write data to or read data from the memory storage device.
Fig. 1 is a schematic diagram of a host system, a memory storage device, and an input/output (I/O) device according to an example embodiment, and fig. 2 is a schematic diagram of a host system, a memory storage device, and an input/output (I/O) device according to another example embodiment.
Referring to fig. 1 and 2, the host system 11 generally includes a processor 111, a Random Access Memory (RAM) 112, a Read Only Memory (ROM) 113, and a data transmission interface 114. The processor 111, the RAM 112, the ROM 113, and the data transmission interface 114 are all electrically connected to the system bus (system bus) 110.
In the present exemplary embodiment, the host system 11 is electrically connected to the memory storage device 10 through the data transmission interface 114. For example, host system 11 may write data to memory storage device 10 or read data from memory storage device 10 via data transfer interface 114. In addition, the host system 11 is electrically connected to the I/O device 12 via a system bus 110. For example, the host system 11 may transmit output signals to the I/O device 12 or receive input signals from the I/O device 12 via the system bus 110.
In the present exemplary embodiment, the processor 111, the random access memory 112, the read only memory 113 and the data transmission interface 114 are disposed on the motherboard 20 of the host system 11. The number of data transfer interfaces 114 may be one or more. The motherboard 20 can be electrically connected to the memory storage device 10 through the data transmission interface 114 in a wired or wireless manner. The memory storage device 10 can be, for example, a personal disk 201, a memory card 202, a Solid State Drive (SSD) 203, or a wireless memory storage device 204. The wireless memory Storage device 204 can be, for example, a Near Field Communication (NFC) memory Storage device, a wireless facsimile (WiFi) memory Storage device, a Bluetooth (Bluetooth) memory Storage device, or a low power Bluetooth memory Storage device (e.g., iBeacon) based on various wireless Communication technologies. In addition, the motherboard 20 may also be electrically connected to various I/O devices such as a Global Positioning System (GPS) module 205, a network interface card 206, a wireless transmission device 207, a keyboard 208, a screen 209, a speaker 210, and the like through the System bus 110. For example, in an exemplary embodiment, the motherboard 20 may access the wireless memory storage device 204 via the wireless transmission device 207.
In an exemplary embodiment, the host system referred to is substantially any system that can cooperate with a memory storage device to store data. Although the host system is described as a computer system in the above exemplary embodiment, fig. 3 is a schematic diagram of a host system and a memory storage device according to another exemplary embodiment. Referring to fig. 3, in another exemplary embodiment, the host system 31 may also be a digital camera, a video camera, a communication device, an audio player, a video player, or a tablet computer, and the memory storage device 30 may be various non-volatile memory storage devices such as an SD card 32, a CF card 33, or an embedded storage device 34. The embedded storage device 34 includes various types of embedded Multi-media cards (eMMC) 341 and/or embedded Multi-Chip Package storage devices (eMCP) 342 to electrically connect the memory module directly to the embedded storage device on the substrate of the host system.
FIG. 4 is a schematic block diagram of a host system and a memory storage device according to an example embodiment.
Referring to fig. 4, the memory storage device 10 includes a connection interface unit 402, a memory control circuit unit 404 and a rewritable nonvolatile memory module 406.
In the present exemplary embodiment, connection interface unit 402 is compatible with the Serial Advanced Technology Attachment (SATA) standard. However, it should be understood that the present invention is not limited thereto, and the connection interface unit 402 may also conform to the Parallel Advanced Technology Attachment (PATA) standard, the Institute of Electrical and Electronic Engineers (IEEE) 1394 standard, the High-Speed Peripheral Component connection interface (PCI Express) standard, the Universal Serial Bus (USB) standard, the Ultra High Speed-I (UHS-I) interface standard, the Ultra High Speed-II (UHS-II) interface standard, the Secure Digital (SD) interface standard, the Memory Stick (Memory Stick, MS) interface standard, the Multi-Chip Package (Multi-Package) interface standard, the Multimedia storage Card (Electronic, Multimedia Embedded) interface (MMC), eMMC) interface standard, Universal Flash Storage (UFS) interface standard, embedded Multi-Chip Package (eMCP) interface standard, Compact Flash (CF) interface standard, Integrated Device Electronics (IDE) standard, or other suitable standard. In the present exemplary embodiment, the connection interface unit 402 and the memory control circuit unit 404 may be packaged in one chip, or the connection interface unit 402 is disposed outside a chip including the memory control circuit unit.
The memory control circuit unit 404 is used for executing a plurality of logic gates or control commands implemented in a hardware type or a firmware type, and performing operations such as writing, reading and erasing data in the rewritable nonvolatile memory module 406 according to commands of the host system 11.
The rewritable nonvolatile memory module 406 is electrically connected to the memory control circuit unit 404 and is used for storing data written by the host system 11. The rewritable nonvolatile memory module 406 has physical erase units 410(0) -410 (N). For example, the physical erase units 410(0) -410 (N) may belong to the same memory die (die) or to different memory dies. Each of the plurality of physical erase units has a plurality of physical program units, wherein the physical program units belonging to the same physical erase unit can be independently written and simultaneously erased. However, it should be understood that the invention is not limited thereto, and each of the plurality of physically erased cells may be composed of 64 physically programmed cells, 256 physically programmed cells, or any other number of physically programmed cells.
In more detail, the physically erased cell is the minimum unit of erase. That is, each physically erased cell contains one of the minimum number of memory cells that are erased. The physical programming unit is a minimum unit for programming. That is, the physical programming unit is the minimum unit for writing data. Each physical programming cell typically includes a data bit region and a redundancy bit region. The data bit region includes a plurality of physical access addresses for storing user data, and the redundancy bit region is used for storing system data (e.g., control information and error correction codes). In the exemplary embodiment, each physical program unit includes 8 physical access addresses in the data bit region, and one physical access address has a size of 512 bytes (byte). However, in other exemplary embodiments, the data bit region may include a greater or lesser number of physical access addresses, and the size and number of the physical access addresses are not limited in the present invention. For example, in an exemplary embodiment, the physically erased cells are physical blocks, and the physically programmed cells are physical pages or physical sectors, but the invention is not limited thereto.
In the present exemplary embodiment, the rewritable nonvolatile memory module 406 is a multi-Level Cell (TLC) NAND flash memory module (i.e., a flash memory module capable of storing 3 data bits in one memory Cell). Specifically, the storage state of each memory cell of the rewritable nonvolatile memory module 406 can be identified as "111", "110", "101", "100", "011", "010", "001", or "000", wherein the 1 st bit from the left side is the LSB, the 2 nd bit from the left side is the CSB, and the 3 rd bit from the left side is the MSB. In addition, the memory cells arranged on the same word line may constitute 3 physical program units, wherein the physical program unit constituted by the LSBs of the memory cells is referred to as a lower physical program unit, the physical program unit constituted by the CSBs of the memory cells is referred to as a middle physical program unit, and the physical program unit constituted by the MSBs of the memory cells is referred to as an upper physical program unit. And a physical erase unit is composed of a plurality of physical program unit groups including a lower physical program unit, a middle physical program unit and an upper physical program unit which are composed of a plurality of memory cells arranged on the same word line.
However, the invention is not limited thereto, and the rewritable nonvolatile memory module 406 may also be a Multi-Level Cell (MLC) NAND-type flash memory module (i.e., a flash memory module capable of storing 2 data bits in one memory Cell), other flash memory modules, or other memory modules with the same characteristics.
FIG. 5 is a schematic block diagram of a memory control circuit unit according to an example embodiment.
Referring to FIG. 5, the memory control circuit unit 404 includes a memory management circuit 502, a host interface 504, a memory interface 506, a buffer memory 508, a power management circuit 510, and an error checking and correcting circuit 512.
The memory management circuit 502 is used to control the overall operation of the memory control circuit unit 404. Specifically, the memory management circuit 502 has a plurality of control commands, and the control commands are executed to perform data writing, reading, and erasing operations when the memory storage device 10 is in operation.
In the exemplary embodiment, the control instructions of the memory management circuit 502 are implemented in firmware. For example, the memory management circuit 502 has a microprocessor unit (not shown) and a read only memory (not shown), and the control instructions are burned into the read only memory. When the memory storage device 10 is in operation, the control instructions are executed by the microprocessor unit to perform operations such as writing, reading, and erasing data.
In another exemplary embodiment of the present invention, the control instructions of the memory management circuit 502 can also be stored in the form of program codes in a specific area of the rewritable non-volatile memory module 406 (e.g., a system area dedicated to storing system data in the memory module). Further, the memory management circuit 502 has a microprocessor unit (not shown), a read only memory (not shown), and a random access memory (not shown). In particular, the rom has a driver code, and when the memory control circuit unit 404 is enabled, the microprocessor unit first executes the driver code segment to load the control instruction stored in the rewritable nonvolatile memory module 406 into the ram of the memory management circuit 502. Then, the microprocessor unit operates the control commands to perform data writing, reading, erasing, and the like.
In addition, in another exemplary embodiment of the present invention, the control instructions of the memory management circuit 502 can also be implemented in a hardware type. For example, the memory management circuit 502 includes a microcontroller, a cell management circuit, a memory write circuit, a memory read circuit, a memory erase circuit, and a data processing circuit. The memory cell management circuit, the memory writing circuit, the memory reading circuit, the memory erasing circuit and the data processing circuit are electrically connected to the microcontroller. The memory cell management circuit is used for managing the entity erasing unit of the rewritable nonvolatile memory module 406; the memory writing circuit is used for issuing a writing instruction to the rewritable nonvolatile memory module 406 so as to write data into the rewritable nonvolatile memory module 406; the memory reading circuit is used for sending a reading instruction to the rewritable nonvolatile memory module 406 so as to read data from the rewritable nonvolatile memory module 406; the memory erasing circuit is used for issuing an erasing instruction to the rewritable nonvolatile memory module 406 so as to erase data from the rewritable nonvolatile memory module 406; the data processing circuit is used for processing data to be written into the rewritable nonvolatile memory module 406 and data read from the rewritable nonvolatile memory module 406.
The host interface 504 is electrically connected to the memory management circuit 502 and is electrically connected to the connection interface unit 402 for receiving and recognizing commands and data transmitted by the host system 11. That is, commands and data transmitted by the host system 11 are transmitted to the memory management circuit 502 through the host interface 504. In the exemplary embodiment, host interface 504 is compatible with the SATA standard. However, it should be understood that the present invention is not limited thereto, and the host interface 504 may be compatible with the PATA standard, the IEEE 1394 standard, the PCI Express standard, the USB standard, the UHS-I interface standard, the UHS-II interface standard, the SD standard, the MS standard, the MMC standard, the CF standard, the IDE standard, or other suitable data transfer standards.
The memory interface 506 is electrically connected to the memory management circuit 502 and is used for accessing the rewritable nonvolatile memory module 406. That is, the data to be written to the rewritable nonvolatile memory module 406 is converted into a format accepted by the rewritable nonvolatile memory module 406 through the memory interface 506.
The buffer memory 508 is electrically connected to the memory management circuit 502 and is used for temporarily storing data and instructions from the host system 11 or data from the rewritable nonvolatile memory module 406.
The power management circuit 510 is electrically connected to the memory management circuit 502 and is used for controlling the power of the memory storage device 10.
The error checking and correcting circuit 512 is electrically connected to the memory management circuit 502 and is used for performing an error checking and correcting process to ensure the correctness of data. Specifically, when the memory management circuit 502 receives a write command from the host system 11, the Error Checking and Correcting circuit 512 generates an Error Checking and Correcting Code (ECC Code) corresponding to the data corresponding to the write command, and the memory management circuit 502 writes the data corresponding to the write command and the corresponding ECC Code into the rewritable nonvolatile memory module 406. Thereafter, when the memory management circuit 502 reads data from the rewritable nonvolatile memory module 406, the corresponding error checking and correcting codes are simultaneously read, and the error checking and correcting circuit 512 performs an error checking and correcting process on the read data according to the error checking and correcting codes.
FIGS. 6 and 7 are schematic diagrams of exemplary managing physical erase units according to an exemplary embodiment.
It should be understood that, when describing the operation of the physically erased cells of the rewritable non-volatile memory module 406, it is a logical concept to operate the physically erased cells by the words "extract", "group", "partition", "associate", and the like. That is, the physical locations of the physical erase units of the rewritable nonvolatile memory module are not changed, but the physical erase units of the rewritable nonvolatile memory module are logically operated.
Operations performed by the memory management circuit 502, the host interface 504 and the memory interface 506, the buffer memory 508, the power management circuit 510 and the error checking and correcting circuit 512 are described below and may also be referred to as being performed by the memory control circuit unit 404.
Referring to FIG. 6, the memory management circuit 502 logically groups the physical erase units 410(0) -410 (N) into a data area 602, an idle area 604, a system area 606, and a replacement area 608.
The physically erased cells logically belonging to the data area 602 and the idle area 604 are used for storing data from the host system 11. Specifically, the wear-leveling cells in the data area 602 are regarded as the wear-leveling cells storing data, and the wear-leveling cells in the idle area 604 are used to replace the wear-leveling cells in the data area 602. That is, when receiving a write command and data to be written from the host system 11, the memory management circuit 502 extracts the physical erase unit from the idle region 604 and writes the data into the extracted physical erase unit to replace the physical erase unit of the data region 602.
The physically erased cells logically belonging to the system area 606 are used for recording system data. For example, the system data includes information about the manufacturer and model of the rewritable nonvolatile memory module, the number of physically erased cells of the rewritable nonvolatile memory module, the number of physically programmed cells per each physically erased cell, and the like.
The physically erased cells logically belonging to the replacement area 608 are used in the bad-physically-erased-cell replacement procedure to replace the damaged physically erased cells. Specifically, if there are normal physically erased cells in the replacement area 608 and the physically erased cells in the data area 602 are damaged, the memory management circuit 502 extracts the normal physically erased cells from the replacement area 608 to replace the damaged physically erased cells.
In particular, the number of physically erased cells in the data area 602, the idle area 604, the system area 606 and the replacement area 608 may vary according to different memory specifications. Moreover, it should be understood that during operation of the memory storage device 10, the grouping relationship of the physically erased cells associated with the data area 602, the idle area 604, the system area 606 and the replacement area 608 may dynamically change. For example, when the physically erased cells in the idle area 604 are damaged and replaced by the physically erased cells in the replacement area 608, the physically erased cells in the replacement area 608 are associated with the idle area 604.
Referring to fig. 7, the memory management circuit 502 configures the logic units LBA (0) -LBA (h) to map the physical erase units of the data area 602, where each logic unit has a plurality of logic sub-units to map the physical program units of the corresponding physical erase units. Moreover, when the host system 11 is going to write data into the logical units or update the data stored in the logical units, the memory management circuit 502 extracts a physical erase unit from the idle area 604 to write data, so as to replace the physical erase unit in the data area 602. In the present exemplary embodiment, the logical subunit may be a logical page or a logical sector.
In order to identify which physically erased cell the data of each logical cell is stored in, in the exemplary embodiment, the memory management circuit 502 records a mapping between the logical cells and the physically erased cells. Moreover, when the host system 11 intends to access data in the logical sub-unit, the memory management circuit 502 identifies the logical unit to which the logical sub-unit belongs, and accesses data in the physical erase unit mapped by the logical unit. For example, in the exemplary embodiment, the memory management circuit 502 stores a logical-to-physical mapping table in the rewritable nonvolatile memory module 406 to record the physical erase unit mapped by each logical unit, and the memory management circuit 502 loads the logical-to-physical mapping table into the buffer memory 508 to maintain when data is to be accessed.
It should be noted that, since the buffer 508 has a limited capacity and cannot store a mapping table for recording mapping relationships of all logic units, in the exemplary embodiment, the memory management circuit 502 groups the logic units LBA (0) -LBA (h) into a plurality of logic zones LZ (0) -LZ (m), and configures a logic-entity mapping table for each logic zone. In particular, when the memory management circuit 502 wants to update the mapping of a logical unit, the logical-to-physical mapping table corresponding to the logical area to which the logical unit belongs is loaded into the buffer memory 508 for updating.
In the present exemplary embodiment, the memory management circuit 502 programs the physically erased cells using the first mode or the second mode. For example, if the data to be written is the logical-to-physical mapping table, the memory management circuit 502 erases the physically erased cells using a single-level erase operation corresponding to the first programming mode and writes the logical-to-physical mapping table into the physically erased cells using the first programming mode. For example, if the data to be written is user data from host system 11, memory management circuit 502 uses a plurality of levels of erase operations corresponding to the second programming mode to erase the physically erased cells and uses the second programming mode to write the user data into the physically erased cells.
The first programming mode is a programming mode in which one memory cell stores one bit of data. For example, in the first programming mode, the memory management circuit 502 may program the memory cells of the physical erase unit in a single layer memory cell (SLC) mode, a lower physical programming (lower physical programming) mode, a hybrid programming (mixture programming) mode, or a less layer memory cell (SLC) mode. That is, in the first programming mode, the memory management circuit 502 only performs the data writing operation on the lower physical programming unit. Thus, in the present exemplary embodiment, only one-third of the capacity of a physically erased cell programmed in the first programming mode is used.
The second programming mode is a programming mode in which one memory cell stores a plurality of bits. For example, in the second programming mode, the memory management circuit 502 may program the physically erased cells in a multi-level cell (MLC) programming mode, a multiple level (TLC) cell programming mode, or the like. That is, when data is written using the second programming mode, the memory management circuit 502 performs programming on a physical programming cell group. It is worth mentioning that the life time of the physically erased cells operated in the second programming mode is shorter than that of the physically erased cells operated in the first programming mode. Specifically, the number of times each physically erased cell can be written or erased is limited, and when the number of times a physically erased cell is written exceeds a threshold, the physically erased cell may be damaged and cannot be written with data any more, wherein the wear of the physically erased cell operated in the second programming mode is higher, and the wear of the physically erased cell operated in the first programming mode is lower.
In the present exemplary embodiment, when there is no valid data stored in a physically erased cell (e.g., all stored data are marked as invalid data), the memory management circuit 502 may perform an erase operation on the physically erased cell to write data again. In the exemplary embodiment, the memory management circuit 502 records the corresponding erase counts for each of the physically erased cells 410(0) -410 (N). For example, when a physically erased cell in the rewritable nonvolatile memory module 406 is erased, the memory management circuit 502 will add 1 to the erase count corresponding to the physically erased cell. Herein, the erase count may be recorded in an erase count table or a physically erased unit corresponding thereto.
In addition to the erasure table, the memory management circuit 502 records a corresponding wear level for each of the physically erased cells 410(0) -410 (N). For example, in the exemplary embodiment, the wear level for each of the physically erased cells 410(0) -410 (N) is initially set to 0. When a physically erased cell is to be erased, memory management circuitry 502 updates the wear level of the physically erased cell based on the type of erase operation being performed. Specifically, when performing a single-layer erase operation on a physically-erased cell (hereinafter also referred to as a first physically-erased cell), the memory management circuit 502 adds the wear level of the first physically-erased cell to the first parameter value as a new wear level; when the first erase unit is subjected to a plurality of erase operations, the memory management circuit 502 adds the second parameter value to the wear level of the first erase unit to obtain a new wear level. Here, the second parameter value is larger than the first parameter value. For example, in the present exemplary embodiment, the first parameter value is 1, and the second parameter value is 10. In the exemplary embodiment, memory management circuitry 502 performs the wear leveling operation based on the wear values of each of the physically erased cells 410(0) -410 (N). That is, when performing the wear leveling operation, the wear leveling operation is performed on a physically erased cell that is subjected to the N-th multi-level erase operation prior to a physically erased cell that is subjected to the N-th single-level erase operation according to the wear leveling value.
FIG. 8 is a diagram illustrating an erasure count table according to an exemplary embodiment.
Referring to FIG. 8, the erase count table 800 includes a physical erase cell field, a single-layer erase count field, a plurality of layers of erase count fields, and an erase count field. During operation of the memory storage device 10, the memory management circuit 502 updates the erase count table 800 according to each erase operation to record the single-layer erase count, the plurality of-layer erase counts and the erase counts of each physically erased cell.
FIG. 9 is a diagram of a loss table according to an example embodiment.
Referring to fig. 9, the wear-out table 900 includes a physically erased cell field, a single-layer erase count field, a plurality of layers of erase count fields, and a wear-out value field. During operation of the memory storage device 10, the memory management circuit 502 updates the wear table 900 according to the erase operation column, the first parameter value and the second parameter value each time, so as to record the single-layer erase count, the plurality of-layer erase counts and the wear level of each physically erased cell. For example, the memory management circuit 502 multiplies the erase count of a physical erase unit by a first parameter to obtain a value (also referred to as a first sub-wear value), multiplies the erase count of a plurality of layers of the physical erase unit by a second parameter to obtain a value (also referred to as a second sub-wear value), and adds the first sub-wear value and the second sub-wear value to obtain a wear value corresponding to the physical erase unit.
Referring to fig. 8 and fig. 9, in the erasure count table 800, the physical erase unit 410(0) with the highest erasure count, and the physical erase unit 410(100) with the highest wear level in the wear table 900. Accordingly, the wear leveling operation is performed according to the wear values of the physical erase units 410(0) to 410(N), so that the use of the physical erase units 410(0) to 410(N) of the rewritable nonvolatile memory module 406 can be leveled.
It should be understood that although a single layer erase count and a plurality of layer erase counts are recorded in the erase count table 800, the present invention is not limited thereto, and in another exemplary embodiment, the memory management circuit 502 can directly calculate and update the erase counts of the physical erase units 410(0) -410 (N) according to the erase operation without recording the single layer erase count and the plurality of layer erase counts. Similarly, although the wear table 900 has a single layer erase count and a plurality of layer erase counts recorded therein, the invention is not limited thereto, and in another exemplary embodiment, the memory management circuit 502 can directly calculate and update the wear values of the physically erased cells 410(0) -410 (N) according to the type of erase operation, the first parameter value and the second parameter value without recording the single layer erase count and the plurality of layer erase counts.
FIG. 10 is a flowchart illustrating a memory management method according to an example embodiment.
Referring to FIG. 10, in step S1001, the memory management circuit 502 records a wear level for each of the physical erase units 410(0) to 410 (N). In step S1003, the memory management circuit 502 updates the wear level of the erase units 410(0) -410 (N) according to the type of erase operation performed on the erase units 410(0) -410 (N). The loss values of the physical erase units 410(0) -410 (N) are calculated and recorded as described above, and will not be described again.
In step S1005, the memory management circuit 502 performs an average wear operation based on the wear values of 410(0) to 410 (N).
FIG. 11 is a flowchart illustrating an operation for performing an average loss operation, according to an example embodiment.
Referring to fig. 11, in step S1101, the memory management circuit 502 continuously determines whether to initiate an average wear operation. For example, the memory management circuit 502 may initiate the wear leveling operation when the memory storage device 10 is operated for a predetermined time or the total erase count of physically erased cells of the rewritable nonvolatile memory module 406 is greater than a predetermined threshold.
If the wear leveling operation is started, in step S1103, the memory management circuit 502 selects a physical erase unit (hereinafter, referred to as a second physical erase unit) with the lowest wear level from the data area 602 according to the wear table 900. For example, referring to FIG. 9, assuming that the physical erase units 410(0) -410 (96) are associated with the data area 602 and the wear-level of the physical erase units 410(4) is the lowest, the memory management circuit 502 selects the physical erase units 410(4) from the data area 602.
In step S1105, the memory management circuit 502 selects a physical erase unit (hereinafter referred to as a third physical erase unit) with the highest wear level from the idle area 604 according to the wear table 900. For example, referring to FIG. 9, assuming that the physical erase units 410(97) -410 (100) are associated with the idle region 604 and the wear level of the physical erase units 410(100) is highest, the memory management circuit 502 selects the physical erase units 410(100) from the idle region 605.
In step S1107, the memory management circuit 502 copies the valid data in the second physical erase unit to the third physical erase unit, associates the second physical erase unit to the idle region 604, and associates the third physical erase unit to the data region. For example, in the logical-physical mapping table, the logical unit originally mapped to the physical erase unit 410(4) is updated to be mapped to the physical erase unit 410(100) so as to associate the physical erase unit 410(100) to the data area 602, and the physical erase unit 410(4) is added to the idle area queue table so as to associate the physical erase unit 410(4) to the idle area 604.
It should be noted that, in the present exemplary embodiment, the ratio of the first parameter value to the second parameter value is fixed, for example, as described above, the ratio of the first parameter value to the second parameter value is 1: 10. however, the invention is not limited thereto, and in another exemplary embodiment, the memory management circuit 502 can dynamically adjust the ratio of the first parameter value to the second parameter value according to the total erase count of the physically erased cells of the rewritable non-volatile memory module 406. For example, after the wear-leveling count of the physically-erased cells of the rewritable nonvolatile memory module 406 is greater than a wear-leveling threshold (e.g., 500), the ratio of the first parameter value to the second parameter value is adjusted to 1: 100. that is, the second parameter value is adjusted by 100. Accordingly, the wear of the physically erased cells 410(0) -410 (N) can be measured more precisely.
In summary, the memory management method, the memory control circuit unit and the memory storage device according to the exemplary embodiment estimate the wear-out value of the physical erase unit according to the wear-out of the memory cells in different programming modes, and perform the wear-leveling operation according to the estimated wear-out value, thereby averaging the usage of each physical erase unit and effectively prolonging the life of the memory storage device.
Although the present invention has been described with reference to the above embodiments, it should be understood that various changes and modifications can be made therein by those skilled in the art without departing from the spirit and scope of the invention.
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