CN109659312B - Array substrate and preparation method thereof - Google Patents
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- CN109659312B CN109659312B CN201811194117.2A CN201811194117A CN109659312B CN 109659312 B CN109659312 B CN 109659312B CN 201811194117 A CN201811194117 A CN 201811194117A CN 109659312 B CN109659312 B CN 109659312B
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- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
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Abstract
本申请提供一种阵列基板及其制备方法，所述方法包括以下步骤：在衬底基板上沉积第一金属层，并图案化形成栅极与第一金属图案；在所述栅极上依次形成栅极绝缘层、氧化物半导体层，并采用湿法蚀刻工艺在对应所述第一金属图案的相应位置对所述氧化物半导体层以及部分所述栅极绝缘层进行蚀刻，形成中间孔；采用干法蚀刻工艺对对应所述中间孔的所述栅极绝缘层的剩余部分进行蚀刻，形成栅极绝缘层过孔；在所述氧化物半导体层上形成第二金属层，图案化后形成薄膜晶体管与第二金属图案，所述第二金属图案通过所述栅极绝缘层过孔与所述第一金属图案接触。
The present application provides an array substrate and a method for preparing the same. The method includes the following steps: depositing a first metal layer on a base substrate, and patterning to form a gate and a first metal pattern; sequentially forming a gate on the gate a gate insulating layer and an oxide semiconductor layer, and a wet etching process is used to etch the oxide semiconductor layer and part of the gate insulating layer at corresponding positions corresponding to the first metal pattern to form intermediate holes; A dry etching process is used to etch the remaining part of the gate insulating layer corresponding to the intermediate hole to form a gate insulating layer via hole; a second metal layer is formed on the oxide semiconductor layer, and a thin film is formed after patterning The transistor and the second metal pattern are in contact with the first metal pattern through the gate insulating layer via hole.
Description
Technical Field
The application relates to the technical field of panel manufacturing, in particular to an array substrate and a preparation method thereof.
Background
In the active matrix driven LCD display technology, in order to improve the stability of the oxide TFT, a TFT with an Etching Stopper Layer (ESL) structure is widely used, which can effectively reduce the influence of external environmental factors and the etching damage of the source and drain electrodes on the back channel. However, the method of manufacturing arrays of ESL structures requires more mask times and significantly increases TFTSize and parasitic capacitance. The Back Channel Etching (BCE) structured TFT does not need an etching barrier layer, and the channel can be obviously reduced compared with an ESL structure, but the conventional BCE IGZO LCD Array flow needs 6 optical masks, namely a grid (M1), a grid insulating layer via hole (GI via), a semiconductor IGZO layer, a source drain (M2), a passivation layer via hole (PV via), a Pixel electrode (Pixel ITO) and the like, and the problems of more optical masks and higher production cost still exist.
Therefore, the prior art has defects and needs to be improved urgently.
Disclosure of Invention
The application provides an array substrate and a preparation method thereof, which can reduce the number of times of light covers in the preparation of the array substrate, simplify the process and save the cost.
In order to achieve the purpose, the technical scheme provided by the application is as follows:
the application provides a preparation method of an array substrate, which comprises the following steps:
step S10, depositing a first metal layer on the substrate base plate, and patterning to form a gate and a first metal pattern;
step S11, sequentially forming a gate insulating layer and an oxide semiconductor layer on the gate electrode, and etching the oxide semiconductor layer and a portion of the gate insulating layer at corresponding positions corresponding to the first metal pattern by using a wet etching process to form a middle hole;
step S12, etching the remaining portion of the gate insulating layer corresponding to the middle hole by using a dry etching process to form a gate insulating layer via hole;
step S13, forming a second metal layer on the oxide semiconductor layer, and forming a thin film transistor and a second metal pattern after patterning, wherein the second metal pattern is in contact with the first metal pattern through the gate insulating layer via hole.
In the preparation method of the array substrate of the present application, the gate insulating layer includes a first gate insulating layer and a second gate insulating layer stacked on the gate electrode, and the step S11 includes the following steps:
step S110, etching the oxide semiconductor layer and the second gate insulating layer by using a wet etching process to form a middle hole.
In the preparation method of the array substrate, the etching area of the oxide semiconductor layer is larger than that of the gate insulating layer at the position corresponding to the middle hole.
In the method for manufacturing an array substrate of the present application, the step S12 includes the following steps:
and step S120, etching the first gate insulating layer corresponding to the middle hole by adopting a dry etching process to form the gate insulating layer through hole.
In the method for manufacturing an array substrate of the present application, the step S13 includes the following steps:
step S130, performing a photomask process by using a halftone mask, and removing the second metal layer and the oxide semiconductor layer corresponding to a completely light-transmitting region of the halftone mask to form an oxide semiconductor pattern corresponding to the gate and the first metal pattern; and removing the second metal layer corresponding to the light-transmitting area of the half-tone mask plate part to form a source drain electrode of the thin film transistor and the second metal pattern corresponding to the first metal pattern.
In the preparation method of the array substrate, a part of the second metal pattern is in contact with the corresponding oxide semiconductor pattern, and the rest part of the second metal pattern is in contact with the first metal pattern through the gate insulating layer via hole.
In the method for manufacturing an array substrate of the present application, before the wet etching process is performed in step S11, the method further includes: a metal oxide layer is formed on the oxide semiconductor layer.
In the method for manufacturing an array substrate of the present application, in the step S11, the wet etching process includes the steps of: and etching the metal oxide layer, the oxide semiconductor layer and part of the gate insulating layer at corresponding positions corresponding to the first metal pattern by using a wet etching process to form the intermediate hole.
In the method for manufacturing an array substrate of the present application, the step S13 includes the steps of:
and forming a second metal layer on the metal oxide layer, forming a thin film transistor and a second metal pattern after patterning, wherein the second metal pattern is in contact with the first metal pattern through the gate insulating layer via hole.
In order to achieve the above object, the present application also provides an array substrate prepared by the above preparation method.
The beneficial effect of this application does: compared with the existing array substrate manufacturing process, the array substrate and the preparation method thereof provided by the application complete the array substrate manufacturing process by using 5 photomask processes, namely, the photomask processes of the grid electrode, the grid electrode insulating layer through hole, the source and drain electrode, the passivation layer through hole and the pixel electrode, so that the use times of the photomask are reduced. In the manufacturing process of the gate insulation layer via hole, the gate insulation layer via hole is obtained by using 1 time of wet etching and 1 time of dry etching, the preparation process is optimized, the interface of the gate insulation layer and the oxide semiconductor layer can be optimized, the direct low-impedance contact between the first metal pattern and the second metal pattern is ensured while the process is simplified, and therefore the good conductivity of the substrate is ensured.
Drawings
In order to illustrate the embodiments or the technical solutions in the prior art more clearly, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the application, and it is obvious for those skilled in the art that other drawings can be obtained according to these drawings without creative efforts.
Fig. 1 is a flowchart of a method for manufacturing an array substrate according to an embodiment of the present disclosure;
fig. 2A to 2H are schematic views illustrating a process of manufacturing an array substrate according to an embodiment of the present disclosure;
fig. 3 is a flowchart of a method for manufacturing an array substrate according to another embodiment of the present disclosure;
fig. 4A to 4F are schematic views illustrating a manufacturing process of an array substrate according to another embodiment of the present disclosure.
Detailed Description
The following description of the various embodiments refers to the accompanying drawings, which are included to illustrate specific embodiments that can be implemented by the application. Directional phrases used in this application, such as [ upper ], [ lower ], [ front ], [ rear ], [ left ], [ right ], [ inner ], [ outer ], [ side ], etc., refer only to the directions of the attached drawings. Accordingly, the directional terminology is used for purposes of illustration and understanding, and is in no way limiting. In the drawings, elements having similar structures are denoted by the same reference numerals.
The array substrate with the back channel etching structure aims at the technical problems that in the array substrate with the back channel etching structure in the prior art, the number of times of light covers is large and production cost is high in the preparation process, and the defect can be solved by the embodiment.
Fig. 1 is a flowchart of a method for manufacturing an array substrate according to an embodiment of the present disclosure. Fig. 2A to 2H are schematic diagrams illustrating a process of manufacturing an array substrate according to an embodiment of the present disclosure. The method comprises the following steps:
step S10, a first metal layer is deposited on the substrate base plate and patterned to form a gate and a first metal pattern.
Specifically referring to fig. 2A, a first metal layer 21 is deposited on the substrate 20, and the first metal layer 21 is patterned to form a gate 210 and a first metal pattern 211. The gate electrode 210 and the first metal pattern 211 are spaced apart.
Step S11, sequentially forming a gate insulating layer and an oxide semiconductor layer on the gate electrode, and etching the oxide semiconductor layer and a portion of the gate insulating layer at corresponding positions corresponding to the first metal pattern by using a wet etching process to form a middle hole.
As shown in fig. 2B, a gate insulating layer 22, an oxide semiconductor layer 23, and a first photoresist layer 24 are sequentially formed on the gate electrode 210. The gate insulating layer 22 includes a first gate insulating layer 220 and a second gate insulating layer 221 stacked on the gate 210; the material of the oxide semiconductor layer 23 may be Indium Gallium Zinc Oxide (IGZO).
In one embodiment, the first gate insulating layer 220 and the second gate insulating layer 221 are made of one of SiOx and SiNx, respectively. Of course, the material of the gate insulating layer 22 is not limited to the above two materials. In the above method, since the gate insulating layer 22 and the oxide semiconductor layer 23 can be deposited continuously, the number of interface contamination and defects can be reduced.
Wherein, the step S11 includes the following steps:
step S110, etching the oxide semiconductor layer and the second gate insulating layer by using a wet etching process to form a middle hole.
Referring to fig. 2C, after the photolithography process, an etching solution that can simultaneously etch the oxide semiconductor layer 23 and the second gate insulating layer 221 using a wet etching process using HF acid or the like is used to form the central hole 25 at a position corresponding to the first metal pattern 211.
In one embodiment, an etching area of the oxide semiconductor layer 23 is larger than an etching area of the second gate insulating layer 221 at a position corresponding to the central hole 25.
Step S12, etching the remaining portion of the gate insulating layer corresponding to the middle hole by using a dry etching process to form a gate insulating layer via hole.
In this embodiment, the step S12 includes the following steps:
and step S120, etching the first gate insulating layer corresponding to the middle hole by adopting a dry etching process to form the gate insulating layer through hole.
Referring to fig. 2D, the first gate insulating layer 220 is etched by a dry etching process, and a portion of the first gate insulating layer 220 corresponding to the intermediate hole 25 is removed, so as to form a gate insulating layer via hole 26 communicating with the first metal pattern 211. Then, the first photoresist 24 remaining on the surface of the oxide semiconductor layer 23 is removed.
Step S13, forming a second metal layer on the oxide semiconductor layer, and forming a thin film transistor and a second metal pattern after patterning, wherein the second metal pattern is in contact with the first metal pattern through the gate insulating layer via hole.
As shown in fig. 2E to 2F, a second metal layer 27 is formed on the oxide semiconductor layer 23, a second photoresist layer 28 is formed on the second metal layer 27, and a photomask process is performed using a halftone mask 29.
Specifically, the step S13 includes the steps of:
step S130, performing a photomask process by using a halftone mask, and removing the second metal layer and the oxide semiconductor layer corresponding to a completely light-transmitting region of the halftone mask to form an oxide semiconductor pattern corresponding to the gate and the first metal pattern; and removing the second metal layer corresponding to the light-transmitting area of the half-tone mask plate part to form a source drain electrode of the thin film transistor and the second metal pattern corresponding to the first metal pattern.
After the mask process is completed, the second metal layer 27 and the oxide semiconductor layer 23 corresponding to the complete light-transmitting region 291 of the half-tone mask 29 are etched to form an oxide semiconductor pattern 230; the second metal layer 27 corresponding to the partial light-transmitting region 292 of the halftone mask 29 is etched, and the second metal layer 27 and the oxide semiconductor layer 23 corresponding to the light-opaque region 290 of the halftone mask 29 are remained, so as to form a second metal pattern 270 and a source/drain electrode 271.
Wherein a portion of the second metal pattern 270 contacts the corresponding oxide semiconductor pattern 230, and another portion of the second metal pattern 270 contacts the first metal pattern 211 through the gate insulating layer via 26.
After the second metal layer 27 is deposited, since the oxide semiconductor layer 23 within the gate-insulating layer via hole 26 has been etched in advance during the formation of the gate-insulating layer via hole 26, direct low-resistance contact of the second metal pattern 270 with the first metal pattern 211 is ensured; while optimizing the interface of the gate insulating layer 22 and the oxide semiconductor layer 23.
As shown in fig. 2G to 2H, the method further includes the following steps: forming a passivation layer 30 on the source and drain electrodes 271 and patterning the passivation layer 30 to form a passivation layer through hole 301 corresponding to the source and drain electrodes 271; a patterned pixel electrode 31 is formed on the passivation layer 30, and the pixel electrode 31 is electrically connected to the source and drain electrodes 271 through the passivation layer via hole 301.
Fig. 3 is a flowchart of a method for manufacturing an array substrate according to another embodiment of the present disclosure. Fig. 4A to 4F are schematic diagrams illustrating a manufacturing process of an array substrate according to another embodiment of the present disclosure. The method comprises the following steps:
step S30, a first metal layer is deposited on the substrate base plate and patterned to form a gate and a first metal pattern.
The step S30 in this embodiment is the same as the step S10 in the above embodiment, and please refer to fig. 2A for details, which are not repeated here.
Step S31, sequentially forming a gate insulating layer, an oxide semiconductor layer, and a metal oxide layer on the gate electrode, and etching the metal oxide layer, the oxide semiconductor layer, and a portion of the gate insulating layer at corresponding positions corresponding to the first metal pattern by using a wet etching process to form a middle hole.
Specifically, referring to fig. 4A to 4B, a first metal layer 41 is disposed on the substrate 40, and the first metal layer 41 includes a patterned gate 410 and a first metal pattern 411. A gate insulating layer 42 is prepared on the first metal layer 41; an oxide semiconductor layer 43 is prepared on the gate insulating layer 42; a metal oxide layer 44 is prepared on the oxide semiconductor layer 43; a first photoresist layer 45 is prepared on the metal oxide layer 44.
In one embodiment, the gate insulating layer 42 includes, but is not limited to, a silicon nitride inorganic layer and a silicon oxide inorganic layer (not shown) stacked on each other. After the photolithography process, the etching solution for simultaneously etching the metal oxide layer 44, the oxide semiconductor layer 43 and the silicon oxide inorganic layer using HF acid or the like by a wet etching process, and the central hole 46 is formed at a position corresponding to the first metal pattern 411.
Step S32, etching the remaining portion of the gate insulating layer corresponding to the middle hole by using a dry etching process to form a gate insulating layer via hole.
Referring to fig. 4C, the remaining portion of the gate insulating layer 42 corresponding to the central hole 46 is etched by a dry etching process to form a gate insulating layer via hole 47. Then, the first photoresist layer 45 remaining on the surface of the metal oxide layer 44 is removed.
In one embodiment, the portion of the gate insulating layer 42 that is etched away using a dry etching process is a silicon nitride inorganic layer.
In one embodiment, the gate insulator via 47 has a stepped cross-sectional shape.
Step S33, forming a second metal layer on the metal oxide layer, and forming a thin film transistor and a second metal pattern after patterning, wherein the second metal pattern is in contact with the first metal pattern through the gate insulating layer via hole.
As shown in fig. 4D to 4E, a second metal layer 48 is formed on the metal oxide layer 44, a second photoresist layer 49 is formed on the second metal layer 48, and a photomask process is performed using a halftone mask 50.
Specifically, the step S33 includes the steps of:
step S330, performing a photomask process by using a halftone mask plate, removing the second metal layer, the metal oxide layer and the oxide semiconductor layer corresponding to a complete light transmission region of the halftone mask plate, and forming an oxide semiconductor pattern corresponding to the gate and the first metal pattern; and removing the second metal layer and the metal oxide layer corresponding to the light-transmitting area of the part of the halftone mask to form a source/drain electrode of the thin film transistor and the second metal pattern corresponding to the first metal pattern.
After the mask process is completed, the second metal layer 48, the metal oxide layer 44 and the oxide semiconductor layer 43 corresponding to the complete light-transmitting region 502 of the half-tone mask 50 are etched to form an oxide semiconductor pattern 430; the second metal layer 48 and the metal oxide layer 44 corresponding to the partial light-transmitting region 503 of the half-tone mask 50 are etched, and the second metal layer 48, the metal oxide layer 44 and the oxide semiconductor layer 43 corresponding to the light-transmitting region 501 of the half-tone mask 50 are remained, thereby forming a second metal pattern 480 and a source/drain 481. Wherein the second metal pattern 480 is in contact with the first metal pattern 411 through the gate insulating layer via 47.
As shown in connection with fig. 4F, the method further comprises the steps of: forming a passivation layer 51 on the source and drain 481 and patterning the passivation layer to form a passivation layer via 510 corresponding to the source and drain 481; a patterned pixel electrode 52 is formed on the passivation layer 51, and the pixel electrode 52 is electrically connected to the source and drain electrodes 481 through the passivation layer via 510.
The present application further provides an array substrate prepared by the above preparation method, where the structure of the array substrate is shown in fig. 2A to 2H or fig. 4A to 4F, and please refer to the description in the above embodiments, which is not repeated herein.
According to the array substrate and the preparation method thereof, 5 photomask processes are used, namely, the manufacturing process of the array substrate is completed through the photomask processes of the grid electrode, the grid insulation layer through hole, the source drain electrode, the passivation layer through hole and the pixel electrode, so that the using times of the photomask are reduced. In the manufacturing process of the gate insulation layer via hole, the gate insulation layer via hole is obtained by using 1 time of wet etching and 1 time of dry etching, the preparation process is optimized, the interface of the gate insulation layer and the oxide semiconductor layer can be optimized, the direct low-impedance contact between the first metal pattern and the second metal pattern is ensured while the process is simplified, and therefore the good conductivity of the substrate is ensured.
In summary, although the present application has been described with reference to the preferred embodiments, the above-described preferred embodiments are not intended to limit the present application, and those skilled in the art can make various changes and modifications without departing from the spirit and scope of the present application, so that the scope of the present application shall be determined by the appended claims.
Claims (8)
1. A preparation method of an array substrate is characterized by comprising the following steps:
step S10, depositing a first metal layer on the substrate base plate, and patterning to form a gate and a first metal pattern;
step S11, continuously forming a gate insulating layer and an oxide semiconductor layer on the gate electrode, where the gate insulating layer includes a first gate insulating layer and a second gate insulating layer stacked on the gate electrode, and etching the oxide semiconductor layer and the second gate insulating layer at corresponding positions corresponding to the first metal pattern by using a wet etching process to form a middle hole;
step S12, etching the first gate insulation layer corresponding to the middle hole by adopting a one-time dry etching process to form a gate insulation layer through hole;
step S13, forming a second metal layer on the oxide semiconductor layer, and forming a thin film transistor and a second metal pattern after patterning, wherein the second metal pattern is in contact with the first metal pattern through the gate insulating layer via hole.
2. The production method according to claim 1, wherein an etching area of the oxide semiconductor layer is larger than an etching area of the gate insulating layer at a position corresponding to the central hole.
3. The method as claimed in claim 1, wherein the step S13 includes the steps of:
step S130, performing a photomask process by using a halftone mask, and removing the second metal layer and the oxide semiconductor layer corresponding to a completely light-transmitting region of the halftone mask to form an oxide semiconductor pattern corresponding to the gate and the first metal pattern; and removing the second metal layer corresponding to the light-transmitting area of the half-tone mask plate part to form a source drain electrode of the thin film transistor and the second metal pattern corresponding to the first metal pattern.
4. The method according to claim 3, wherein a portion of the second metal pattern is in contact with the corresponding oxide semiconductor pattern, and a remaining portion of the second metal pattern is in contact with the first metal pattern through the gate insulating layer via.
5. The method for preparing a semiconductor device according to claim 1, wherein in the step S11, before the wet etching process is performed, the method further comprises the steps of: a metal oxide layer is formed on the oxide semiconductor layer.
6. The method for preparing a semiconductor device according to claim 5, wherein in the step S11, the wet etching process includes the steps of: and etching the metal oxide layer, the oxide semiconductor layer and part of the gate insulating layer at corresponding positions corresponding to the first metal pattern by using a wet etching process to form the intermediate hole.
7. The method for preparing a composite material according to claim 6, wherein the step S13 includes the steps of:
and forming a second metal layer on the metal oxide layer, forming a thin film transistor and a second metal pattern after patterning, wherein the second metal pattern is in contact with the first metal pattern through the gate insulating layer via hole.
8. An array substrate prepared by the method according to any one of claims 1 to 7.
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| CN201811194117.2A CN109659312B (en) | 2018-10-15 | 2018-10-15 | Array substrate and preparation method thereof |
| PCT/CN2018/124436 WO2020077861A1 (en) | 2018-10-15 | 2018-12-27 | Array substrate and preparation method therefor |
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| CN110783321B (en) * | 2019-10-15 | 2021-03-19 | 福建省福联集成电路有限公司 | Method for manufacturing SMIM capacitor structure and capacitor structure |
| CN110634795B (en) * | 2019-10-23 | 2022-12-02 | 京东方科技集团股份有限公司 | Preparation method of array substrate, array substrate and display device |
| CN111261644B (en) * | 2020-03-10 | 2023-05-02 | Tcl华星光电技术有限公司 | Array substrate and its preparation method |
| CN115360141B (en) * | 2022-08-23 | 2024-05-03 | 昆山龙腾光电股份有限公司 | Metal oxide thin film transistor array substrate and manufacturing method thereof |
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