CN109657323B - Wavelet reconstruction accelerating circuit - Google Patents

Abstract

The invention discloses a wavelet reconstruction accelerating circuit, which comprises m reconstruction units, wherein each reconstruction unit comprises a data input port, a data selection signal input port, a high-pass filtering parameter input port, a low-pass filtering parameter input port, a convolution data input port and an output port, the m reconstruction unit is an initial reconstruction unit, and the input data of the corresponding convolution data input port is 0; the 1 st reconstruction unit is a termination reconstruction unit, and the corresponding output port outputs the reconstruction data of the reconstruction acceleration circuit; the output port of the reconstruction unit is connected with the convolution data input port of the next reconstruction unit. The wavelet reconstruction accelerating circuit provided by the invention improves the calculation proportion of useful data calculation in the whole calculation, realizes the sharing of the multiplier and the adder through the control of parameters and data flow, further reduces the circuit area and effectively reduces the power consumption.

Description

A wavelet reconstruction acceleration circuit

technical field

The invention belongs to the field of digital circuits, and in particular relates to a wavelet reconstruction acceleration circuit.

Background technique

The basic idea of Fourier transform is to use sine and cosine functions to represent a certain function, so as to map a time-domain signal to the frequency domain and complete the frequency-domain analysis of the signal. However, the periodicity of the sine and cosine functions makes the Fourier transform unable to reflect the information of the signal in the time domain well. Precision in the frequency domain leads to ambiguity in the time domain, and precision in the time domain also leads to ambiguity in the frequency domain. Wavelet transform, which uses the translation and stretching of basis functions to represent the target signal, can reflect the information of the signal in the time domain and frequency domain at the same time, so it has gradually attracted attention.

Wavelet transform is widely used in digital signal processing and image processing. Its main steps are divided into two steps, namely signal decomposition and reconstruction. In the decomposition process of the signal, there are basic operations such as convolution and downsampling. The performance of the two basic operations determines the performance of the wavelet operation. In the design process of the wavelet computing hardware accelerator, factors such as circuit computing speed, power consumption, and area need to be considered at the same time, and the calculation process and timing should be properly arranged in order to obtain the best results.

The reconstruction of the wavelet transform is just the opposite of the decomposition process. The low-pass and high-pass data are up-sampled respectively, and the corresponding high-pass and low-pass reconstruction filters are used to add the two to finally calculate the corresponding result. The entire process of data reconstruction can be understood as synthesizing new data from low-pass and high-pass data. If the data volumes of the high-pass and low-pass are n respectively, the combined data volume is 2n.

The basic process of wavelet reconstruction is shown in Figure 1. The input data x1(n) and x2(n) are up-sampled by 2 times, and the corresponding low-frequency and high-frequency reconstruction filters are used to generate The new data flow sequence is conv1(n) and conv2(n), and the two are added to complete the data reconstruction of the first layer. The reconstruction method of the second layer is similar to that of the first layer, and is also divided into several basic steps of upsampling, filtering and addition. For wavelet reconstruction at different levels, there is a basic structural unit, as shown by the area marked by the dotted line. Optimization of this repeat unit determines the overall performance of the circuit.

In the reconstruction process, the upsampling process is relatively simple, but the filter immediately after it will filter all the data. Since the data stream after upsampling is a sparse data stream adjacent to 0 and valid data, a large number of multiplication and addition operations are redundant in the filtering process. Therefore, it is necessary to further increase the calculation density of useful data, share the relative calculation amount, adjust the data structure, method and structure of wavelet reconstruction, complete the calculation optimization, and design the corresponding hardware acceleration circuit.

Contents of the invention

The purpose of the present invention is to provide a wavelet reconstruction acceleration circuit, which no longer calculates redundant data caused by upsampling, improves the calculation ratio of useful data calculation in the overall calculation, and realizes The multiplier and the adder are shared, the circuit area is further reduced, and the power consumption is effectively reduced.

In order to achieve the above object, the present invention adopts the following technical solution: a wavelet reconstruction acceleration circuit, including m reconstruction units, the reconstruction unit includes a data input port, a data selection signal input port, a high-pass filter parameter input port, a low Through the filter parameter input port, the convolution data input port and the output port, the data input port inputs data x(n), and the data selection signal input port inputs the data selection signal sel, wherein the mth reconstruction unit is The initial reconstruction unit, the input data of its corresponding convolution data input port is 0; the first reconstruction unit is a termination reconstruction unit, and its corresponding output port outputs the reconstruction data of the reconstruction acceleration circuit; The low-pass filter parameter input port inputs the low-pass filter parameter, and the high-pass filter parameter input port inputs the high-pass filter parameter; the output port of the reconstruction unit is connected to the convolution data input port of the next reconstruction unit; m is a wavelet base The length of , and 2≤m.

Further, the reconstruction unit further includes a multiplier, a first adder, a second adder, a first data selector, a second data selector, a third data selector, a first register, and a second register. In the first data selector, the selection of high-pass filter parameters and low-pass filter parameters is completed, and multiplied with the input data; in the second data selector, the selection of the data registered in the previous clock cycle and 0 in the first register is completed, and combined with The data after the above multiplication are added, and the addition result is stored in the first register, and the selection of the above addition result and 0 is completed in the third data selector, and the data of the data input port of the reconstruction unit is added again. Add, and the result of the addition is stored in the second register and used as the output data of the reconstruction unit.

Further, the two selection ends of the first data selector are respectively connected to the high-pass filter parameters and the low-pass filter parameters, the output end of the first data selector is connected to the second input port of the multiplier, and the input Data x(n) is connected to the first input port of the multiplier, the output port of the multiplier is connected to the first input port of the first adder, and the output port of the first adder is connected to the input port of the first register , the output port of the first register is connected to one selection terminal of the second data selector and the third selector at the same time, the other selection terminal of the second data selector and the third selector is connected to 0, and the second The output port of the data selector is connected to the second input port of the first adder, the output port of the third data selector is connected to the first input port of the second adder, and the first adder of the second adder The second input port is the convolution data input port of the reconstruction unit, the output port of the second adder is connected to the input port of the second register, and the output port of the second register is the output port of the reconstruction unit ; The data selection signal sel is simultaneously connected to the enable input terminals of the first data selector, the second data selector and the third data selector, wherein, when 0 is selected in the second data selector, the third data The selector selects the data output from the output terminal of the first register.

Further, the output port of the first register is connected to the first selection terminal of the second data selector and the second selection terminal of the third data selector at the same time, and the second selection terminal of the second data selector is connected to the third data selection terminal The input data of the first selection terminal of the selector is 0.

Further, when the data selection signal sel is 0, both the second data selector and the third data selector are controlled to select the data connected to the first selection end, and the first data selector selects high-pass filter parameters or low-pass filter parameters. Pass filtering parameters, the input data is high-pass data or low-pass data corresponding to the first data selector, and the data selection signal sel input to the reconstruction acceleration circuit for the first time is 1.

Further, when the data selection signal sel is 0, the second data selector and the third data selector are controlled to select the data connected to their second selection terminals, and the first data selector selects high-pass filter parameters or low-pass filter parameters. Pass filtering parameters, the input data is high-pass data or low-pass data corresponding to the first data selector, and the data selection signal sel input to the reconstruction acceleration circuit for the first time is 0.

Further, the output data corresponding to the input data x(n) is delayed by two clock cycles.

Further, the low-pass input data and the high-pass input data in the input data x(n) are arranged alternately.

The beneficial effects of the present invention are: (1) The present invention defines a new data input structure, and the low-pass and high-pass filtering results realize time-division multiplexing in the same data channel.

(2) The calculation of redundant data caused by upsampling is no longer performed, and the calculation ratio of useful data calculation in the overall calculation is improved. At the same time, through the control of parameters and data flow, the sharing of multipliers and adders is realized, and the circuit area is reduced. Further reduction, power consumption has been effectively reduced.

(3) The reasonable parameter position reduces the data calculation delay, so that the overall delay of the circuit will not change due to the expansion of the wavelet base.

(4) With the expansion of the wavelet base dimension, the circuit shown in this patent can be effectively expanded, showing good adaptability to different lengths and different wavelet bases.

Description of drawings

Accompanying drawing 1 is the basic flowchart of existing wavelet reconstruction.

Accompanying drawing 2 is the overall diagram of a wavelet reconstruction acceleration circuit of the present invention.

Accompanying drawing 3 is the circuit connection diagram of the ith reconstruction unit.

Accompanying drawing 4 is the arrangement sequence of input data.

Accompanying drawing 5 is the reconstruction circuit of wavelet base length 6 in the embodiment.

Accompanying drawing 6 is the timing diagram of the wavelet reconstruction acceleration circuit in the embodiment.

Detailed ways

In order to make the purpose, technical solution and advantages of the present invention clearer, the specific implementation manners of the present invention will be further described in detail below in conjunction with the accompanying drawings.

As shown in Figure 2, a wavelet reconstruction acceleration circuit includes m reconstruction units, and the reconstruction unit includes a data input port, a data selection signal input port, a low-pass filter parameter input port, a high-pass filter parameter input port, a volume Product data input port and output port, data input port input data x(n), data selection signal input port input data selection signal sel, wherein, the mth reconstruction unit is the initial reconstruction unit, and its corresponding convolution data The input data of the input port is 0; the first reconstruction unit is a terminating reconstruction unit, and its corresponding output port outputs the reconstruction data of the reconstruction acceleration circuit, and the input port of the first reconstruction unit’s low-pass filter parameter input is low Pass filter parameter a ₁ , high-pass filter parameter b ₁ is input to the high-pass filter parameter input port of the first reconstruction unit; the output port of the k-th reconstruction unit is connected to the convolution data input port of the k-1-th reconstruction unit; The low-pass filter parameter input port of the kth reconstruction unit inputs the low-pass filter parameter a _k , and the high-pass filter parameter input port of the kth reconstruction unit inputs the high-pass filter parameter b _k , where k is the length of the wavelet basis, m and k are both integers, and 2≤m, 1<k≤m

As shown in Figure 3, the i-th reconstruction unit includes a multiplier, a first adder, a second adder, a first data selector mux1, a second data selector mux2, a third data selector mux3, a first The register R _A and the second register R _B assume that the first data selector mux1, the second data selector mux2, and the third data selector mux3 are the same, and each has two selection terminals, which are respectively the first selection terminal and the second selection terminal. terminal, enable input and output ports. The same data selection signal sel controls the first data selector mux1 , the second data selector mux2 , and the third data selector mux3 to simultaneously select the first selection terminal or the second connection terminal to connect to the input data.

In the present invention, the two selection terminals of the first data selector are respectively connected to the high-pass filter parameters and the low-pass filter parameters, the output terminal of the first data selector is connected to the second input port of the multiplier, and the input data x(n) is connected to the multiplier The first input port of the multiplier, the output port of the multiplier is connected to the first input port of the first adder, the output port of the first adder is connected to the input port of the first register, and the output port of the first register is connected to the second data selector at the same time and one selection terminal of the third selector, the other selection terminal of the second data selector and the third selector is connected to 0, the output port of the second data selector is connected to the second input port of the first adder, and the third data The output port of the selector is connected to the first input port of the second adder, the second input port of the second adder is the convolution data input port of the reconstruction unit, and the output port of the second adder is connected to the input of the second register port, the output port of the second register is the output port of the reconstruction unit; the data selection signal sel is simultaneously connected to the enable input terminals of the first data selector, the second data selector and the third data selector. Among them, the relationship between the two selectors of the second data selector and the third data selector in the present invention must satisfy: when 0 is selected in the second data selector, the third data selector selects the output of the output terminal of the first register data.

Assume that the output port of the first register is connected to the first selection terminal of the second data selector and the second selection terminal of the third data selector at the same time, and the second selection terminal of the second data selector and the second selection terminal of the third data selector The input data of a selection terminal is 0. Then there are the following two situations: (1) when the data selection signal sel is 0, both the second data selector and the third data selector are controlled to select the data connected to the first selection end, and the first data selector selects the high-pass filter parameter or For low-pass filter parameters, the input data is high-pass data or low-pass data corresponding to the first data selector, and the data selection signal sel input to the reconstruction acceleration circuit for the first time is 1. (2) When the data selection signal sel is 0, control the second data selector and the third data selector to select the data connected to its second selection end, the first data selector selects high-pass filter parameters or low-pass filter parameters, and input data It is high-pass data or low-pass data corresponding to the first data selector, and the data selection signal sel input to the reconstruction acceleration circuit for the first time is 0. The following is illustrated by taking accompanying drawing 3 as an example:

Please continue to refer to accompanying drawing 3, the high-pass filter parameter b _i is connected to the first selection terminal of the first data selector mux1, the low-pass filter parameter a _i is connected to the second selection terminal of the first data selector mux1, and the first data selector mux1 The output terminal of the multiplier is connected to the second input port of the multiplier, the input data x(n) is connected to the first input port of the multiplier, the output port of the multiplier is connected to the first input port of the first adder, and the output port of the first adder Connect the input port of the first register R _A , the output port of the first register R _A is connected to the first selection end of the second data selector mux2 and the second selection end of the third data selector mux3 at the same time, and the second data selector The input data of the second selection terminal of mux2 and the first selection terminal of the third data selector mux3 is 0, the output port of the second data selector mux2 is connected with the second input port of the first adder, and the output port of the third data selector mux3 The output port is connected to the first input port of the second adder, the second input port of the second adder is the convolution data input port c _i-1 of the reconstruction unit, and the output port of the second adder is connected to the second register R The input port of _B , the output port of the second register _RB is the output port conv _i of the reconstruction unit. Wherein, the data selection signal sel is simultaneously connected to the enable input terminals of the first data selector mux1, the second data selector mux2 and the third data selector mux3, wherein, i represents the i-th reconstruction unit, 1≤i≤m .

Please continue to refer to accompanying drawing 3, sel=0 is used for selecting the first selection terminal of the first data selector mux1, the second data selector mux2 and the third data selector mux3, and sel=1 is used for selecting the first data selector The second selection end of mux1, the second data selector mux2 and the third data selector mux3, that is, when sel=0, the first data selector mux1, the second data selector mux2 and the third data selector mux3 select its The data corresponding to the first selection terminal, when sel=1, the first data selector mux1, the second data selector mux2 and the third data selector mux3 select the data corresponding to the second selection terminal, as shown in Figure 3 .

Please continue to refer to accompanying drawing 3, when the input data x(n) is low-pass data, the selection signal sel is 1, the first data selector mux1 selects the low-pass filter parameter a _i , and multiplies it with the input data x(n), The multiplication result is stored in the first register _RA . At this time, the data at the convolution data input port of the reconstruction unit is added to the stored data in the first register _RA in the reconstruction unit, and the addition result is stored in the first register RA. Second register _RB , and output on the next clock cycle. When the input data x(n) is high-pass data, the selection signal sel is 0, the first data selector mux1 selects the high-pass filter parameter b _i , multiplies it with the input data x(n), and the multiplication result is compared with the first register R _A The data of the last clock cycle stored in is added, and the addition result is stored in the first register R _A , at this time, the data in the first register R _A is not selected, and the reconstruction unit convolution data input port The data of is used as the output data of the reconstruction unit and is output in the next clock cycle. It is worth noting that, in the structure of Fig. 3, the data selection signal sel input to the reconstruction acceleration circuit for the first time is 1, and the corresponding first selector selects the low-pass filter parameter, so the input to the circuit The data stream is a data stream starting with low-pass data, as shown in FIG. 4 .

In the present invention, the bit width of the multiplier, the adder and the register changes with the bit width of the input data, the bit width of the parameters a, b and the change of the precision required for calculation. The data selection signal sel is used as a control signal to simultaneously control the data selection of the three data selectors. The selection of parameters a and b is controlled in the first data selector to complete the multiplication of corresponding data and parameters. In the second data selector, the selection of the registered data and 0 in the first register in the previous clock cycle is completed, and the selection of whether to enable the integration function in the time domain is completed, and the calculation result is stored in the first register. In the third data selector, by selecting 0 or the calculation result in the first register, the selection of whether to enable or disable the addition function of the calculation result of the previous level and the calculation result of the current level is completed, and stored in the second register.

This circuit completes the sharing of parameters and data between the multiplier and the adder. The categorical processing and addition of categorical data is completed. A total of one multiplier and two adders are consumed. Even considering part of the data selection circuit, the circuit area is greatly reduced compared to the traditional split-channel calculation scheme. From data input to final data output, the overall latency is 2 clock cycles.

As shown in Figure 5, it is a circuit with a wavelet base length of 6, and the input data are x1, x2, x3, x4..., where the odd-numbered data corresponds to the output of the low-pass filter, and the even-numbered data corresponds to the output of the high-pass filter . The corresponding reconstruction filter coefficients are low-pass filter parameters {a1, a2, a3, a4, a5, a6} and high-pass filter parameters {b1, b2, b3, b4, b5, b6} respectively. Wherein conv6-conv2 are data outputs from the sixth reconstruction unit to the second reconstruction unit. Conv is the overall output. Wherein, the specific operation of the circuit in the wavelet reconstruction process is shown in Table 1, its final output data is shown in Table 2, and its corresponding timing diagram is shown in Figure 6, wherein, in Figure 6, a Please refer to the values in Table 1 for the values of and b. When the data selection signal sel=1, the parameter a is selected, multiplied by the input data, and stored in the first register R _A. At the same time, the data in the first register _RA is selected, added to the convolution result of the previous stage, stored in the second register _RB , and output in the next clock cycle. When sel=0, parameter b is selected and multiplied with the input data, and the multiplication result is added to the data in the first register R _A and stored in the first register R _A. The data in the first register R _A is not selected, and the convolution input of the upper stage is directly used as the final result and output in the next clock cycle.

Table 1 The specific calculation results of the wavelet base with length 6 in the process of data reconstruction

Table 2 The output data of the wavelet base with length 6 in the process of data reconstruction

input output x1 0 x2 a1*x1+b1*x2 x3 a2*x2+b2*x2 x4 a3*x1+a1*x3+b3*x2+b1*x4 x5 a4*x1+a2*x3+b4*x2+b2*x4 x6 a5*x1+a3*x3+a1*x5+b5*x2+b3*x4+b1*x6 x7 a6*x1+a4*x3+a2*x5+b6*x2+b4*x4+b2*x6 x8 a5*x3+a3*x5+a1*x7+b5*x4+b3*x6+b1*x8 x9 a6*x3+a4*x5+a2*x7+b6*x3+b4*x6+b2*x8 x10 a5*x5+a3*x7+a1*x9+b5*x6+b3*x8+b1*x10 x11 a6*x5+a4*x7+a2*x9+b6*x6+b4*x8+b2*x10 x12 a5*x7+a3*x9+a1*x11+b5*x8+b3*x10+b1*x12 x13 a6*x7+a4*x9+a2*x11+b6*x8+b4*x10+b2*x12 ... ...

The above are only preferred embodiments of the present invention, and the embodiments are not intended to limit the scope of patent protection of the present invention, so all equivalent structural changes made by using the description and drawings of the present invention should be included in the same reason Within the protection scope of the appended claims of the present invention.

Claims (8)

1. A wavelet reconstruction acceleration circuit, characterized in that, comprises m reconstruction units, and the reconstruction unit comprises a data input port, a data selection signal input port, a high-pass filter parameter input port, a low-pass filter parameter input port, Convolution data input port and output port, the data input port input data x(n), the data selection signal input port input data selection signal sel, wherein, the mth reconstruction unit is the initial reconstruction unit, its The input data of the corresponding convolution data input port is 0; the first reconstruction unit is a termination reconstruction unit, and its corresponding output port outputs the reconstruction data of the reconstruction acceleration circuit; the low-pass filter parameter input port Input low-pass filter parameters, the high-pass filter parameter input port input high-pass filter parameters; the output port of the reconstruction unit is connected to the convolution data input port of the next reconstruction unit; m is the length of the wavelet base, and 2≤ m. 2. A wavelet reconstruction acceleration circuit according to claim 1, wherein the reconstruction unit further comprises a multiplier, a first adder, a second adder, a first data selector, a second data Selector, the third data selector, the first register and the second register, complete the selection of high-pass filter parameters and low-pass filter parameters in the first data selector, and multiply with the input data; in the second data selector Complete the selection of the registered data and 0 in the previous clock cycle in the first register, and add the data after the above multiplication, the addition result is stored in the first register, and the above addition result and sum are completed in the third data selector 0, and add it again to the data at the data input port of the reconstruction unit, and the result of the addition is stored in the second register as the output data of the reconstruction unit. 3. A kind of wavelet reconstruction acceleration circuit according to claim 2, characterized in that, the two selection terminals of the first data selector are respectively connected with a high-pass filter parameter and a low-pass filter parameter, and the first data selector The output terminal of the multiplier is connected to the second input port of the multiplier, the input data x(n) is connected to the first input port of the multiplier, and the output port of the multiplier is connected to the first input of the first adder Port, the output port of the first adder is connected to the input port of the first register, and the output port of the first register is connected to a selection terminal of the second data selector and the third selector at the same time, and the second data selection The other selection terminal of the third selector and the third selector is connected to 0, the output port of the second data selector is connected to the second input port of the first adder, and the output port of the third data selector is connected to the The first input port of the second adder, the second input port of the second adder is the convolution data input port of the reconstruction unit, the output port of the second adder is connected to the input of the second register Port, the output port of the second register is the output port of the reconstruction unit; the data selection signal sel is simultaneously connected to the enable input of the first data selector, the second data selector and the third data selector terminal, wherein, when 0 is selected in the second data selector, the third data selector selects the data output from the output terminal of the first register. 4. A wavelet reconstruction acceleration circuit according to claim 3, wherein the output port of the first register is simultaneously connected to the first selection end of the second data selector and the second selection end of the third data selector. The input data of the second selection terminal of the second data selector and the first selection terminal of the third data selector are 0. 5. A wavelet reconstruction acceleration circuit according to claim 4, characterized in that, when the data selection signal sel is 0, both the second data selector and the third data selector are controlled to select the first selection The first data selector selects high-pass filter parameters or low-pass filter parameters, the input data is high-pass data or low-pass data corresponding to the first data selector, and the first input The data selection signal sel in the reconstruction acceleration circuit is 1. 6. A wavelet reconstruction acceleration circuit according to claim 4, wherein when the data selection signal sel is 0, the second data selector and the third data selector are controlled to select their second selection The first data selector selects high-pass filter parameters or low-pass filter parameters, the input data is high-pass data or low-pass data corresponding to the first data selector, and the first input The data selection signal sel in the reconstruction acceleration circuit is 0. 7. The wavelet reconstruction acceleration circuit according to claim 2, wherein the output data corresponding to the input data x(n) is delayed by two clock cycles. 8 . The wavelet reconstruction acceleration circuit according to claim 1 , wherein the low-pass input data and high-pass input data in the input data x(n) are arranged alternately.

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