CN109643651A - The manufacturing method of etching stopping layer and semiconductor devices - Google Patents
The manufacturing method of etching stopping layer and semiconductor devices Download PDFInfo
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- CN109643651A CN109643651A CN201880003102.5A CN201880003102A CN109643651A CN 109643651 A CN109643651 A CN 109643651A CN 201880003102 A CN201880003102 A CN 201880003102A CN 109643651 A CN109643651 A CN 109643651A
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- layer
- etching
- etching stopping
- stopping layer
- etched
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- 238000005530 etching Methods 0.000 title claims abstract description 68
- 239000004065 semiconductor Substances 0.000 title claims abstract description 16
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 13
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims abstract description 20
- 229910052796 boron Inorganic materials 0.000 claims abstract description 20
- 229910052727 yttrium Inorganic materials 0.000 claims abstract description 3
- VWQVUPCCIRVNHF-UHFFFAOYSA-N yttrium atom Chemical compound [Y] VWQVUPCCIRVNHF-UHFFFAOYSA-N 0.000 claims abstract description 3
- 238000001039 wet etching Methods 0.000 claims description 15
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims description 12
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 6
- 229920005591 polysilicon Polymers 0.000 claims description 6
- 238000003475 lamination Methods 0.000 claims description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 3
- 239000001301 oxygen Substances 0.000 claims description 3
- 229910052760 oxygen Inorganic materials 0.000 claims description 3
- 239000010410 layer Substances 0.000 description 72
- 239000000758 substrate Substances 0.000 description 30
- 238000000034 method Methods 0.000 description 18
- 238000004544 sputter deposition Methods 0.000 description 15
- 239000007789 gas Substances 0.000 description 11
- 239000000463 material Substances 0.000 description 10
- 229910052782 aluminium Inorganic materials 0.000 description 9
- 239000004411 aluminium Substances 0.000 description 9
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 9
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 6
- 230000003647 oxidation Effects 0.000 description 6
- 238000007254 oxidation reaction Methods 0.000 description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 229910052814 silicon oxide Inorganic materials 0.000 description 4
- PNEYBMLMFCGWSK-UHFFFAOYSA-N Alumina Chemical compound [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 229910052786 argon Inorganic materials 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000002474 experimental method Methods 0.000 description 3
- 239000002245 particle Substances 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 238000004380 ashing Methods 0.000 description 2
- 238000005086 pumping Methods 0.000 description 2
- 238000003860 storage Methods 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- XPDWGBQVDMORPB-UHFFFAOYSA-N Fluoroform Chemical compound FC(F)F XPDWGBQVDMORPB-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 230000008676 import Effects 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 239000011261 inert gas Substances 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 239000002365 multiple layer Substances 0.000 description 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 230000001737 promoting effect Effects 0.000 description 1
- 238000005546 reactive sputtering Methods 0.000 description 1
- 230000009257 reactivity Effects 0.000 description 1
- 239000003507 refrigerant Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
- 238000005477 sputtering target Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
- H01L21/76813—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving a partial via etch
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
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- Microelectronics & Electronic Packaging (AREA)
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- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Plasma & Fusion (AREA)
- Drying Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Electrodes Of Semiconductors (AREA)
- Weting (AREA)
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
Abstract
The present invention provides the manufacturing method of a kind of etching stopping layer when being wet etched with excellent controlling and semiconductor devices.When etching etched layer (Le) in one direction by dry ecthing, etching stopping layer of the invention (Ls) is laminated on front side of the etching direction of propulsion of etched layer, the etching stopping layer is made of the pellumina (BAlOx film, YAlOx film) of the boron containing 20~50 weight % or yttrium.
Description
Technical field
The present invention relates to a kind of etching stopping layer and the laminar structure with the etching stopping layer and etched layer half
The manufacturing method of conductor device.
Background technique
As it is known in the semiconductor devices of large capacity, such as patent document 1 will be made of storage unit longitudinal lamination
3D (three-dimensional) nand flash memory.It include: the process to form etching stopping layer in the manufacturing process of the 3D-NAND flash memory；Stop in etching
Only lamination constitutes the polysilicon layer of storage unit or the process of silicon oxide layer etc. on layer；And using the product after these laminations as quilt
Etching layer, the process that longitudinal dry ecthing etched layer forms the hole of wiring formation.Usually using as pellumina conduct
Etching stopping layer.
Further more, using the etching solutions wet etching etching stopping layer such as hydrofluoric acid after forming hole by dry ecthing.However, oxidation
The wet-etch rate of aluminium film isLeft and right, than very fast, it is difficult to the opportunity of wet etching is being suitble to terminate.Once wet etching
End opportunity delay, then since wet etching isotropically promotes, so can generate to etching stopping layer in lateral over etching
The problem of.The problem is more significant when the thickness of aluminum oxide film is thin.The etching stopping layer of pellumina composition is not as a result,
To the good product of wet etching controlling.
Existing technical literature
Patent document
[patent document 1] Japanese Patent Publication 2016-25141 bulletin
Summary of the invention
Technical problems to be solved by the inivention
In view of the foregoing, the etching that the subject of the invention is to provide a kind of when being wet etched with excellent controlling stops
The only manufacturing method of layer and semiconductor devices.
Solve the means of technical problem
To solve the above subject, etching stopping layer of the invention, it is characterised in that: lost in one direction when by dry ecthing
When carving etched layer, be laminated the etching stopping layer on front side of the etching direction of propulsion of etched layer, the etching stopping layer by
The pellumina of boron containing 20~50 weight % is constituted.
Etching stopping layer can be reduced due to the boron containing 20~50 weight % in pellumina using the present invention
Wet-etch rate.Using experiment described below, it is thus identified that, can be by wet corrosion when hydrofluoric acid being used to carry out wet etching as etching solution
Speed control is carved to existIn the range of.To which the etching in wet etching with excellent controlling can be obtained
Stop-layer.
The etched layer by use oxygen carry out dry ecthing, be laminated 32 layers and 32 layers or more polysilicon layer and
When the laminated film of siliceous insulating layer is constituted, it can be applicable in the present invention well.
Manufacturing, there is the of the invention of semiconductor devices of the laminar structure of above-mentioned etching stopping layer and etched layer partly to lead
The manufacturing method of body device characterized by comprising after etched layer described in dry ecthing, selected using from hydrofluoric acid etc.
A kind of etching solution carry out the process of etching stopping layer described in wet etching, the wet-etch rate setting of the etching stopping layer existsIn the range of.
Detailed description of the invention
Fig. 1 is the diagrammatic cross-section using the semiconductor devices of the etching stopping layer of embodiments of the present invention.
Fig. 2 (a)~(d) is the diagrammatic cross-section for illustrating the manufacturing method of semiconductor devices.
Fig. 3 is the figure for schematically illustrating to be formed the sputtering equipment of the etching stopping layer of embodiments of the present invention.
Fig. 4 is the chart for showing the experimental result for confirming effect of the present invention.
Specific embodiment
The semiconductor devices for the etching stopping layer for being applicable in embodiments of the present invention is illustrated with reference to the accompanying drawings.
As shown in Figure 1, semiconductor devices SD has the etching stopping layer Ls and etch stop formed on substrate S, substrate S
The etched layer Le formed on layer Ls.
It, can be according to the type of semiconductor devices SD, from silicon substrate, GaAs substrate, GaP substrate, InP substrate as substrate S
It suitably selects and uses in.Further more, substrate S includes the semiconductor element for forming transistor etc. on the surface of substrate S
Substrate.
When etching etched layer Le in one direction by dry ecthing, on front side of the etching direction of propulsion of etched layer Le
(downside) is laminated etching stopping layer Ls.Etching stopping layer Ls by the boron containing 20~50 weight % pellumina (BAlOx film)
It constitutes.Boron content is unable to fully inhibit the wet-etch rate of etching stopping layer Ls, another party sometimes less than 20 weight %
Face, if boron content is more than 50 weight %, dry ecthing tolerance declines sometimes.
Etched layer Le is, for example, multilayer (such as the 32 layers and 32 layers or more) polysilicon layer and siliceous insulating layer being laminated
Laminated film layer.Herein, it can be used silicon oxide film, silicon nitride film or silicon oxynitride film as siliceous insulating layer.Join below
It is illustrated according to manufacturing method of the Fig. 2 to above-mentioned semiconductor device SD.
Firstly, forming etching stopping layer Ls on substrate S as shown in Fig. 2 (a).Herein, etching stopping layer Ls can be used such as
Sputtering equipment SM shown in Fig. 3 is formed.Sputtering equipment SM has the vacuum chamber 1 for limiting process chamber 10, in the side wall of vacuum chamber 1
On, connect the tracheae 11 for importing sputter gas in oriented process chamber 10, plug mass flow controller 12 on tracheae 11, and with splash
Emanate body gas source 13 be connected to.In sputter gas in addition to the inert gases such as argon gas, when carrying out reactive sputtering, comprising oxygen and
Vapor isoreactivity gas.It is connected on the bottom wall of vacuum chamber 1 and connects with vacuum pumping hardwares P such as rotary pump, turbomolecular pumps
Logical exhaust pipe 14.The pressure of process chamber 10 in film forming procedure is set to keep approximately fixed as a result,.
The bottom center of vacuum chamber 1 is provided with substrate rack 2.Substrate rack 2 is for example by having the profile pair with substrate S
The base station 21 of the metal material for the upper surface shape answered, and it is mounted on the composition of snap-gauge 22 of the upper surface of the base station 21.Snap-gauge
The well known electrode of illustration omitted is built-in in 22, by from chuck power supply to the electrode apply chucking voltage, can make substrate S with
Its film forming is adsorbed upward and is maintained at 22 upper surface of snap-gauge.It is connected in the lower surface center of base station 21 and is supported by bearing 23
Rotary shaft 24, the opening on 1 bottom surface of vacuum chamber is arranged in 23 break-through of bearing, and the driving portion for passing through 1 outside of vacuum chamber (saves
Sketch map shows) the driving rotary shaft 24 is rotated, substrate rack 2 can be made to keep the state of substrate S to rotate.In addition, may be alternatively provided as
It is built-in with refrigerant circulation channel and heater in base station 21, during spatter film forming, substrate S can also be controlled in regulation temperature
Degree.
In the inner top of vacuum chamber 1, circumferentially-spaced 180 ° are tiltedly installed with two pieces of targets 3a, 3b, so that sputter face 3a, 3b point
It is not opposite with substrate S.It can be used the target of oxidation aluminium material as target 3a, can be used the target of boron material as target 3b.Although omitting
Diagram, but at the upper surface of target 3a, 3b (back to the face of sputter face 3a, 3b), pass through the material high by pyroconductivities such as indium or tin
Expect the adhesives constituted, is bonded to the backboard of the copper material of cooled target 3a, 3b during spatter film forming.In addition, can also be
Well known magnet unit is respectively configured above each target 3a, 3b, makes to generate magnetic in the lower space of target 3a, 3b sputter face 3a, 3b
(well known closed magnetic field or cusp fields) when sputtering, capture electronics of ionization etc. and effectively in the lower section of sputter face 3a, 3b
Ground ionizes the sputtering particle to disperse from target 3a, 3b.
It is separately connected high frequency electric source E1, E2 as shielding power supply on target 3a, 3b, when sputtering, applies between ground at it
The RF power of assigned frequency (such as 13.56MHz).In addition, it includes microcomputer or sequencer that above-mentioned sputtering equipment SM, which has,
Deng well known control device, be uniformly controlled the work of mass flow controller 12, the work and sputtering of vacuum pumping hardware P
The work etc. of power supply E1, E2.
When using above-mentioned sputtering equipment SM to form the pellumina as etching stopping layer Ls on substrate S, by vacuum
(process chamber 10) is evacuated down to defined vacuum degree (such as 1 × 10 in room 1-5Pa), by not shown carrier robot by base
Plate S is transported in vacuum chamber 1, and substrate S is positioned and maintained on substrate rack 2.Then, mass flow controller 12 is controlled simultaneously
The argon gas (at this point, the pressure of process chamber 10 be 0.1~0.2Pa) of regulation flow is imported, it is matched, from high frequency electric source E1 to target
3a for example applies the 13.56MHz RF power of 100W~500W, and for example applies 100W~500W from high frequency electric source E2 to target 3b
13.56MHz RF power.Plasma is formed in vacuum chamber 1 as a result, target 31 is sputtered.Made by sputtering from target
The sputtering particle attachment that 3a, 3b disperse is deposited in the surface substrate S, to form the pellumina of boracic on the surface substrate S
(BAlOx film).Boron content in pellumina can be by changing the ratio for being applied to the electric power of target 3a and being applied to the electric power of target 3b
Example controls.
Then, mul-tiple layers of polysilicon film or silicon oxide film etc. are formed on etching stopping layer Ls, as etched layer Le.These
The known methods such as sputtering method or CVD method can be used to be formed for polysilicon film or silicon oxide film, therefore, detailed description will be omitted herein.Make
When with well known sputtering equipment, as long as using the target of silicon material as target in process chamber.If existed using known method
If forming the corrosion-resisting pattern as mask layer Lm on etched layer Le, then structure shown in Fig. 2 (a) can be obtained.
Then, as shown in Fig. 2 (b), longitudinal dry ecthing etched layer Le forms wiring hole h on etched layer Le.This
Outside, for the condition of dry ecthing, such as well known RIE condition can be used, uses CHF3、C2F6、CF4Equal fluoro-gas conduct
Etching gas, therefore, detailed description will be omitted herein.
After dry ecthing, as shown in Fig. 2 (c), wet etching etching stopping layer Ls.It can be used and selected such as from hydrofluoric acid
Well known etching solution out is as the etching solution for being used for wet etching.Herein, the etching stopping layer Ls of present embodiment is by containing 20
The pellumina of the boron of~50 weight % is constituted, therefore can reduce the wet-etch rate of etching stopping layer Ls.It therefore, can be appropriate
Opportunity terminates wet etching, can prevent etching stopping layer Ls from horizontally excessively promoting.To the etching stopping layer of present embodiment
Ls is it may be said that have excellent controlling to wet etching.
Finally, semiconductor devices SD shown in Fig. 2 (d) can be obtained after through ashing removal mask layer Lm.In addition, root
According to needs, conductive film is formed in the h of hole.Well known condition can be used therefore to omit herein specifically the condition of ashing
It is bright.
Then, in order to confirm said effect, following experiments are carried out using above-mentioned sputtering equipment SM.In this experiment, Φ is used
The silicon substrate of 300mm is as substrate S, after substrate S is set on the substrate rack 2 in vacuum chamber 1, into process chamber 10 with
Flow 300sccm imports argon gas (the pressure about 1.35Pa in process chamber 10 at this time), from power supply E1 to the target of oxidation aluminium material
3a applies the 13.56MHz RF power of 227W, and applies the 13.56MHz high-frequency electrical of 300W to the target 3b of boron material from power supply E2
Power (the electric power ratio for being applied to target 3a, 3b at this time is 1:1.32).Sputtering target 3a, 3b as a result, is formed on the surface substrate S and is contained 20 weights
Measure the pellumina (BAlOx film) of the boron of % (wt%).Wet etching is somebody's turn to do the aluminium oxide of the boron containing 20 weight %, the erosion measured
Carving speed isUse HF:H2Etching solution of the hydrofluoric acid solution of O=1:2000 (0.05 weight %) as wet etching.
Further more, change the electric power ratio for being applied to target 3a, 3b in a manner of 1:0,1:0.7,1:1,1:1.3,1:1.5,1:1.8,1:2.6,
Thus it is respectively formed the oxidation of the boron containing 0 weight %, 10 weight %, 15 weight %, 25 weight %, 30 weight %, 50 weight %
Aluminium film, measurement wet-etch rate are respectively
It is final as shown in Figure 4.It thereby confirms that:, can by being arranged the boron content in pellumina in the range of 20~50 weight %
The wet-etch rate control of pellumina is existedIn the range of.Further more, confirmed by will be in pellumina
Boron content be arranged in the range of 25~50 weight %, can by the wet-etch rate of pellumina control exist
In the range of.Furthermore, it is thus identified that once boron content is more than 50 weight %, then wet-etch rate is constant, and particle increases.
Embodiments of the present invention are explained above, but the present invention is not limited in aforesaid way.In above embodiment
In, use the target of oxidation aluminium material as target 3a, but can also be used the target of aluminium material as target 3a, it is possible to use reactivity is splashed
The mode for penetrating the target of the aluminium material is constituted.
Further more, in the above-described embodiment, although in case where using two pieces of targets 3a, 3b to form etching stopping layer Ls
It is illustrated, but the target (BAlOx of the oxidation aluminium material of one block of boron containing normal concentration (such as 30 weight %) can be used
Target) form etching stopping layer Ls.
Further more, in the above-described embodiment, although being carried out in case where forming etching stopping layer Ls by sputtering
Illustrate, but the forming method of etching stopping layer Ls is not limited to that, such as film build method well known to usable CVD method etc..Make
When with CVD method, boron content can be controlled by the flow-rate ratio of the unstrpped gas and unstrpped gas containing aluminium that control boracic.
Further more, in the above-described embodiment, although to use the pellumina of the boron containing 20~50 weight % as etching
It is illustrated in case where stop-layer Ls, but when containing the pellumina of the yttrium of 20~50 weight % using not boracic
Same effect can be reached.
Description of symbols
S ... substrate, Ls ... etching stopping layer, Le ... etched layer.
Claims (3)
1. a kind of etching stopping layer, it is characterised in that:
When etching etched layer in one direction by dry ecthing, on front side of the etching direction of propulsion of etched layer described in lamination
Etching stopping layer；
The etching stopping layer is made of the pellumina of the boron containing 20~50 weight % or yttrium.
2. etching stopping layer according to claim 1, it is characterised in that:
The etched layer by use oxygen carry out dry ecthing, be laminated 32 layers and 32 layers or more of polysilicon layer and siliceous
The laminated film of insulating layer is constituted.
3. a kind of manufacturing method of semiconductor devices, it is characterised in that: be that there is etching stopping layer of any of claims 1 or 2
With the manufacturing method of the semiconductor devices of the laminar structure of etched layer, the manufacturing method includes:
After etched layer described in dry ecthing, using the etching solution being made of hydrofluoric acid come the work of etching stopping layer described in wet etching
The wet-etch rate setting of sequence, the etching stopping layer existsIn the range of.
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| JP2017-058670 | 2017-03-24 | ||
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| PCT/JP2018/008299 WO2018173718A1 (en) | 2017-03-24 | 2018-03-05 | Etching stop layer, and method for manufacturing semiconductor device |
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| KR20220163117A (en) | 2021-06-02 | 2022-12-09 | 삼성전자주식회사 | Semiconductor device |
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| US4767724A (en) * | 1986-03-27 | 1988-08-30 | General Electric Company | Unframed via interconnection with dielectric etch stop |
| CN1767171A (en) * | 2004-10-14 | 2006-05-03 | 三星电子株式会社 | Etch stop structure and manufacture method, and semiconductor device and manufacture method |
| US20130084441A1 (en) * | 2011-09-29 | 2013-04-04 | Seagate Technology Llc | Optical articles and methods of making same |
| CN104051256A (en) * | 2013-03-14 | 2014-09-17 | 台湾积体电路制造股份有限公司 | Semiconductor Devices and Methods of Manufacture Thereof |
| US20150187950A1 (en) * | 2013-12-26 | 2015-07-02 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device |
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| US9437606B2 (en) * | 2013-07-02 | 2016-09-06 | Sandisk Technologies Llc | Method of making a three-dimensional memory array with etch stop |
| JP2015056444A (en) * | 2013-09-10 | 2015-03-23 | 株式会社東芝 | Nonvolatile storage device and manufacturing method of the same |
| JP6163446B2 (en) * | 2014-03-27 | 2017-07-12 | 株式会社東芝 | Manufacturing method of semiconductor device |
| JP6290022B2 (en) | 2014-07-17 | 2018-03-07 | 東芝メモリ株式会社 | Manufacturing method of semiconductor device |
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|---|---|---|---|---|
| US4767724A (en) * | 1986-03-27 | 1988-08-30 | General Electric Company | Unframed via interconnection with dielectric etch stop |
| CN1767171A (en) * | 2004-10-14 | 2006-05-03 | 三星电子株式会社 | Etch stop structure and manufacture method, and semiconductor device and manufacture method |
| US20130084441A1 (en) * | 2011-09-29 | 2013-04-04 | Seagate Technology Llc | Optical articles and methods of making same |
| CN104051256A (en) * | 2013-03-14 | 2014-09-17 | 台湾积体电路制造股份有限公司 | Semiconductor Devices and Methods of Manufacture Thereof |
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| CN112289803A (en) * | 2020-10-22 | 2021-01-29 | 长江存储科技有限责任公司 | 3D memory device and method of manufacturing the same |
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| KR20190071829A (en) | 2019-06-24 |
| KR102228330B1 (en) | 2021-03-16 |
| JP6603436B2 (en) | 2019-11-06 |
| WO2018173718A1 (en) | 2018-09-27 |
| CN109643651B (en) | 2023-04-28 |
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