CN109637473B

CN109637473B - Array substrate, display panel and display device

Info

Publication number: CN109637473B
Application number: CN201811521945.2A
Authority: CN
Inventors: 陈伟; 纪飞林
Original assignee: HKC Co Ltd
Current assignee: HKC Co Ltd
Priority date: 2018-12-12
Filing date: 2018-12-12
Publication date: 2021-04-06
Anticipated expiration: 2038-12-12
Also published as: WO2020119641A1; CN109637473A

Abstract

The invention discloses an array substrate, a display panel and a display device, and the array substrate, the display panel and the display deviceThe array substrate comprises a controller; a substrate laid with data lines, wherein the number of the data lines is N, then

The source driving module is connected between the timing controller and the substrate, and comprises a first driving chip and a second driving chip, wherein the first driving chip comprises a first output pin and a first suspension pin, the second driving chip comprises a first output pin and a second suspension pin, the number of the first output pins is defined as x1, the number of the first suspension pins is y1, the number of the second output pins is x2, the number of the second suspension pins is y2, and then x1+ x2 is N; x1+ y1 ═ x2+ y 2. The array substrate provided by the technical scheme of the invention has the advantage of low manufacturing cost.

Description

Array substrate, display panel and display device

Technical Field

The invention relates to the technical field of liquid crystal display, in particular to an array substrate, a display panel and a display device.

Background

The statements herein merely provide background information related to the present application and may not necessarily constitute prior art.

A Thin Film Transistor Liquid Crystal Display (TFT-LCD) utilizes the variation of electric field intensity on a Liquid Crystal layer to change the direction of Liquid Crystal molecules, thereby controlling the intensity of light transmission to Display images.

Generally, the array substrate of the TFT-LCD has two architectures, one is a Normal (Normal) architecture, and the other is a Dual gate line (Dual gate) architecture, and compared with the conventional architecture, the Dual gate line architecture increases the number of gate lines, reduces the number of data lines, and further reduces the number of source driver chips for transmitting pixel data to the data lines, and increases the number of gate driver chips.

However, when the horizontal pixels of the TFT-LCD cannot be divided by 4, due to the transmission of a Mini Low Voltage Differential Signaling (Mini-LVDS) between the Timing Controller (TCON) and the driving chip, when the output signals of the Mini-LVDS are 3 pairs (pair), the Mini-LVDS is a dual-bus topology structure, which may cause the TFT-LCD to display a picture without picture information, and thus the TFT-LCD cannot use a dual-gate line architecture.

Disclosure of Invention

The invention mainly aims to provide an array substrate, which realizes the technical effect that a panel with horizontal pixels incapable of being divided by 4 is in a double-grid structure.

In order to achieve the above object, the array substrate provided by the present invention is based on a dual gate line architecture, and includes:

a time schedule controller;

a substrate laid with data lines, wherein the number of the data lines is N, then

And

a source driving module connected between the timing controller and the substrate, the source driving module including a first driving chip and a second driving chip, the first driving chip including a first output pin and a first suspension pin, the second driving chip including a first output pin and a second suspension pin,

defining the number of the first output pins as x1, the number of the first floating pins as y1, the number of the second output pins as x2, and the number of the second floating pins as y2, then

x1+x2＝N；

x1+y1＝x2+y2。

Optionally, N2049, x1 1026, and x2 1023.

Optionally, a plurality of the second flying pins are adjacently arranged.

Optionally, the plurality of second floating pins are also disposed at one end of the second driving chip.

Optionally, the second floating pin is connected to the auxiliary pixel unit.

Optionally, the transmission data of the timing controller is transmitted from the first driving chip to the second driving chip, and the second suspension pin is disposed at one end of the second driving chip close to the first driving chip.

Optionally, a connection line is laid on the array substrate, and the second suspension pin is connected to the auxiliary pixel unit through the connection line.

Optionally, when 2052< N <3078, the source driver module further includes a third driver chip, the third driver chip is located between the first driver chip and the second driver chip, the third driver chip includes a third output pin and a third floating pin, the number of the third output pins is defined as x3, and the number of the third floating pin is defined as y3, then

x1＝x2＝1026；

x3＝N-x1-x2；

(x3+y3)|2。

The invention further provides a display panel, which comprises an array substrate based on the double-grid-line architecture, wherein the array substrate comprises: a time schedule controller;

And

x1+x2＝N；

x1+y1＝x2+y2。

The invention further provides a display device, which comprises an array substrate based on the double-grid-line architecture, wherein the array substrate comprises: a time schedule controller;

And

x1+x2＝N；

x1+y1＝x2+y2。

The array substrate provided by the technical scheme of the invention has the advantages that the first suspension pins are arranged on the first driving chip, the second suspension pins are arranged on the second driving chip, and the quantity of the first output pins and the first suspension pins is equal to that of the second output pins and the second suspension pins, so that when image data are transmitted, only the time schedule controller is required to insert a certain amount of virtual data into the first suspension pins and/or the second suspension pins in the image data transmitted to the source electrode driving module, so that the first driving chip and the second driving chip output the same quantity of data, the phenomenon of sub-pixel data loss can be avoided when the array substrate displays a picture, the loss of picture information is avoided, and the problem that a TFT-LCD (thin film transistor-liquid crystal display) with horizontal pixels incapable of being divided by 4 can not use a double-grid structure is solved, the manufacturing cost of such TFT-LCD is reduced.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the structures shown in the drawings without creative efforts.

Fig. 1 is a schematic structural diagram of an array substrate having 1366 × 768 pixels in a display area and based on a dual gate line architecture

FIG. 2 is a schematic diagram illustrating data transmission between a timing controller and a source driving module according to an embodiment of the present invention;

FIG. 3 is a schematic structural diagram of the array substrate in the embodiment shown in FIG. 2;

fig. 4 is a schematic diagram illustrating data transmission between a timing controller and a source driving module according to another embodiment of the invention.

The implementation, functional features and advantages of the objects of the present invention will be further explained with reference to the accompanying drawings.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

It should be noted that, if directional indications (such as up, down, left, right, front, and back … …) are involved in the embodiment of the present invention, the directional indications are only used to explain the relative positional relationship between the components, the movement situation, and the like in a specific posture (as shown in the drawing), and if the specific posture is changed, the directional indications are changed accordingly.

In addition, if there is a description of "first", "second", etc. in an embodiment of the present invention, the description of "first", "second", etc. is for descriptive purposes only and is not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In addition, the meaning of "and/or" appearing throughout is to include three juxtapositions, exemplified by "A and/or B" including either scheme A, or scheme B, or a scheme in which both A and B are satisfied. In addition, technical solutions between various embodiments may be combined with each other, but must be realized by a person skilled in the art, and when the technical solutions are contradictory or cannot be realized, such a combination should not be considered to exist, and is not within the protection scope of the present invention.

Referring to fig. 1, fig. 1 is a schematic structural diagram of an array substrate having 1366 × 768 pixels in a display area and based on a dual gate line architecture, and a data line 1 is laid on the substrate of the array substrate. Generally, a display panel displays a picture of one pixel and requires an array substrate to simultaneously output information of 3 sub-pixels 7 (i.e., R/G/B), in a conventional architecture, since one data line 1 controls only one sub-pixel 7, the array substrate with 1366 pixels in a horizontal row requires 1366 × 3 — 4098 data lines 1, while in a dual-gate architecture, since one data line 1 can control two sub-pixels 7, only 1366 × 3/2 — 2049 data signals need to be laid on the array substrate in the dual-gate architecture.

Generally, when the array substrate displays a picture, the timing controller 3 is required to sequence the received image data in a certain time sequence, and then the image data is transmitted to each data line 1 through the source driver chip to transmit different voltage signals to each sub-pixel 7, so that each sub-pixel 7 displays with different brightness. Each source driving chip has 1026 output channels at most, and the source driving chips are communicated with the data lines 1 through output pins, that is, one source driving chip can transmit data to 1026 data lines 1 at most, so in the dual-gate-line architecture of the 1366 pixel substrate, at least two source driving chips are required to transmit data information to 2049 data lines 1.

Still further, data transmission between the timing controller 3 and the driving chip is realized by Mini Low Voltage Differential Signaling (Mini-LVDS). From the topological structure, the Mini-LVDS has two buses, each bus carries the image data of the left half panel and the right half panel respectively (i.e. the two buses transmit the image data of half of the display area of the array substrate respectively). In the transmission, the timing controller 3 divides the data of one row of pixels into two parts and transmits the two parts to the source driver chips in charge of the left half panel and the right half panel of the array substrate, in this embodiment, the data of the timing controller 3 is transmitted to the two source driver chips, so that each source driver chip theoretically receives 2049/2 ═ 1024.5 parts of data, that is, each source driver chip has 1024.5 output channels connected to the data lines 1, but in practice, both the output channels and the data lines 1 are in units of positive integers. Therefore, in actual design, two source driver chips will be connected to 1025 and 1024 data lines 1, respectively. Taking this case as an example, the R sub-pixel 7 of the 684 th pixel is connected to the 1025 th data line 1, the G sub-pixel 7 and the B sub-pixel 7 of the 684 th pixel are controlled by the 1026 th data line 1, and since the data received by each source driver chip from the timing controller 3 is only the pixel data controlled by the 1024.5 th data line 1, the 1025 th data line 1 can actually transmit the voltage signal to only the B sub-pixel 7 of the 683 th pixel, which results in that the R sub-pixel 7 of the 684 th pixel cannot be lit when the array substrate displays a picture, thereby resulting in the loss of image data; meanwhile, the driver chip connected with 1024 data lines 1 cannot completely output 1024.5 the data information carried by the data line 1, so that image data of one sub-pixel 7 is lost for a certain pixel on the other half of the panel, which results in the loss of picture information when the array substrate displays images. Therefore, in the prior art, a double-gate-line architecture cannot be adopted for the array substrate with 1366 pixels in the horizontal row, so that the cost of the array substrate with 1366 pixels in the horizontal row is high.

It should be noted that the horizontal row of pixels referred to in this application does not limit the pixels in the horizontal direction on the array substrate, but refers to the pixels on the array substrate that are charged with the voltage signals transmitted by the data lines 1. Meanwhile, reasonable calculation shows that the double-gate line structure cannot be used for the array substrate with the horizontal pixels not being evenly divided by 4.

The invention provides an array substrate, aiming at solving the technical problem that a panel with horizontal pixels incapable of being divided by 4 cannot use a double-grid-line structure.

In an embodiment of the invention, please refer to fig. 2 and 3, the array substrate includes a timing controller 3, a substrate, and a source driving module 4, wherein the substrate is laid with data lines 1, and the number of the data lines 1 is defined as N, then

The source driving module 4 is connected between the timing controller 3 and the substrate, and includes a first driving chip 41 and a second driving chip 42, where the first driving chip 41 includes a first output pin and a first suspension pin, and the second driving chip 42 includes a second output pin and a second suspension pin 421;

defining the number of the first output pins as x1 and the number of the first floating pins as y 1;

the number of the second output pins is x2, and the number of the second flying pins 421 is y 2;

then the process of the first step is carried out,

x1+x2＝N；

x1+y1＝x2+y2。

in addition, the symbols

In mathematics, the meaning is "division by no integer", i.e.

The term "N" means that N is not evenly divisible by 6, and the number of data lines 1N is equal to 3/2 corresponding to the horizontal pixels of the array substrate

I.e. it means that the horizontal rows of pixels of the array substrate cannot be divided by 4.

It should be noted that, the first output pin described in this application refers to a pin where the first driving chip 41 is connected to the data line 1 and can transmit a voltage signal of the sub-pixel 7, and the first floating pin refers to a pin where the first driving chip 41 is connected to the data line 1, but transmitted data cannot be displayed in the display area of the array substrate, or transmitted data cannot be displayed in the display area of the array substrate without being connected to the data line 1. In the technical solution disclosed in the present application, the number of the first or second floating pins 421 may be set to 0. Meanwhile, since the second output pin has the same function as the first output pin, and the second floating pin 421 has the same function as the first floating pin, the description thereof is omitted.

It can be understood that, in the array substrate provided by the technical solution of the present invention, by arranging the first floating pins on the first driving chip 41 and the second floating pins 421 on the second driving chip 42, the number of the first output pins plus the first floating pins is equal to the number of the second output pins and the second floating pins 421, so that, when transmitting image data, only the timing controller 3 is required to insert a certain amount of dummy data into the first floating pins and/or the second floating pins 421 in the image data transmitted to the source driving module 4, so as to enable the first driving chip 41 and the second driving chip 42 to output the same amount of data, thereby avoiding the phenomenon of data loss of the sub-pixels 7 when the array substrate displays a picture, avoiding the loss of picture information, and further solving the problem that the TFT-LCD in which the horizontal pixels cannot be completely divided by 4 cannot use a dual-gate architecture, the manufacturing cost of such TFT-LCD is reduced.

It should be noted that the dummy data referred to in the present application refers to data information inserted into the image data by the timing controller 3, which may be data of any form, but can only be transmitted to the first floating pin and/or the second floating pin 421 in a directional manner, and thus cannot be displayed in the display area of the array substrate.

Specifically, in this embodiment, an array substrate of 1366 × 768 pixels is taken as an example to explain how to use a dual-gate architecture for an array substrate in which horizontal pixels cannot be divided by 4 by the technical solution of the present application. At this time, N1366 × 3/2 is 2049, the number x1 of the first output pins is 1026, the number x2 of the second output pins is 1023, the number y1 of the first floating pins is 0, and the number y2 of the second floating pins 421 is 3.

While the timing controller 3 actually receives 2049 data lines 1 of image data when outputting video, in the present embodiment, the first driving chip 41 and the second driving chip 42 share x1+ y1+ x2+ y2 of 1026+0+1023+3 of 2052 output pins, that is, 2052 output channels of data. At this time, when the timing controller 3 transmits the image data to the source driving module 4, 3 pieces of virtual data of non-frame data are inserted into 2049 pieces of data to obtain temporary storage data occupying 2052 output channels, and the temporary storage data are both two pieces and are respectively transmitted to the first driving chip 41 and the second driving chip 42, since the number of the first output pins of the first driving chip 41 is 1026 and the number of the second output pins of the second driving chip 42 is 1023, 3 pieces of virtual data inserted by the timing controller 3 are transmitted to 3 second suspending pins 421 of the second driving chip 42, since the data transmitted by the second suspending pins 421 are not displayed in the display area of the array substrate, the actually displayed frame is consistent with the frame received by the timing controller 3, thereby avoiding the missing of frame information, and then a double-gate line framework is realized, thereby reducing the manufacturing cost of the array substrate.

As can be seen from the above, no matter whether the array substrate is connected to the data line 1 by the even number of source driver chips or the odd number of source chips, the dual gate line architecture can be implemented by the technical scheme of the present application, and the core of the odd number scheme of the present application is to provide a floating pin in the source driver chip, and insert a certain amount of dummy data when the timing controller 3 transmits data to the source driver module 4, so that the left and right sides of the source driver module 4 can transmit complete image data.

It should be noted that, the number of the floating pins disposed in the source driver chip is not limited to 3, but different numbers of floating pins may be inserted according to different pixels in a specific row, and the number of the first floating pins or the second floating pins 421 may be adaptively adjusted according to actual production applications.

In the embodiment, the number N of the data lines 1 is 2049, that is, the horizontal row of pixels of the array substrate is 1366, while in practical production applications, the array substrate of 1366 × 768 pixels is widely applied in portable computers, so that the dual-gate architecture is used for the array substrate of 1366 × 768 pixels, which has a wide application range and great economic benefits. Of course, the technical solution disclosed in the present application is not only directed to the array substrate with 1366 horizontal pixels.

As can be seen from fig. 2 and fig. 3, in the embodiment, x1 is 1026, y1 is 0, x2 is 1023, and y2 is 3, that is, only the second floating pin 421 is disposed on the second driver chip 42, but not the first floating pin. This has the advantage that, first, as shown in fig. 1 and fig. 2, the 684 th sub-pixel 7 is controlled by the 1025 th data line 1 and the 1026 th data line 1, since the first driving chip 41 is responsible for transmitting the image data of the left half of the display area of the array substrate under the Mini-LVDS transmission protocol, by setting the first output pins of the first output chip to 1026, it is possible to make 684 th pixels, that is, all the sub-pixels 7 of one pixel are transmitted by the same bus, so as to prevent the sub-pixels 7 of one pixel from being transmitted by different buses, and correspondingly, in order to balance the data amount transmitted in the Mini-LVDS two buses, the timing controller 3 inserts 3 pieces of dummy data into the video transmitted to the second driving chip 42, so that 3 second suspension pins 421 are correspondingly arranged on the second driving chip 42.

It should be noted that, when the three sub-pixels 7 of one pixel respectively have two buses of Mini-LVDS for transmission, in order to prevent the display frame from tearing, the timing controller 3 will increase the output frequency to increase the refresh frequency of the frame displayed on the array substrate, which will increase the power consumption of the timing controller 3 and increase the temperature of the timing controller 3, which is not favorable for the performance of the timing controller 3. Therefore, all the sub-pixels 7 of one pixel are transmitted by the same bus of the Mini-LVDS, so that the stability of the image display of the array substrate can be improved, the power consumption can be reduced, and the stability of the performance exertion of the time schedule controller 3 can be ensured.

It should be noted that, in other embodiments of the present application, for the array substrate with 1366 pixels in the horizontal row, the first driving chip 41 and the second driving chip 42 may be further configured to implement a dual-gate architecture according to the following data:

(1)x1＝1025,y1＝0；x2＝1024,y2＝1；

(2)x1＝1025,y1＝1；x2＝1024,y2＝2。

moreover, since only the second suspension pin 421 needs to be disposed on the second driving chip 42, and the first suspension pin does not need to be disposed on the first driving chip 41, the amount of work can be saved, the manufacturing time of the array substrate can be reduced, and the cost can be reduced.

Optionally, as shown in fig. 2, in the present embodiment, the plurality of second floating pins 421 are disposed adjacent to each other. Since the timing controller 3 needs to insert the dummy data having the same number as the second floating pins 421 through its own configuration when transmitting the video data to the source driving module 4, and directionally transmit the dummy data to the second floating pins 421, the plurality of second floating pins 421 are arranged adjacent to each other, so that the computation amount of the timing controller 3 can be reduced, and the heat generation and the energy consumption of the timing controller 3 can be reduced. In addition, from the perspective of the manufacturing process, the second floating pins 421 are disposed adjacent to each other, which is simpler than the discrete arrangement of the second floating pins 421. It is understood that in some embodiments where the first flying pins are disposed, a plurality of the first flying pins may also be disposed adjacent to each other. It should be noted that, in other embodiments of the present application, the plurality of second floating pins 421 may also be discretely distributed.

Optionally, the plurality of second floating pins 421 are disposed on the same side of the second driving chip 42. Since the TFT-LCD display is turned on line by line, image data is transferred from one side of the source driver chip to the other side while being transferred on the source driver chip. For the timing controller 3, the second floating pin 421 is disposed at one side of the second floating pin 421, and when the dummy data is transmitted to the second driving chip 42, the dummy data only needs to be inserted at the beginning or the end of the image data, so that the required computation amount is lower, and the energy consumption is relatively lower. In terms of the manufacturing process of the second driving chip 42, the physical positions of the plurality of second floating pins 421 are disposed on the same side of the second driving chip 42, which is simpler than disposing the second floating pins 421 on the middle portion of the second driving chip 42, and the time required for manufacturing the second driving chip 42 is also shorter. Of course, the first floating pin can also be configured in the same manner as the second floating pin 421. It should be noted that, in other embodiments of the present application, the second floating pin 421 may also be disposed at a middle position of the second driving chip 42.

Optionally, as shown in fig. 2, in the embodiment, the data transmitted by the timing controller 3 is transmitted from the first driving chip 41 to the second driving chip 42, and the data transmitted to the source driving module 4 is set to be transmitted unidirectionally by the timing control, and correspondingly, the plurality of second floating pins 421 are also disposed at one end of the second driving chip 42 close to the first driving chip 41. It is understood that since the image data is transmitted in one direction, the amount of calculation of the timing controller 3 itself can be reduced to reduce the power consumption of the timing controller 3. The plurality of second floating pins 421 are also disposed on one side of the second driving chip 42 close to the first driving chip 41, which is equivalent to the second floating pins 421 disposed at the beginning of the data transmission of the second driving chip 42, so that for the timing controller 3, the computation amount required for inserting and transmitting the dummy data is lower, which is beneficial to reducing the power consumption of the timing controller 3. It should be noted that, in other embodiments, the second floating pin 421 may also be disposed at the end of the second driving chip 42 in the data transmission direction. In another embodiment, the image data may be transmitted from a side where the first driver chip 41 and the second driver chip 42 are close to each other to a side where the first driver chip 41 and the second driver chip 42 are far from each other.

Optionally, a second floating pin 421 is laid on the array substrate and connected to the auxiliary pixel unit 6 through a connection line 5. In general, the array substrate includes a display region and a non-display region, in the display region of the array substrate, black matrixes are disposed between the R, G, B three sub-pixels 7 of the color film substrate and in the non-display region to block the light source, and an edge of the black matrix disposed in the non-display region is generally aligned with the display region. In the design of the array substrate, the uniformity of various devices at the operation start end and the operation end is poor, and the uniformity at the working middle section is good, and in order to ensure the process uniformity of each Pixel unit in the display area, the auxiliary Pixel unit 6(Dummy Pixel) is usually arranged in the black matrix. The design of the auxiliary pixel cell 6 substantially corresponds to the pixel cell structure in the display area, but typically the TFT devices in the auxiliary pixel cell 6 are eliminated.

It can be understood that, since the auxiliary pixel unit 6 is originally present in the array substrate, and the auxiliary pixel unit 6 cannot be displayed in the display area, the second suspending pin 421 is connected with the auxiliary pixel unit 6 through the connecting line 5, so that the virtual signal inserted by the timing controller 3 can be the same as or similar to the image data, the operation difficulty of the timing controller 3 is simplified, the output of the virtual data is realized, meanwhile, the design difficulty of the array substrate can be reduced, the manufacture of the array substrate is facilitated, and the yield of the product is improved.

Specifically, in the present embodiment, the material and the forming manner of the connecting lines 5 are the same as those of the data lines 1, so that the manufacturing difficulty of the array substrate can be further reduced, and the method is suitable for mass production. In other embodiments, the connecting lines 5 may also be formed in other ways.

It should be noted that, in other embodiments of the present application, the second floating pin 421 may also be directly connected to the load, or may also be indirectly connected to the load through the connection line 5, as long as the load does not interfere and affect the display of the image on the array substrate, and for example, the load may be a resistor or the like.

It should be noted that, in some embodiments of the present application, the first floating pin may also be connected to the auxiliary pixel unit 6 through the connection line 5.

Referring to fig. 4, optionally, in an exemplary embodiment of the application, when 2052< N <3078, the source driving module 4 further includes a third driving chip 43, the third driving chip 43 is located between the first driving chip 41 and the second driving chip 42, the third driving chip 43 includes a third output pin and a third floating pin 431, the number of the third output pin is defined as x3, and the number of the third floating pin 431 is defined as y3, then

x1＝x2＝1026，

x3＝N-x1-x2，

(x3+y3)|2。

It should be noted that in the mathematical formula, the symbol "|" indicates that the integer division means that the sum of the numbers of the third output pins and the third floating pins 431 can be divided by 2, i.e., (x3+ y3) |2 ". Meanwhile, since the function of the third output pin is the same as that of the first output pin, and the function of the third floating pin 431 is the same as that of the first floating pin, the description thereof is omitted.

It can be understood that when 2052< N <3078, the array substrate needs to use three source driver chips to transmit data to the data lines 1, according to the Mini-LVDS transmission method, the data transmitted by the third driver chip 43 is equally divided into the left and right display areas of the array substrate, in order to avoid the loss of picture information during the transmission process, a certain number of third floating pins 431 may be disposed in the third driver chip 43, and similarly, when the timing controller 3 transmits image data to the source driver module 4, dummy data having the same number as the third floating pins 431 may be inserted and transmitted to the third floating pins 431 to balance the data output from the left and right sides of the third driver chip 43, so that the left and right sides of the third driver chip 43 can both transmit complete image data, and further avoid the loss of image data during the transmission process.

Specifically, as shown in fig. 4, at least 3 source driver chips are needed to control the data line 1 according to the conversion of the horizontal pixels of the array substrate. At this time, the number N of the data lines 1 laid on the array substrate is 1766 × 3/2 — 2649, and x1 is x2 — 1026, and the number y3 of the third floating pins 431 is 3, where x3 is N-x1-x2 is 2649 — 1026 — 597. Therefore, in the process of actually transmitting data, the image data received by the second driving chip 42 is 597/2 ═ 298.5, in order to avoid the loss of the image data in the transmission process, we insert 3 third floating pins 431 into the third driving chip 43, and at the same time, when the timing controller 3 is set to transmit the image data to the

third driving chip

43, 3 pieces of dummy data are inserted and transmitted to the 3 third floating pins 431 of the third driving chip 43, so that the image data transmitted on the left and right sides of the third driving chip 43 are balanced, and the loss of the image data is avoided, thereby implementing a dual-gate architecture.

It should be noted that, in the technical solution disclosed in the present application, the number of the third flying pins 431 is also not limited to 3, and may also be adaptively adjusted according to actual production applications.

It should be further noted that, in the embodiment of the present application where the third floating pin 431 is disposed, the third floating pin 431 may also be connected to the auxiliary pixel unit 6 through the connection line 5 or directly connected to the load, and obviously, the third floating pin 431 may also be disposed in the same manner as the first floating pin or the second floating pin 421, for example, a plurality of the third floating pins 431 are disposed in an adjacent manner.

The present invention further provides a display panel, which includes an array substrate, and the specific structure of the array substrate refers to the above embodiments, and since the display panel provided by the present invention adopts all technical solutions of all the above embodiments, the display panel at least has all the beneficial effects brought by the technical solutions of the above embodiments, and details are not repeated herein.

The present invention further provides a display device, which includes an array substrate, and the specific structure of the array substrate refers to the above embodiments, and since the display device provided by the present invention adopts all technical solutions of all the above embodiments, at least all the beneficial effects brought by the technical solutions of the above embodiments are achieved, and are not repeated herein.

The above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention, and all modifications and equivalents of the present invention, which are made by the contents of the present specification and the accompanying drawings, or directly/indirectly applied to other related technical fields, are included in the scope of the present invention.

Claims

1. An array substrate based on a dual gate line architecture, comprising:

a time schedule controller;

the data line is laid on the substrate, and N ∤ 6 is obtained when the number of the data lines is N; and

a source driving module connected between the timing controller and the substrate, the source driving module including a first driving chip and a second driving chip, the first driving chip including a first output pin and a first suspension pin, the second driving chip including a second output pin and a second suspension pin,

x1+x2=N；

x1+y1=x2+y2；

The time schedule controller inserts a certain part of virtual data into the first suspension pin and/or the second suspension pin in the image data transmitted to the source electrode driving module, so that the first driving chip and the second driving chip output the same amount of data, and all sub-pixels of any pixel of the array substrate are transmitted by the same bus of Mini-LVDS.

2. The array substrate of claim 1, wherein N =2049, x1=1026, and x2= 1023.

3. The array substrate of claim 2, wherein a plurality of the second flying leads are disposed adjacent to each other.

4. The array substrate of claim 2, wherein the second plurality of floating pins are disposed at one end of the second driver chip.

5. The array substrate of claim 4, wherein the transmission data of the timing controller is transmitted from the first driving chip to the second driving chip, and the second floating pin is disposed at one end of the second driving chip close to the first driving chip.

6. The array substrate of claim 1, wherein a connecting line is laid on the array substrate, and the second floating pin is connected to the auxiliary pixel unit through the connecting line.

7. The array substrate of claim 1, wherein the second flying lead is connected to a load.

8. A display panel comprising the array substrate according to any one of claims 1 to 7.

9. A display device comprising the array substrate according to any one of claims 1 to 7.