CN109631954B - Programmable linear Hall sensor chip structure for realizing on-chip temperature compensation function - Google Patents
Programmable linear Hall sensor chip structure for realizing on-chip temperature compensation function Download PDFInfo
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Abstract
The invention relates to a programmable linear Hall sensor chip structure for realizing on-chip temperature compensation function, which comprises a signal acquisition module, a signal processing module and a control module, wherein the signal acquisition module is used for generating a differential output current signal, converting the differential output current signal into a differential voltage signal, and amplifying and recovering the differential voltage signal; the filtering processing module is connected with the signal acquisition module and is used for performing first-order filtering and filtering signals of a specific frequency point and providing driving capability of Hall voltage output; and the signal processing module is connected with the signal acquisition module and the filtering processing module and is used for detecting the temperature, carrying out digital signal processing and providing clocks with different time sequences for each module. By adopting the chip structure, a more convenient and efficient gain adjustment scheme is provided, so that the programmable linear Hall can meet the client application with different sensitivity requirements, and meanwhile, the response time of the linear Hall is shortened, and the programmable linear Hall is more suitable for some application occasions with quick response. The temperature sensor and the digital compensation algorithm ensure the precision of the application and detection of the sensor.
Description
Technical Field
The invention relates to the field of sensors, in particular to the field of a quick-response current sensor, and specifically relates to a programmable linear Hall sensor chip structure for realizing an on-chip temperature compensation function.
Background
The linear hall sensor generally comprises a hall element, a hall signal amplifying and demodulating circuit, a driving circuit and the like. Its input is the magnetic field strength and its output is the voltage. Wherein the output voltage is proportional to the input magnetic field strength. Therefore, the sensor is called as a linear Hall sensor, and the circuit has the characteristics of high sensitivity, good linearity, small temperature drift, high reliability, high integration level, small chip area and the like.
According to the characteristics of the linear Hall sensor, the linear Hall sensor can be applied to the detection of various magnetic fields. In some applications, such as position sensors, proximity sensors, power supply sensing, current sensors, etc., are widely used. The sensitivity requirements of different applications on the linear hall sensor are inconsistent, so that the client needs to program the linear hall sensor, namely the programmable linear hall sensor adjusts the sensitivity of the linear hall sensor and indexes such as static output voltage through a built-in EEPROM or MTP and the like.
A typical application of the programmable linear hall in the current sensor is shown in fig. 1, and the current sensor module scheme shown in fig. 1 includes a conductor through which a current Ip to be detected flows; a Ring Concentrator (Ring Concentrator) is surrounded outside the conductor, and a linear Hall sensor chip (Hs) is placed at the opening of the Ring Concentrator and used for detecting the concentrated magnetic field intensity Bp. The magnetic field strength is proportional to the current Ip through the conductor. Meanwhile, the change of the current to be detected can be converted into the change of the output voltage of the linear Hall sensor by adjusting the sensitivity of the programmable linear Hall sensor, the static output voltage and other indexes, and the output voltage can be changed within a certain range.
Namely:
Vh＝Si×Ip+Vq；
where Vh is the voltage output of the programmable linear hall sensor. Si is the sensitivity of the current sensor, Ip is the current to be sensed, Vq is the static voltage output of the linear hall sensor when the current to be sensed is 0. Both Si and Vq can be adjusted by client programming according to application requirements.
The output voltage of the Hall element is amplified and demodulated, and then filtered to generate the output of the linear Hall sensor. The sensitivity is typically adjusted by adjusting the amplification of the front-end amplifier, such as adjusting the current, i.e., the transconductance (gm) of the input device. The temperature compensation is also typically done purely analog or by a D/a (digital to analog conversion). The traditional programmable linear Hall has the problems of low programming precision, high programming complexity and the like. For example, by adjusting the implementation of gm, gm itself is a parameter that varies with temperature, which makes temperature compensation more complicated and requires multiple segmented compensations to achieve the required accuracy. Either purely analog compensation or using D/a increases hardware complexity. And the common filtering mode can generate very large time delay, so that the response time of the programmable linear Hall becomes slow.
Disclosure of Invention
The invention aims to overcome the defects of the prior art and provides a programmable linear Hall sensor chip structure which has low hardware development cost, simple programming and small temperature drift and realizes the on-chip temperature compensation function.
In order to achieve the above object, the chip structure of the programmable linear hall sensor for realizing the on-chip temperature compensation function of the present invention is as follows:
the programmable linear Hall sensor chip structure for realizing the on-chip temperature compensation function is mainly characterized by comprising the following components in parts by weight:
the signal acquisition module is used for generating a differential output current signal, converting the differential output current signal into a differential voltage signal, and amplifying and recovering the differential voltage signal;
the filtering processing module is connected with the signal acquisition module and is used for performing first-order filtering and filtering signals of a specific frequency point and providing driving capability of Hall voltage output;
and the signal processing module is connected with the signal acquisition module and the filtering processing module and is used for detecting the temperature, carrying out digital signal processing and providing clocks with different time sequences for each module.
Preferably, the signal obtaining module includes:
the silicon Hall element array is connected with the signal processing module and is used for generating a pair of differential output current signals;
and the integrator is connected with the silicon Hall element array and the signal processing module and is used for integrating the differential current signals generated by the two Hall elements into differential voltage signals in a period.
Preferably, the signal acquisition module further comprises a voltage sampling amplification and signal rectification module, which is connected with the integrator and the signal processing module and is used for amplifying and recovering the hall voltage signal.
Preferably, the filtering processing module includes:
the anti-aliasing filter is connected with the voltage sampling amplification and signal rectification module and is used for performing first-order filtering and filtering signals above the Nyquist sampling frequency;
the self-adaptive frequency trap is connected with the anti-aliasing filter and the signal processing module and is used for filtering signals of specific frequency points;
and the driving module is connected with the adaptive frequency wave trap and used for providing the driving capability of Hall voltage output, finishing high-frequency filtering and adjusting static output voltage.
Preferably, the filtering processing module further comprises a reference voltage and current generating module, connected to the driving module and the signal processing module, for providing a reference voltage and a current for the chip.
Preferably, the signal processing module includes:
the digital processing module is connected with the silicon Hall element array, the integrator, the voltage sampling amplification and signal rectification module, the self-adaptive frequency trap and the reference voltage and current generation module and is used for carrying out digital signal processing and providing clocks with different time sequences for each analog module;
the clock oscillator is connected with the digital processing module and is used for providing a digital working clock for the digital processing module and providing a working clock with a specific time sequence for the self-adaptive frequency trap filter;
and the temperature sensor is connected with the digital processing module and used for detecting the temperature.
Preferably, the digital processing module comprises:
the first multiplication operation module is connected;
the second multiplication module is connected with the first multiplication module;
the first addition module is connected with the first multiplication operation module;
the second addition module is connected with the second multiplication operation module;
the first programmable module is connected with the first multiplication module and the second multiplication module;
the second programmable module is connected with the first adding module;
the third programmable module is connected with the second addition module;
the register module is connected with the first programmable module, the first adding module and the second adding module;
and the clock generation module is connected with the register module.
Preferably, the combination of the silicon hall element array is one hall element, two hall elements or four hall elements.
Preferably, the silicon hall element array comprises a first hall element and a second hall element, and the first hall element and the second hall element are connected with each other.
Preferably, the hall elements of the silicon hall element array are cross-shaped hall elements.
Preferably, the integrator includes an integrating capacitor, and two ends of the integrating capacitor are respectively connected to the silicon hall element array and the voltage sampling amplification and signal rectification module.
Preferably, the integrating capacitor changes the coarse adjustment digit and the fine adjustment digit according to the gear requirement of the application end and the requirement of the adjustment step length.
Preferably, the integrating capacitor is formed by connecting 8 binary weight capacitors in parallel and is controlled by 8 bits, and is used for realizing 8-bit fine adjustment.
By adopting the programmable linear Hall sensor chip structure for realizing the on-chip temperature compensation function, a more convenient and efficient gain adjustment scheme is provided, so that the programmable linear Hall sensor chip structure can meet the client application with different sensitivity requirements, and simultaneously, the response time of the linear Hall sensor chip is shortened, and the programmable linear Hall sensor chip structure is more suitable for some application occasions with quick response, such as the application of a current sensor. The temperature sensor and the digital compensation algorithm ensure that the sensitivity of the sensor and the static voltage output change very little with the temperature, thereby ensuring the precision of the application and the detection of the sensor.
Drawings
Fig. 1 shows a typical application of a programmable linear hall in a current sensor according to the prior art.
FIG. 2 is a schematic diagram of an overall circuit of a programmable linear Hall sensor chip structure implementing an on-chip temperature compensation function according to the present invention.
FIG. 3 is a schematic diagram of an embodiment of a Hall element array of a programmable linear Hall sensor chip structure implementing an on-chip temperature compensation function according to the present invention.
FIG. 4 is a schematic diagram of a signal acquisition module of the programmable linear Hall sensor chip structure implementing on-chip temperature compensation of the present invention.
FIG. 5 is a timing diagram of a Hall element operating clock of a programmable linear Hall sensor chip structure implementing on-chip temperature compensation in accordance with the present invention.
FIG. 6 is a schematic diagram of a filtering processing module of the chip structure of the programmable linear Hall sensor for implementing the on-chip temperature compensation function according to the present invention.
FIG. 7 is a schematic diagram of a signal processing module of the programmable linear Hall sensor chip architecture for implementing on-chip temperature compensation in accordance with the present invention.
Reference numerals:
100 silicon Hall element array
200 integrator
300 voltage sampling amplifying and signal rectifying module
400 anti-aliasing filter
500 adaptive frequency trap
600 drive module
700 reference voltage and current generation module
800 digital processing module
900 clock oscillator
1000 temperature sensor
810 first programmable module
820 second programmable module
830 third programmable module
840 first multiplication module
850 second multiplication module
860 first adding module
870 second summing module
880 register module
890 clock generating module
H1 first Hall element
H2 second Hall element
Detailed Description
In order to more clearly describe the technical contents of the present invention, the following further description is given in conjunction with specific embodiments.
The invention relates to a programmable linear Hall sensor chip structure for realizing on-chip temperature compensation function, wherein the chip structure comprises:
the silicon Hall element array 100 is connected with the signal processing module and is used for generating a pair of differential output current signals;
and the integrator 200 is connected with the silicon Hall element array 100 and the signal processing module and is used for integrating the differential current signals generated by the two Hall elements into differential voltage signals in a period.
As a preferred embodiment of the present invention, the signal acquiring module further includes a voltage sampling amplifying and signal rectifying module 300, which is connected to the integrator 200 and the signal processing module, and is used for amplifying and recovering the hall voltage signal.
As a preferred embodiment of the present invention, the filtering processing module includes:
the anti-aliasing filter 400 is connected with the voltage sampling amplification and signal rectification module 300 and is used for performing first-order filtering and filtering signals above the Nyquist sampling frequency;
the adaptive frequency trap 500 is connected with the anti-aliasing filter 400 and the signal processing module, and is used for filtering out signals of specific frequency points;
and the driving module 600 is connected with the adaptive frequency trap 500 and is used for providing the driving capability of hall voltage output, finishing high-frequency filtering and adjusting static output voltage.
As a preferred embodiment of the present invention, the filtering processing module further includes a reference voltage and current generating module 700, connected to the driving module 600 and the signal processing module, for providing a reference voltage and a current to the chip.
As a preferred embodiment of the present invention, the signal processing module includes:
a digital processing module 800, connected to the silicon hall element array 100, the integrator 200, the voltage sampling amplification and signal rectification module 300, the adaptive frequency trap 500 and the reference voltage and current generation module 700, for performing digital signal processing and providing clocks with different time sequences for each analog module;
a clock oscillator 900, connected to the digital processing module 800, for providing a digital working clock for the digital processing module 800 and providing a working clock with a specific timing sequence for the adaptive frequency trap 500;
and the temperature sensor 1000 is connected with the digital processing module 800 and is used for detecting temperature.
As a preferred embodiment of the present invention, the digital processing module 800 includes:
a first multiplication module 840 connected to the temperature sensor 1000;
a second multiplication module 850 connected to the temperature sensor 1000 and the first multiplication module 840;
a first addition module 860 connected to the first multiplication module 840;
a second adding module 870 connected to the second multiplying module 850;
a first programmable module 810 connected to the first multiplication module 840 and the second multiplication module 850;
a second programmable module 820, connected to the first adding module 860;
a third programmable module 830 coupled to said second summing module 870;
a register module 880, connected to the first programmable module 810, the first adding module 860 and the second adding module 870;
a clock generation module 890 connected to said register module 880.
In a preferred embodiment of the present invention, the combination of the silicon hall element array 100 is one hall element, two hall elements, or four hall elements.
As a preferred embodiment of the present invention, the silicon hall element array 100 includes a first hall element H1 and a second hall element H2, which are connected to each other.
In a preferred embodiment of the present invention, the hall elements of the silicon hall element array 100 are cross-shaped hall elements.
As a preferred embodiment of the present invention, the integrator 200 includes an integrating capacitor, and two ends of the integrating capacitor are respectively connected to the silicon hall element array 100 and the voltage sampling amplifying and signal rectifying module 300.
As a preferred embodiment of the invention, the integrating capacitor changes the coarse adjustment digit and the fine adjustment digit according to the gear requirement of an application end and the requirement of an adjustment step.
As a preferred embodiment of the invention, the integrating capacitor is composed of 8 binary weight capacitors in parallel and is controlled by 8 bits, and is used for realizing 8-bit fine adjustment.
In the embodiment of the invention, the device comprises a silicon Hall element array 100 which is composed of one, two or more Hall element arrays and generates a differential current signal which is in direct proportion to an external magnetic field; an integrator 200 for integrating the current signal into a voltage signal for a certain period of time; the voltage sampling amplification and signal rectification module 300 is used for amplifying and recovering a Hall voltage signal; the anti-aliasing filter 400 is used for avoiding the signal aliasing phenomenon of the subsequent sampling circuit after filtering; an adaptive frequency trap 500 for filtering a signal at a specific frequency point, wherein the specific frequency point is adaptive; the driving module 600 is configured to provide a driving capability of hall voltage output, and complete high-frequency filtering and static output voltage adjustment at the same time; a reference voltage and current generating module 700 for providing a reference voltage and current to the entire chip; the digital processing module 800 performs digital signal processing and provides clocks with different time sequences, namely a clock group CKA, a clock group CKB, a clock group CKC and a clock group CKD, for each analog module; a clock oscillator 900 providing a digital reference working clock CKREF for 800; and a temperature sensor 1000 for sensing temperature and providing a temperature compensation reference.
A silicon hall element array 100 composed of two hall element arrays; the two Hall elements work under different chopping clocks, and input signals are current signals and are used for generating a pair of differential output current signals.
An integrator 200 for integrating the differential current signals generated by the two hall elements into a differential voltage signal within a certain time period;
the voltage sampling amplification and signal rectification module 300 is used for further amplifying and recovering the Hall voltage signal;
the anti-aliasing filter 400 is used for performing first-order filtering, filtering out signals above the Nyquist sampling frequency and avoiding the signal aliasing phenomenon of a subsequent sampling circuit;
the adaptive frequency trap 500 is used for filtering a signal of a specific frequency point, and the specific frequency point can be adaptive and changes along with the change of a sampling clock;
the driving module 600 is configured to provide a driving capability of hall voltage output, and simultaneously perform functions of high-frequency filtering and static output voltage adjustment;
a reference voltage and current generating module 700 for providing a reference voltage and current to the entire chip;
a digital processing module 800, which performs digital signal processing and provides clocks of different timing sequences to the various analog modules, embeds a Multiple Time Programmable (MTP) memory module, which, in conjunction with the temperature compensation algorithm of the present invention, provides for sensitivity and static output voltage adjustment and temperature correction at the end of the production line, such as at the time of final test and at the time of client application.
A clock oscillator 900 for providing a digital operation clock for 800 and an operation clock with a specific timing sequence for the adaptive frequency trap 500;
and a temperature sensor 1000 for detecting temperature, the output of which is a set of digital signals, which are input to the digital processing module 800, and which, in combination with a built-in temperature calibration algorithm, provide temperature compensation for the sensitivity and the static output voltage.
The technical solution in the embodiments of the present invention is clearly and completely described below with reference to the drawings in the embodiments of the present invention.
The silicon Hall element array 100 is used to generate a pair of differential Hall current signals proportional to an external magnetic field. The silicon Hall element array can adopt one, two or four combinations, and the embodiment comprises two Hall element arrays H1 and H2. As shown in fig. 3, the hall element is a cross hall, and has four ports, i.e., C1, C2, C3, and C4, respectively, and the hall element operates at a chopping frequency, and four-phase chopping clocks, i.e., CK1, CK2, CK3, and CK4, respectively. Taking one hall element H1 of the two hall elements H1, H2 as an example, when the CK1 is active at high level, corresponding to the working state of 1, i.e., C1, C4 are used as input terminals of the reference current Ibias, and C2, C3 are used as output terminals of the differential current outputs In and Ip. By analogy, when CK2 is active high, it corresponds to operating state 2, when CK3 is active high, it corresponds to operating state 3, and when CK4 is active high, it corresponds to operating state 4. That is, the operating state 1234 switch of H1 is clockwise. The other hall element H2 is switched to the opposite operating state, i.e., when CK1 is at a high level, it corresponds to operating state 3, when CK2 is at a high level, it corresponds to operating state 2, when CK3 is at a high level, it corresponds to operating state 1, and when CK4 is at a high level, it corresponds to operating state 4. That is, the switching of the operating state of H2 from (3), (2), (1) to 4 is a counter-clock reversal.
The two hall devices H1, H2 operating on the four-phase chopper clock are then connected as shown in fig. 4. The timing sequence of the operating clock is shown in fig. 5, when CKr is at a high level, two ends of the adjustable integrating capacitor Cin are short-circuited by the switch, and the reset operation is performed. When CKi is high, the integrator starts integrating for 4 t. In the integration period, CK1, CK2, CK3 and CK4 are used as four-phase chopping operation clocks of the double-hall H1 and H2, are respectively alternated to a high level, the time length of the high level is t, and differential current signals Iop and Ion are output. The two paths of differential current signals Iop and Ion are sent to the integrator 200, and output signals Vop1 and Von1 after the integration time length of 4 t. When CKs is at high level, the voltage sampling amplifying and signal rectifying module 300 samples and rectifies the output signals Vop1, Von1 of the voltage sampling amplifying and signal rectifying module 200 to output the signals Vop2 and Von 2.
Iop－Ion＝2×Ihall；
Vop1－Von1＝(Iop－Ion)×Cint×(4t)；
That is, Vop 1-Von 1 ═ 8 × Ihall × Cint × t;
wherein Ihall is a Hall current signal generated by a Hall element, Cint is an integral capacitor, and t is an integral time parameter. According to the formula, the gain of the Hall signal amplification link is adjusted by adjusting the integration time parameter t and the value of the adjustable integration capacitor Cint, and the sensitivity of the linear Hall sensor is also adjusted. According to the scheme, the t is controlled by two bits, two-bit coarse adjustment is realized, and the t corresponds to four gears of the application end with different sensitivity requirements on the linear Hall. Cint is controlled by 8 bits and is formed by connecting 8 binary weight capacitors in parallel, and 8-bit fine adjustment is realized. Of course, the number of coarse adjustment bits and the number of fine adjustment bits may be changed according to the gear requirement of the application end and the requirement of the adjustment step. The scheme is only one of the implementation cases.
Vop2 and Von2 are firstly used as the input of the anti-aliasing filter 400 to filter the frequency part above the nyquist frequency of the subsequent adaptive frequency trap 500, so as to avoid the aliasing phenomenon in the sampling process. The outputs Vop3 and Von3 of the anti-aliasing filter 400 are used as input signals of the adaptive frequency trap 500, the adaptive frequency trap 500 is implemented by taking an average after multiple sampling, the sampling frequency is a multiple of CKs, the frequency of the average operation is CKs, the first notch frequency point is CKs, the specific implementation can take the sampling frequency of the adaptive frequency trap 500 as 2 × CKs, the bandwidth of the anti-aliasing filter 400 is the frequency of CKs, and the notch frequency point is an integral multiple of CKs. And an anti-aliasing filter and a wave trap are adopted for filtering, so that the response time of the linear Hall is greatly shortened.
As shown in fig. 6, the output signals Vop4 and Von4 of the adaptive frequency trap 500 are used as the input of the driving module 600, and the driving module 600 filters the high frequency signal while realizing the function of converting the differential signal into the single-ended output. The Voff is inputted to the other end of the driving module 600 and provided by the reference voltage and current generating module 700. In this embodiment Voff is defined by the number of 8 bits Cbits < 7: 0>, and other numbers of bits can be adopted to realize the control in practical application and realization according to the requirements of adjustment precision and range.
As shown in fig. 7, the clock oscillator 900 provides a digital reference clock CKREF for the digital processing module 800, the clock of the clock oscillator is a clock reference source close to zero temperature coefficient, and the frequency of the clock oscillator in this embodiment is determined by the PTAT current directly proportional to the temperature and the charge and discharge voltage related to the negative temperature coefficient mobility. Namely, it is
Where f is the oscillator clock frequency, I is the PTAT current, and μ is the mobility.
The temperature sensor 1000 is used for detecting the ambient temperature of the chip, and outputting an 8-bit digital code x as the difference between the actual temperature and the room temperature.
x＝Ta－T0；
Where Ta is the detected actual operating temperature of the chip and T0 is room temperature. x is the difference between the actual temperature and the room temperature, which is used as an input to the digital processing module 800.
The digital processing module 800 comprises three multi-time programmable modules MTP0810, MTP1820, MTP2830, two multiplication modules MATH1840, MATH2850, two addition modules addrer 1860, addr 2870, and a register module 880, a clock generation module 890.
The MTP0 is used to store parameters a1, a2, b1, b2, Tsel < 1: 0 >.
Wherein a1 is the sensitivity temperature coefficient, b1 is the sensitivity configuration target value at room temperature, a2 is the static output voltage temperature coefficient, and b2 is the static output voltage configuration target value at room temperature. a1, a2 can be obtained by testing different sensitivity and static output voltages at high temperature and room temperature. Tsel < 1: 0> is used to achieve coarse tuning of the sensitivity.
The MPT1820 and the MTP2830 are respectively used for storing 8-bit digital codes and are provided for clients to use in client programming of sensitivity and static output voltage.
The first multiplication module (MATH1)840 and the second multiplication module (MATH2)850 respectively perform multiplication operations of a1 × x + b1 and a2 × x + b2, and realize first-order temperature correction of sensitivity and static output voltage.
The outputs of the first multiplication module 840 and the second programmable module 820 are input to the first addition module 860 for addition and then stored in the register module 880, which generates a result of Cintc < 7: 0> is used to control the value of the integrating capacitor Cint of the integrator 200, enabling fine tuning of the sensitivity.
The outputs of the second multiply module 850, the third programmable module and 830 are fed to the second add module 870 for addition and then stored in the register module 880, which generates a bit < 7: 0> is used to control the output value Voff of the voltage and current generation module 700, which implements the regulation of the static output voltage.
The other two-bit output of register module 880, Tsela < 1: 0> is used as the input of the clock generation module 890 to perform coarse adjustment of the sensitivity, that is, the requirements of the application on different sensitivity gears are realized by adjusting the integration time t of the integrator 200.
The clock generation module 890 has as its input the output CLKREF of the clock oscillator 900, and the clock generation module 890 outputs four clock signal groups CKA, CKB, CKC, CKD, respectively.
The clock group CKA includes CK1, CK2, CK3 and CK4, and is used as a four-phase clock for the silicon hall element array 100.
The clock group CKB includes CKi and CKr, which are used as the operating clocks of the integrator 200.
The clock group CKC includes CKs and corresponding non-overlapping clocks as working clocks of the voltage sampling, amplifying and signal rectifying module 300.
The CKD includes CK11, CK12, CKa, CKs1, etc. as the operating clock of the adaptive frequency trap 500.
In the scheme, the digital part is directly used for programming the client and adding or subtracting the temperature calibration to control the sensitivity of the analog part and the adjustment of the static output voltage, so that the design method is simplified.
And (3) correcting the sensitivity temperature, and realizing coarse adjustment by controlling the integration time t through two digits of a digital part, wherein the coarse adjustment corresponds to different gears of the sensitivity of the application terminal. The value of the integrating capacitor Cint is adjusted through eight digital control bits, and fine adjustment is performed in the same sensitivity gear. Neither the adjusted parameters t nor Cint substantially change with temperature. Most of the traditional ways of fine and coarse adjustment of sensitivity are accomplished by adjusting current, namely transconductance gm, and output impedance R of an amplifier, and the value of the current, namely transconductance gm, has a temperature drift characteristic. The temperature compensation becomes more complex, and higher precision can be achieved by temperature sectional compensation basically. In the scheme, the parameters t and Cint of the coarse adjustment and the fine adjustment can be ignored for the change of the temperature. The digital part can reach the same precision by adopting first-order compensation, and the hardware design and the programming mode are greatly simplified.
The programmable linear Hall sensor chip structure for realizing the on-chip temperature compensation function provides a more convenient and efficient gain adjustment scheme, so that the programmable linear Hall sensor chip structure can meet the client application with different sensitivity requirements, and simultaneously quickens the response time of the linear Hall sensor, thereby being more suitable for some application occasions with quick response, such as the application of a current sensor. The temperature sensor and the digital compensation algorithm ensure that the sensitivity of the sensor and the static voltage output change very little with the temperature, thereby ensuring the precision of the application and the detection of the sensor.
In this specification, the invention has been described with reference to specific embodiments thereof. It will, however, be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the invention. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.
Claims (12)
1. A programmable linear Hall sensor chip structure for realizing on-chip temperature compensation function is characterized in that the chip structure comprises:
the signal acquisition module is used for generating a differential output current signal, converting the differential output current signal into a differential voltage signal, and amplifying and recovering the differential voltage signal;
the filtering processing module is connected with the signal acquisition module and is used for performing first-order filtering and filtering signals of a specific frequency point and providing driving capability of Hall voltage output;
the signal processing module is connected with the signal acquisition module and the filtering processing module and is used for detecting temperature, carrying out digital signal processing and providing clocks with different time sequences for each module;
the signal acquisition module comprises:
the silicon Hall element array (100) is connected with the signal processing module and is used for generating a pair of differential output current signals;
and the integrator (200) is connected with the silicon Hall element array (100) and the signal processing module and is used for integrating the differential current signals generated by the two Hall elements into differential voltage signals in a period.
2. The chip architecture of the programmable linear hall sensor for implementing on-chip temperature compensation according to claim 1, wherein the signal acquisition module further comprises a voltage sampling amplification and signal rectification module (300) connected to the integrator (200) and the signal processing module for amplifying and recovering the hall voltage signal.
3. The programmable linear hall sensor chip architecture for implementing on-chip temperature compensation of claim 2 wherein said filtering processing module comprises:
the anti-aliasing filter (400) is connected with the voltage sampling amplification and signal rectification module (300) and is used for performing first-order filtering and filtering signals above the Nyquist sampling frequency;
the adaptive frequency trap (500) is connected with the anti-aliasing filter (400) and the signal processing module and is used for filtering signals of specific frequency points;
and the driving module (600) is connected with the adaptive frequency trap (500) and is used for providing the driving capability of Hall voltage output, finishing high-frequency filtering and adjusting static output voltage.
4. The chip architecture of the programmable linear hall sensor for implementing on-chip temperature compensation of claim 3 wherein said filtering processing module further comprises a reference voltage and current generating module (700) connected to said driving module (600) and said signal processing module for providing a reference voltage and current to the chip.
5. The programmable linear hall sensor chip architecture for implementing on-chip temperature compensation function according to any of claims 2 or 4, characterized in that the signal processing module comprises:
the digital processing module (800) is connected with the silicon Hall element array (100), the integrator (200), the voltage sampling amplification and signal rectification module (300), the adaptive frequency trap (500) and the reference voltage and current generation module (700) and is used for carrying out digital signal processing and providing clocks with different time sequences for each analog module;
the clock oscillator (900) is connected with the digital processing module (800) and is used for providing a digital working clock for the digital processing module (800) and providing a working clock with a specific time sequence for the adaptive frequency trap (500);
and the temperature sensor (1000) is connected with the digital processing module (800) and is used for detecting the temperature.
6. The programmable linear hall sensor chip architecture for implementing an on-chip temperature compensation function according to claim 5, characterized in that said digital processing module (800) comprises:
a first multiplication module (840) connected to the temperature sensor (1000);
the second multiplication module (850) is connected with the temperature sensor (1000) and the first multiplication module (840);
a first addition module (860) coupled to the first multiplication module (840);
a second addition module (870) coupled to said second multiplication module (850);
a first programmable module (810) connected to said first multiplication module (840) and said second multiplication module (850);
a second programmable module (820) coupled to said first summing module (860);
-a third programmable module (830) connected to said second adding module (870);
a register module (880) coupled to said first programmable module (810), said first summing module (860), and said second summing module (870);
and the clock generation module (890) is connected with the register module (880).
7. The programmable linear hall sensor chip architecture for implementing on-chip temperature compensation of claim 1 wherein the combination of the silicon hall element array (100) is one hall element, two hall elements or four hall elements.
8. The chip structure of programmable linear hall sensor for implementing on-chip temperature compensation of claim 1 wherein the array of silicon hall elements (100) comprises a first hall element (H1) and a second hall element (H2) and are connected to each other.
9. The programmable linear hall sensor chip architecture for implementing on-chip temperature compensation of claim 1 wherein the hall elements of the silicon hall element array (100) are cross hall elements.
10. The chip architecture of the programmable linear hall sensor for implementing on-chip temperature compensation according to claim 2, wherein the integrator (200) comprises an integrating capacitor, and both ends of the integrating capacitor are respectively connected to the silicon hall element array (100) and the voltage sampling amplification and signal rectification module (300).
11. The chip structure of the programmable linear hall sensor for realizing the on-chip temperature compensation function according to claim 10, wherein the integrating capacitor changes the coarse adjustment digits and the fine adjustment digits according to the gear requirement of the application end and the requirement of the adjustment step length.
12. The chip structure of the programmable linear hall sensor for realizing the on-chip temperature compensation function according to claim 10, wherein the integrating capacitor is composed of 8 binary weight capacitors connected in parallel and controlled by 8 bits for realizing 8-bit fine adjustment.
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| CN113029207B (en) * | 2021-03-17 | 2022-06-28 | 上海睿奈电子科技有限公司 | High-sensitivity and configurable sensor driving and signal processing integrated circuit |
| CN113485510A (en) * | 2021-07-09 | 2021-10-08 | 绍兴光大芯业微电子有限公司 | System for realizing time-sharing work of vertical Hall sensor |
| CN113703512B (en) * | 2021-11-01 | 2022-03-08 | 宁波中车时代传感技术有限公司 | Hall sensor temperature compensation circuit and compensation method thereof |
| CN115855122B (en) * | 2022-11-21 | 2025-04-04 | 珠海多创科技有限公司 | A method, device and electronic device for temperature compensation of sensor chip |
| CN115752549A (en) * | 2022-12-07 | 2023-03-07 | 赛卓电子科技(上海)股份有限公司 | Compensation circuit of magnetic sensor and vehicle system |
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