CN109616446A

CN109616446A - Manufacturing method of semiconductor device

Info

Publication number: CN109616446A
Application number: CN201811502331.XA
Authority: CN
Inventors: 汤茂亮; 王阳阳; 刘少东
Original assignee: Huaian Imaging Device Manufacturer Corp
Current assignee: Huaian Imaging Device Manufacturer Corp
Priority date: 2018-12-10
Filing date: 2018-12-10
Publication date: 2019-04-12

Abstract

This disclosure relates to a kind of manufacturing method of semiconductor device, comprising: form first groove in the substrate, the first groove is used to be isolated the active area of the transistor of the first kind；The first insulation filler is formed in the first groove, first filler is configured as applying stress to adjacent active area；Second groove is formed in the substrate, and the second groove is used to be isolated the active area of the transistor of Second Type；The second insulation filler is formed in the second groove, second filler is configured as applying stress to adjacent active area.

Description

The manufacturing method of semiconductor device

Technical field

This disclosure relates to the manufacturing method of semiconductor device.

Background technique

In semiconductor field, it is usually desirable to introduce stress, Lai Tigao carrier mobility to MOS transistor.However, existing There are the complex process for introducing stress in technology to MOS transistor, poor compatibility, manufacturing cost significantly improves.

Accordingly, there exist the needs to improved manufacturing method.

Summary of the invention

On one side according to the disclosure, a kind of manufacturing method of semiconductor device is provided, comprising: form the in the substrate One groove, the first groove are used to be isolated the active area of the transistor of the first kind；First is formed in the first groove Insulation filler, first filler are configured as applying stress to adjacent active area；Second is formed in the substrate Groove, the second groove are used to be isolated the active area of the transistor of Second Type；Second is formed in the second groove absolutely Edge filler, second filler are configured as applying stress to adjacent active area.

In some embodiments, the transistor of the first kind is PMOS transistor, the transistor of the Second Type It is NMOS transistor, wherein forming the first filler in the first groove includes: by high aspect ratio plasma (HARP) Depositing operation forms the oxide of silicon over the substrate, and the oxide for being formed by silicon at least fills the first groove；With And processing is removed to the oxide of the silicon, to retain the oxide for the silicon being filled in the first groove.

In some embodiments, the second filler is formed in the second groove includes: to pass through high-density plasma (HDP) depositing operation forms the oxide of silicon over the substrate, and the oxide for being formed by silicon at least fills described second Groove；And processing is removed to the oxide of the silicon, to retain the oxide for the silicon being filled in the second groove.

In some embodiments, the transistor of the first kind is NMOS transistor, the transistor of the Second Type It is PMOS transistor, wherein forming the first filler in the first groove includes: to be deposited by high-density plasma (HDP) Technique forms the oxide of silicon over the substrate, and the oxide for being formed by silicon at least fills the first groove；And Processing is removed to the oxide of the silicon, to retain the oxide for the silicon being filled in the first groove.

In some embodiments, it includes: by high aspect ratio plasma that the second filler is formed in the second groove (HARP) depositing operation forms the oxide of silicon over the substrate, and the oxide for being formed by silicon at least fills second ditch Slot；And processing is removed to the oxide of the silicon, to retain the oxide for the silicon being filled in the second groove.

In some embodiments, the substrate includes silicon substrate.

In some embodiments, the active area of the first transistor is arranged between two first grooves, described The active area of second transistor is arranged between two second grooves.

In some embodiments, in the substrate formed first groove include: formed over the substrate it is patterned Mask；The substrate is etched using the mask, to form the first groove.

In some embodiments, in the substrate formed second groove include: formed over the substrate it is patterned Mask；The substrate is etched using the mask, to form the second groove.

In some embodiments, the method also includes: over the substrate formed for the first transistor grid it is exhausted Edge layer and the grid on gate insulating layer and the grid for the gate insulating layer of second transistor and on gate insulating layer Pole；It is formed in the substrate for the source region of the first transistor and drain region and source region and drain region for second transistor.

Detailed description of the invention

Attached drawing forms part of this specification, and which depict the exemplary embodiments of the disclosure, and together with specification Principle for explaining the present invention together, in the accompanying drawings:

Figure 1A and 1B schematically shows stress side desired for the semiconductor device of such as NFET and PFET etc To；

Fig. 2A -2I shows the portion of the part steps of the production method of the semiconductor device according to some embodiments of the disclosure Divide schematic section；

Fig. 3 shows the partial schematic cross-section of the semiconductor device according to some embodiments of the disclosure；And

Fig. 4 shows the partial section view of the semiconductor device according to some embodiments of the disclosure.

Note that same appended drawing reference is used in conjunction between different attached drawings sometimes in embodiments described below It indicates same section or part with the same function, and omits its repeated explanation.In the present specification, using similar mark Number and letter indicate similar terms, therefore, once being defined in a certain Xiang Yi attached drawing, then do not needed in subsequent attached drawing pair It is further discussed.

In order to make it easy to understand, position, size and range of each structure shown in attached drawing etc. etc. do not indicate practical sometimes Position, size and range etc..Therefore, disclosed invention is not limited to position, size and range disclosed in attached drawing etc. etc..

Specific embodiment

Describe the specific embodiment of the disclosure in detail below in conjunction with attached drawing.It should be understood that only to the description of embodiment It is illustrative, is not the limitation to the application invention claimed in any sense.Unless otherwise expressly specified Either context or its principle are expressed or are implied, positioned opposite, the expression formula of component and step in the exemplary embodiment With numerical value etc. not as the limitation to the claimed invention of the application.In the present specification, for related fields ordinary skill Technology, method and apparatus known to personnel may be not discussed in detail, but in the appropriate case, the technology, method and apparatus It should be considered as part of specification.

Term used herein, it is only for description specific embodiment, and it is not intended to limit the disclosure.It should be understood that , one word of "comprises/comprising" as used herein, illustrates that there are pointed feature, entirety, step, operation, units And/or component, but it is not excluded that in the presence of or increase one or more of the other feature, entirety, step, operation, unit and/or group Part and/or their combination.

In the word "front", "rear" in specification and claim, "top", "bottom", " on ", " under " etc., if deposited If, it is not necessarily used to describe constant relative position for descriptive purposes.It should be appreciated that the word used in this way Language be in appropriate circumstances it is interchangeable so that the embodiment of the present invention described herein, for example, can in this institute It is operated in those of description show or other other different orientations of orientation.

In the disclosure, therefore term " offer " " it is right to provide certain from broadly by covering all modes for obtaining object As " including but not limited to " purchase ", " preparation/manufacture ", " arrangement/setting ", " installation/assembly ", and/or " order " object etc..

In the disclosure, the ordinal number of " first ", " second ", " third " etc. is obscuring in order to avoid constituent element And mark, rather than in any way on order of priority.

In the context of the disclosure, semiconductor device means such device: at least part of the device includes benefit Element, device, component, component or the constituting portion that principle being formed with semiconductor material or using semiconductor field is operated Point etc..

Fig. 1 schematically shows stress direction desired for the semiconductor device of such as NFET and PFET etc.It is right In NMOS transistor, it is generally desirable to which the direction (in-plain) introduces tensile stress (tensile in face in its active area Stress), to improve carrier mobility.Further, it is desired in antarafacial (out-of- in the channel region in its active area Plain) direction introduces compression (compressive stress), and similarly, this can also be improved carrier mobility.

Accordingly, for PMOS transistor, it is generally desirable to which the direction (in-plain) introduces pressure in face in its active area Stress, to improve carrier mobility.Further, it is desired to which the antarafacial direction (out-of-plain) in its active area introduces and opens Stress, similarly, this can also be improved carrier mobility.

Here, in the face direction may include with substantially coplanar or parallel (or the and grid in the upper surface of channel region Lower surface it is substantially parallel) face in direction, for example, X-direction and Y-direction as shown in Figure 1A and 1B.The antarafacial side To including the direction for intersecting (for example, substantially vertical) with the upper surface of active area (or channel region), for example, as in Figure 1A and 1B Shown in Z-direction.

Stress will lead to the compression of the lattice dot matrix of substrate (for example, substrate of the semiconductor of such as silicon) (compression) or (expansion) is expanded, changed so as to cause the mobility of carrier.

However, foregoing, the process flow in the prior art for improving carrier mobility is complicated, and manufacturing cost It is higher.

Present inventor proposes the invention of the disclosure after in-depth study, the simplified, Cheng Benjie with technique Mode about introduces stress in semiconductor devices.

According to some embodiments of the present disclosure, a kind of manufacturing method of semiconductor device is provided.Below with reference to Fig. 2A -2I The step of this method, is described in detail.Fig. 2A -2I shows the production side of the semiconductor device according to the embodiment of the present disclosure The partial schematic cross-section of the part steps of method.

As shown in Figure 2 A, substrate 101 is provided.According to different embodiments, substrate 101 can be different types of substrate. Such as substrate 101 can be body (bulk) semiconductor substrate, or can be including basal layer and in substrate into upper semiconductor The substrate of layer, such as SOI substrate etc..Substrate 101 may include the semiconductor layer formed by any semiconductor material, such as but not It is limited to: element semiconductor, such as silicon, germanium etc.；Or compound semiconductor layer, such as II-IV race semiconductor or iii-v partly lead Body, oxide semiconductor etc..

As shown in Figure 2 B, first groove 202 is formed in substrate 101.In some embodiments, first groove 202 can be with For isolating device, such as the active area of the transistor of the first kind is isolated.Here the transistor of the first kind can be N-type crystalline substance Body pipe or P-type transistor.In some embodiments, forming first groove in the substrate may include: over the substrate Form patterned mask (not shown)；And the substrate is etched using the mask, to form described One groove.

As shown in Figure 2 C, the first insulation filler 103 is formed in the first groove 202.First filler 103 is matched Stress can be applied to active area adjacent thereto by being set to.First insulation filler 103 is also used to isolating device.In the first insulation Filler 103 is used for the feelings of isolating n-type transistor (that is, the first insulation filler 103 is adjacent with the active area of N-type transistor) Under condition, the first filler 103 can be configured to that the active area of N-type transistor adjacent thereto can be applied (or causing) and answer Power.In the first insulation filler 103 for isolated p transistor (that is, the first insulation filler 103 and P-type transistor has Source region is adjacent) in the case where, the first filler 103 can be configured to that the active area of P-type transistor adjacent thereto can be applied Add (or causing) compression.

In certain embodiments, the case where the transistor of the first kind is p-type (for example, PMOS) transistor Under, the first filler can be formed in the first groove in the following way.Firstly, passing through high aspect ratio plasma (HARP) depositing operation forms the oxide of silicon over the substrate, and the oxide for being formed by silicon at least fills first ditch Slot.Later, processing is removed to the oxide of the silicon, to retain the oxide for the silicon being filled in the first groove. To form the first filler 103.First filler 103 can be formed by the oxidation of silicon.

In certain embodiments, in the case where the transistor of the first kind is NMOS transistor, Ke Yitong It crosses under type such as and forms the first filler in the first groove.Firstly, by high-density plasma (HDP) depositing operation come The oxide for forming silicon over the substrate, the oxide for being formed by silicon fill the first groove.Later, to the silicon Oxide is removed processing, to retain the oxide for the silicon being filled in the first groove.

Here, it should be noted that present inventor is largely studied and tested discovery, passes through high aspect ratio etc. (such as STI) is isolated to be formed in ion (HARP) depositing operation, and the stress of desired type can be introduced to P-type transistor；In addition, Isolation (such as STI) is formed by high-density plasma (HDP) depositing operation, desired type can be introduced to N-type transistor Stress.Present inventor also found, the stress introduced through the above way, as the characteristic size of manufacturing process subtracts It is small and become readily apparent from, so that it can be utilized to introduce stress for semiconductor devices (such as transistor).As One unrestricted example can be through the above way with the characteristic size reduction of manufacturing process close to 90nm node Apparent stress is introduced in the devices.Here, it will be appreciated that the size node is merely possible to example, the disclosure is not limited to this.

Later, as shown in Figure 2 D, second groove 204 is formed in the substrate.Second groove 202 can be used for isolator Part, such as the active area of the transistor of Second Type is isolated.Here the transistor of Second Type can be N-type transistor or p-type Transistor.In some embodiments, forming second groove in the substrate includes: to form patterned cover over the substrate Mould (not shown)；And the substrate is etched using the mask, to form the second groove.

Later, as shown in Figure 2 E, the second insulation filler 103 is formed in the second groove 202.Second filler 105 are configured to apply stress to active area adjacent thereto.Second insulation filler 105 is also used to isolating device.? Second insulation filler 105 is for isolating n-type transistor (that is, the active area of the second insulation filler 105 and N-type transistor It is adjacent) in the case where, the second filler 105 can be configured to that the active area of N-type transistor adjacent thereto can be applied (or Cause) tensile stress.In the second insulation filler 105 for isolated p transistor (that is, the second insulation filler 105 and p-type The active area of transistor is adjacent) in the case where, the second filler 105 can be configured to can be to P-type transistor adjacent thereto Active area apply (or causing) compression.

In certain embodiments, the case where the transistor of the Second Type is p-type (for example, PMOS) transistor Under, the second filler can be formed in the second groove in the following way.Firstly, passing through high aspect ratio plasma (HARP) depositing operation forms the oxide of silicon over the substrate, and the oxide for being formed by silicon at least fills second ditch Slot.Later, processing is removed to the oxide of the silicon, to retain the oxide for the silicon being filled in the second groove. To form the second filler 105.Second filler 105 can be formed by the oxidation of silicon.

In certain embodiments, in the case where the transistor of the Second Type is NMOS transistor, Ke Yitong It crosses under type such as and forms the second filler in the second groove.Firstly, by high-density plasma (HDP) depositing operation come The oxide for forming silicon over the substrate, the oxide for being formed by silicon fill the second groove.Later, to the silicon Oxide is removed processing, to retain the oxide for the silicon being filled in the second groove.

High aspect ratio plasma (HARP) depositing operation and high-density plasma (HDP) depositing operation can use ability Known technique in domain.Therefore, no longer its details is further discussed here.

Later, can come on the basis of foring the substrate of the first filler and the second filler making devices (for example, Transistor).

It is alternatively possible to form the well region for being used for device in the substrate.As illustrated in Figure 3 F, it is formed in the substrate and is used for N-type The well region 104 of transistor.And the well region 106 for being used for P-type transistor is formed in the substrate.It should be readily apparent to one skilled in the art that Well region can be formed in the substrate for example, by Plasma inpouring technique.Therefore, no longer its details is carried out here further It discusses.

In addition, although showing the well region 104 of N-type transistor in fig. 2f and for 106 liang of well region of P-type transistor Person, however the person skilled in the art will easily understand can only form one of them, or both all according to different applications It is not formed.

Later, the gate structure for transistor is formed on the substrate, may include gate insulating layer and exhausted in grid Grid in edge layer.As shown in Figure 3 G, the gate insulating layer of the first kind (such as N-type) transistor can be formed on the substrate 107 and grid 108, and it is used for the gate insulating layer 109 and grid 110 of Second Type (such as p-type) transistor.

Later, the separator (spacer) for being used for gate structure is formed.As shown in figure 3h, on substrate, in gate structure Side formed be used for respective transistor separator 206 and 208.

Later, source region and drain region can be formed for example, by self aligned mode.As shown in fig. 31, by self aligned Mode carries out ion implanting, to form the source/drain region 111 and 113 of respective transistor.To form transistor.In figure only Schematically illustrate two transistors and its forming process；It should be understood that the disclosure is not limited to this.

It should be understood that Fig. 2 G-2I is only to show a kind of illustrative method for forming transistor device, the present invention is not It is limited to example.Those skilled in the art will become apparent from, and can be based on using the method for the diversified known or following exploitation Shown in substrate formed device.

As illustrated in the drawing, in some embodiments, the active area of shown first kind transistor (the first transistor) can To be arranged between two first grooves.The active area of the transistor (second transistor) of shown Second Type can be set Between two second grooves.

Fig. 3 shows the partial schematic cross-section of the semiconductor device according to some embodiments of the disclosure.Shown in Fig. 3 half The structure of conductor device is substantially identical as shown in Fig. 2 I, and one of difference is, some doping are schematically illustrated in Fig. 3 The type in area.Similarly or adaptively it can be applied to this with regard to Fig. 2A -2I explanation carried out above.Therefore, here not Repeated explanation is carried out again.

As shown in figure 3, the well region 104 of the transistor (that is, transistor on the left of in figure) of the first conduction type is N-type, Its source region and drain region are p-types.P+ type shown in figure indicates that the conduction type of the doped region is p-type, but doping concentration is opposite It is higher.The well region 104 of the transistor (that is, transistor on the right side of in figure) of second conduction type is p-type, and source region and drain region are N-type.N+ type shown in figure indicates that the conduction type of the doped region is p-type, but doping concentration is relatively high.

Fig. 4 shows the partial section view of the semiconductor device according to some embodiments of the disclosure.Semiconductor shown in Fig. 4 Substantially with Fig. 2 I and shown in Fig. 3 identical, one of difference is the structure of device, is illustrated only in Fig. 4 for a seed type Transistor well region.Similarly or adaptively it can be applied to this with regard to Fig. 2A -2I and Fig. 3 explanation carried out above. Therefore, repeated explanation is no longer carried out here.

The various embodiments of the disclosure are described above, but above description is only exemplary, and exhaustive Property, and present invention is also not necessarily limited to disclosed various embodiments.

It should be understood that the boundary between aforesaid operations is merely illustrative.Multiple operations can be combined into single operation, Single operation can be distributed in additional operation, and operated and can at least partially overlappingly be executed in time.Moreover, another The embodiment of choosing may include multiple examples of specific operation, and can change operation order in other various embodiments. But others are modified, variations and alternatives are equally possible.Therefore, the specification and drawings should be counted as illustrative , and not restrictive.

Under appropriate circumstances, each embodiment disclosed herein can in any combination, without departing from spirit of the invention and Range.Introduction in this according to the present invention, the those of ordinary skill of correlative technology field be easily envisaged that it is many modification and Variation, these modifications and variations are also included within the spirit and scope of the present invention.The scope of the present invention is by appended claims To limit.

Claims

1. a kind of manufacturing method of semiconductor device, comprising:

First groove is formed in the substrate, and the first groove is used to be isolated the active area of the transistor of the first kind；

The first insulation filler is formed in the first groove, first filler is configured as applying adjacent active area Add stress；

Second groove is formed in the substrate, and the second groove is used to be isolated the active area of the transistor of Second Type；

The second insulation filler is formed in the second groove, second filler is configured as applying adjacent active area Add stress.

2. according to the method described in claim 1,

Wherein the transistor of the first kind is PMOS transistor, and the transistor of the Second Type is NMOS transistor,

The first filler is wherein formed in the first groove includes:

The oxide for forming silicon over the substrate by high aspect ratio plasma deposition process is formed by the oxide of silicon extremely The first groove is filled less；And

Processing is removed to the oxide of the silicon, to retain the oxide for the silicon being filled in the first groove.

3. according to the method described in claim 2, wherein forming the second filler in the second groove and including:

The oxide for forming silicon over the substrate by higli density plasma deposition process is formed by the oxide of silicon extremely The second groove is filled less；And

Processing is removed to the oxide of the silicon, to retain the oxide for the silicon being filled in the second groove.

4. according to the method described in claim 1,

Wherein the transistor of the first kind is NMOS transistor, and the transistor of the Second Type is PMOS transistor,

The first filler is wherein formed in the first groove includes:

The oxide for forming silicon over the substrate by higli density plasma deposition process is formed by the oxide of silicon extremely The first groove is filled less；And

5. according to the method described in claim 4, wherein forming the second filler in the second groove and including:

The oxide for forming silicon over the substrate by high aspect ratio plasma deposition process is formed by the oxide of silicon extremely The second groove is filled less；And

6. method according to any one of claims 1-5, wherein the substrate includes silicon substrate.

7. method according to any one of claims 1-5, in which:

The active area of the first transistor is arranged between two first grooves,

The active area of the second transistor is arranged between two second grooves.

8. method according to any one of claims 1-5, wherein formation first groove includes: in the substrate

Patterned mask is formed over the substrate；

The substrate is etched using the mask, to form the first groove.

9. method according to any one of claims 1-5, wherein forming second groove in the substrate includes:

Patterned mask is formed over the substrate；

The substrate is etched using the mask, to form the second groove.

10. method according to any one of claims 1-5, further includes:

It is formed over the substrate for the gate insulating layer of the first transistor and the grid on gate insulating layer and is used for The gate insulating layer of second transistor and the grid on gate insulating layer；

It is formed in the substrate for the source region of the first transistor and drain region and source region and drain region for second transistor.