CN109614350A

CN109614350A - A kind of interruption system communicated for dual port RAM between processor

Info

Publication number: CN109614350A
Application number: CN201811264377.2A
Authority: CN
Inventors: 周明杰
Original assignee: Luoyang Institute of Electro Optical Equipment AVIC
Current assignee: Luoyang Institute of Electro Optical Equipment AVIC
Priority date: 2018-10-29
Filing date: 2018-10-29
Publication date: 2019-04-12
Anticipated expiration: 2038-10-29
Also published as: CN109614350B

Abstract

The present invention provides a kind of interruption systems communicated for dual port RAM between processor to be used for transmission the FIFO of interruption when communicating between processor 1 and processor 2 by dual port RAM, which realizes by fifo chip or by programmable logic；Port is written by the data that parallel bus connects FIFO in processor 1, and processor 2 connects the data reading port of FIFO by parallel bus, while by the external interrupt input port of the empty indication signal EMPTY connection processor 2 of FIFO.The present invention improves the real-time of dual port RAM communication between processor, guarantees the reliability and high efficiency of interrupting transmitting, while can realize IRQ sharing.

Description

A kind of interruption system communicated for dual port RAM between processor

Technical field

The present invention relates to Embedded System Design technical field, especially a kind of interruption system for dual port RAM communication.

Background technique

Dual port RAM communication be embedded system processing device between the common means of communication of data interaction, communication mode not by Specialized protocol constraint customizes degree height, and low to bottom hardware resource requirement, parallel transmission mode ensure that the band centainly communicated Width, while its data buffer storage mechanism can reduce the synchronous of communicating pair processor operation and require, and guarantee the reliability of communication data. Therefore.At present in airborne equipment, dual port RAM communication is the frequently-used data communication based on printed board interconnection between embeded processor Internal bus.

In dual port RAM communication, there are biggish defects in terms of real-time by the way of software cycle inquiry, therefore Need to design interruption transmission mechanism.It interrupts between conventional processors and is transmitted using general discrete amount interface, this mode is continuous more When interrupting transmission, existing defects in terms of reliability and efficiency, therefore how to design it is a kind of it is reliable, efficiently interrupt transmission mechanism, Be we there is an urgent need to the projects of research.

Summary of the invention

For overcome the deficiencies in the prior art, the present invention provides a kind of interruption system communicated for dual port RAM between processor System.The object of the present invention is to provide a kind of design of interruption communicated for dual port RAM between processor, to improve dual port RAM communication Real-time and reliability.To achieve the above object, the present invention can be realized based on dedicated fifo chip, can also be patrolled programmable It is completed in volume by standard hardware programming language.

The technical solution adopted by the present invention to solve the technical problems is:

The described interruption system communicated for dual port RAM between processor, when passing through twoport between processor 1 and processor 2 When RAM is communicated, it is used for transmission the FIFO of interruption, which realizes by fifo chip or by programmable logic；Processor 1 is logical The data write-in port of parallel bus connection FIFO is crossed, processor 2 reads port by the data that parallel bus connects FIFO, together When by the external interrupt input port of the empty indication signal EMPTY connection processor 2 of FIFO.

It is communicated between processor 1 and processor 2 by dual port RAM, when processor 1 needs to transmit different channels to processor 2 Communication data when, data block is written in dual port RAM in data block corresponding address, then will represent the interruption of the address to Amount is written in FIFO, once being written into data in FIFO, empty indication signal EMPTY is invalid, which triggers the outer of processor 2 Portion is interrupted, and processor 2 enters after interrupt service routine the interrupt vector read in FIFO, and according to interrupt vector from dual port RAM Middle corresponding address reads data, completes interrupt processing, and since the data in FIFO are read, empty indication signal EMPTY is effective, place The interruption of reason device 2 cancels automatically.

The beneficial effects of the present invention are the real-time that dual port RAM communicates between processor is improved, guarantee to interrupt transmitting Reliability and high efficiency, while can realize IRQ sharing.

Detailed description of the invention

Fig. 1 is the design of interruption block diagram the present invention is based on FIFO.

Specific embodiment

Present invention will be further explained below with reference to the attached drawings and examples.

A kind of interruption system communicated for dual port RAM between processor of the invention, when logical between processor 1 and processor 2 When crossing dual port RAM communication, it is used for transmission the FIFO of interruption, which can realize by fifo chip or by programmable logic； Port is written by the data that parallel bus connects FIFO in processor 1, and processor 2 is read by the data that parallel bus connects FIFO Exit port, while by the external interrupt input port of the empty indication signal EMPTY connection processor 2 of FIFO.

A kind of interruption system communicated for dual port RAM between processor of the invention, workflow are as follows: 1 He of processor It is communicated between processor 2 by dual port RAM, when processor 1 needs to transmit the communication data in different channels to processor 2, will be counted It is written in dual port RAM in data block corresponding address according to block, then the interrupt vector for representing the address is written in FIFO, Once being written into data in FIFO, empty indication signal EMPTY is invalid, which triggers the external interrupt of processor 2, processor 2 The interrupt vector in FIFO is read after into interrupt service routine, and corresponding address is read from dual port RAM according to interrupt vector Data complete interrupt processing, and since the data in FIFO are read, empty indication signal EMPTY is effective, and the interruption of processor 2 is certainly Dynamic revocation.

The FIFO of Transmission is designed between processor 1 and processor 2, which can pass through dedicated integrated circuits Chip or programmable logic are realized；

Port is written by the data that parallel bus connects FIFO in processor 1, and processor 2 connects FIFO by parallel bus Data read port, while by the external interrupt input port of the empty indication signal EMPTY connection processor 2 of FIFO；

When processor 1 needs to transmit the communication data in different channels to processor 2, write data into dual port RAM Address is formulated, then the interrupt vector for representing the address is written in FIFO, once being written into data in FIFO, sky instruction letter Number EMPTY is invalid, which triggers the external interrupt of processor 2, and processor 2 is read in FIFO after entering interrupt service routine Interrupt vector, and according to interrupt vector, corresponding address reads data from dual port RAM, interrupt processing is completed, due in FIFO Data are read, and empty indication signal EMPTY is effective, and the interruption of processor 2 cancels automatically.

Claims

1. a kind of interruption system communicated for dual port RAM between processor, it is characterised in that:

The interruption system communicated for dual port RAM between processor, when logical by dual port RAM between processor 1 and processor 2 When letter, it is used for transmission the FIFO of interruption, which realizes by fifo chip or by programmable logic；Processor 1 is by simultaneously Port is written in the data that row bus connects FIFO, and processor 2 reads port by the data that parallel bus connects FIFO, simultaneously will The external interrupt input port of the empty indication signal EMPTY connection processor 2 of FIFO；

It is communicated between processor 1 and processor 2 by dual port RAM, when processor 1 needs to transmit the logical of different channels to processor 2 When letter data, data block is written in dual port RAM in data block corresponding address, is then write the interrupt vector for representing the address Enter into FIFO, once being written into data in FIFO, empty indication signal EMPTY is invalid, which triggers in the outside of processor 2 It is disconnected, the interrupt vector in FIFO is read after the entrance interrupt service routine of processor 2, and right from dual port RAM according to interrupt vector Address reading data is answered, completes interrupt processing, since the data in FIFO are read, empty indication signal EMPTY is effective, processor 2 interruption cancels automatically.