CN109597815A

CN109597815A - A kind of data mode update method, device, equipment and medium

Info

Publication number: CN109597815A
Application number: CN201811256469.6A
Authority: CN
Inventors: 殷贤程
Original assignee: Alibaba Group Holding Ltd
Current assignee: Advanced New Technologies Co Ltd; Advantageous New Technologies Co Ltd
Priority date: 2018-10-26
Filing date: 2018-10-26
Publication date: 2019-04-09
Anticipated expiration: 2038-10-26
Also published as: CN117112581A; CN109597815B

Abstract

This specification embodiment discloses a kind of data mode update method, device, equipment and medium, data mode update method and comprises determining that the state renewal sequence of data；The state of the data is updated according to the state renewal sequence timing；For any data, reaches specified time if data mode update is unsuccessful, which is removed into the state renewal sequence.

Description

Data state updating method, device, equipment and medium

Technical Field

The present application relates to the field of computer technologies, and in particular, to a method, an apparatus, a device, and a medium for updating a data status.

Background

In the prior art, each data is often subjected to one or more processing stages before being finally processed. Each data usually corresponds to a certain number of service details, and each service detail corresponds to a certain service logic at each processing stage, so that the service logic of each service detail of each data needs to be processed (i.e., the service details are processed) at each processing stage. Generally, in each processing stage, each data needs to be scanned to detect whether the service logic of the service detail corresponding to the batch is completed, and if all the service logics of all the service details of a certain data are completed, the state of the data is updated, and the data can enter the next processing stage. The current common scheme is to sort the data according to the creation time, and to periodically fish the front appointed data for scanning and status updating. However, one very easy situation occurs, if the service detail of some data in the previously specified data is blocked or processing fails, the state of the data with the service detail blocking or processing failure (not simply referred to as "processing failure data") is updated unsuccessfully and is put back, and the processing failure services are fished out and put back each time the data is fished out, so that the fishing or updating resources are occupied, and the data processed by other service details sequenced later cannot be fished out later. Under extreme conditions, if the condition that the business detail is blocked or the processing fails occurs to the previous appointed data, the previous appointed data can be fished during each fishing, so that the processed data of other business details sequenced later can not be fished, and the data can not enter the next processing stage to cause the stagnation of the whole processing process.

In view of the above, there is a need for a more efficient and effective data state update scheme.

Disclosure of Invention

The embodiment of the specification provides a data state updating method, a data state updating device, data state updating equipment and a data state updating medium, and aims to solve the technical problem of how to update the data state more effectively and more efficiently.

In order to solve the above technical problem, the embodiments of the present specification are implemented as follows:

an embodiment of the present specification provides a data state updating method, including:

determining a state update sequence of the data;

updating the state of the data according to the state updating sequence at regular time;

for any of the data, if the data status update is unsuccessful up to a specified number of times, moving the data out of the status update sequence.

An embodiment of the present specification further provides a data state updating apparatus, including:

the queuing module is used for determining a state updating sequence of the data;

the state updating module is used for updating the state of the data at regular time according to the state updating sequence;

and the dequeuing module is used for shifting the data out of the state updating sequence if the data is unsuccessfully updated for a specified time.

at least one processor;

and the number of the first and second groups,

a memory communicatively coupled to the at least one processor;

wherein,

the memory stores instructions executable by the at least one processor to enable the at least one processor to:

determining a state update sequence of the data;

Embodiments of the present specification also provide a computer-readable storage medium storing computer-executable instructions, which when executed by a processor implement the following steps:

determining a state update sequence of the data;

The embodiment of the specification adopts at least one technical scheme which can achieve the following beneficial effects:

because the state of the data is updated according to the state updating sequence, and the data which is not successfully updated for the specified time is moved out of the state updating sequence, the state updating sequence can be continuously changed and updated, and the data which is not successfully updated does not continuously occupy the state updating resource, thereby improving the data state updating efficiency. The state updating sequence of the data is determined according to the processing time and/or the priority of the data, so that the data with short processing time and/or high priority can be updated in a state more quickly, and the data state updating efficiency is improved.

Drawings

In order to more clearly illustrate the embodiments of the present specification or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments of the present specification or the prior art will be briefly introduced below, it is obvious that the drawings in the following description are only some embodiments described in the present specification, and for those skilled in the art, other drawings can be obtained according to the drawings without inventive labor.

Fig. 1 is a schematic diagram of a data status updating system according to a first embodiment of the present disclosure.

Fig. 2 is a flowchart illustrating a data status updating method according to a second embodiment of the present disclosure.

Fig. 3 is a schematic diagram of a data status updating process in a second embodiment of the present specification.

Fig. 4 is a schematic diagram of a data status updating process in a third embodiment of the present specification.

Fig. 5 is a schematic structural diagram of a data status updating apparatus according to a fourth embodiment of the present disclosure.

Fig. 6 is a schematic structural diagram of another data status updating apparatus according to a fourth embodiment of the present disclosure.

Detailed Description

In order to make those skilled in the art better understand the technical solutions in the present specification, the technical solutions in the embodiments of the present specification will be clearly and completely described below with reference to the drawings in the embodiments of the present specification, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be obtained by a person skilled in the art without making any inventive step based on the embodiments of the present disclosure, shall fall within the scope of protection of the present application.

In the prior art, a common scheme is to sort data according to creation time, and to periodically fetch a specified number of data before scanning and updating a state. However, one very easy situation occurs, if the service detail of some data in the previously specified data is blocked or processing fails, the state of the data with the service detail blocking or processing failure (not simply referred to as "processing failure data") is updated unsuccessfully and is put back, and the processing failure services are fished out and put back each time the data is fished out, so that the fishing resources (or updating resources) are occupied, and the data processed by other service details sequenced later cannot be fished out later. As shown in fig. 1, in the first embodiment of the present specification, for any or specified data, the data state updating system 1 determines a state updating sequence of the data (for example, the state updating sequence has m positions), and updates the state of the data at regular time according to the state updating sequence; for any of the data, if the data status update is unsuccessful up to a specified number of times, moving the data out of the status update sequence.

In this embodiment, the state of the data is updated according to the state update sequence, and the data that has not been updated successfully for the specified time is shifted out of the state update sequence, so that the state update sequence is continuously changeable and updatable, and the data that has not been updated continuously does not occupy the state update resource, thereby improving the data state update efficiency.

From the program perspective, the main body of the above-mentioned flow may be a computer, a server, or a corresponding data state refinement system, and in addition, a third-party application client may assist the flow execution.

Fig. 2 is a schematic flow chart illustrating a data state updating method according to a second embodiment of the present disclosure, and fig. 3 is a schematic diagram illustrating a data state updating process according to the second embodiment of the present disclosure. Referring to fig. 2 and 3, the data state updating method in the present embodiment may include:

s101: a state update sequence of the data is determined.

In the prior art, each data is often subjected to one or more processing stages before being finally processed. Each data may correspond to a certain number of service details, and each service detail corresponds to a certain service logic in each processing stage, so that the service logic of each service detail of each data needs to be processed in each processing stage. Generally, in each processing stage, each data needs to be scanned at regular time to detect whether the service logic of the service detail corresponding to the batch is completed, and if the service logic of all the service details of a certain data is completed, the state of the data is updated, and the data can enter the next processing stage. In general, on one hand, at any processing stage, a specified number of data are fetched for scanning each time, that is, the number of data that can be status-detected and updated each time is limited and is not recorded as a single update amount; on the other hand, the amount of data processed at any one stage of processing tends to be more than the amount of a single update.

In this embodiment, at any one processing stage, a state update sequence (hereinafter referred to as "sequence") of data is determined for any or specified or random data that needs to enter the processing stage. The sequence has several positions in sequence, which is usually finite, the number of positions in the sequence may be fixed, or the number of positions in the sequence may be determined or transformed as desired.

The sequence of data may be determined in the following manner (which is equivalent to assigning data to a sequence in the following manner):

1. processing time according to the predicted data.

For any or specified data, if the data corresponds to a certain number of service details, the processing time of the data in any processing stage is the time when the service logic of each corresponding service detail is completely processed in the processing stage. For any or specified data, the processing time of the data at any processing stage can be predicted. To predict the processing time of data a in any processing stage (not assumed to be the first processing stage), the processing time of data a in the first processing stage (hereinafter referred to as "predicted processing time of data a") may be predicted from the historical average processing time of the same kind of data a (that is, the same type of data as data a) in the first processing stage. For example, if the same kind of data as the data a in the past week is processed n times in the first processing stage for a time period of a1, a2, … …, An, respectively, (a1+ a2+ … … + An)/n can be used as the processing time period of the data a.

In this embodiment, each processing stage may correspond to a state update sequence. In the following description, it is not assumed that the first processing stage corresponds to a first state update sequence (hereinafter referred to as "first sequence"), and in the present embodiment, it is not assumed that the sequence has m positions, i.e., the 1 st position, the 2 nd position, … …, and the m th position, each of which can accommodate one or more data. .

Each position of the first sequence may correspond to a certain processing time interval or processing time point (hereinafter referred to as "time interval" or "time point"). For example, each position may correspond to a designated time interval, for example, the 1 st position (hereinafter referred to as "1 st bit") of the first sequence corresponds to a time interval: t is more than 0 and less than or equal to 5; the 2 nd position (hereinafter referred to as "2 nd bit") corresponds to a time interval: t is more than 5 and less than or equal to 10; … …, respectively; the mth position (hereinafter, referred to as "mth bit") corresponds to a time interval: (m-1). times.5 is more than t and less than or equal to mx 5. The unit of the time interval may be time, minute, second, etc., and is not assumed to be second in this embodiment. For another example, each position may correspond to a designated time point, for example, the 1 st position corresponds to the 5 th second from a certain time point (which may be set as required); the 2 nd position corresponds to the 10 th second from a certain time point; … …, respectively; the m-th position corresponds to the m × 5 seconds from a certain time point.

Specifically, the time interval and the time point may be determined according to an interval of two adjacent timing updates (hereinafter referred to as "timing update interval"), for example, if the data state is currently updated every 10 seconds, the time interval and the time point may be set to 10 seconds or a multiple (not necessarily an integer multiple) of 10 seconds or not less than 10 seconds, for example, the 1 st position corresponds to the time interval: t is 0 < t.ltoreq.10, or the 1 st position corresponds to the 10 th second from a certain point in time.

For data a, its location may be determined based on its predicted processing time. If the processing time predicted by the data A is 3 seconds and the data A is in the time interval corresponding to the 1 st bit, the data A is located at the 1 st bit, that is, the data A is added to the 1 st bit; if the processing time of the data a prediction is 8 seconds, and the data a is in the time interval corresponding to the 2 nd bit, the data a is located at the 2 nd bit, and so on. If the position of the first sequence corresponds to a time point, if the processing time predicted by the data a is 3 seconds, and the 3 seconds are between the time points of 0 and 1 st bit, the data a is located at the 1 st bit; if the processing time of the data a prediction is 8 seconds, and 8 seconds are between the time points of the 1 st bit and the 2 nd bit, the data a is located at the 2 nd bit, and so on. It can be seen that the positions of the first sequence may be in communication with time intervals or with time points.

Since the position of the first sequence may be limited, data with a predicted processing time of more than m × 5 seconds may be added to the mth bit as well.

2. According to the priority of the data.

Different data may have different priorities and therefore the position of the data in the first sequence may be determined according to the priority of the data. In this embodiment, each position of the first sequence may correspond to a different priority, for example, bit 1 may correspond to a highest priority, bit 2 may correspond to a second priority, and so on.

It should be noted that each position of the first sequence does not necessarily correspond to only one level of priority, for example, the 1 st bit may correspond to the highest level of priority and the second level of priority, the 2 nd bit may correspond to the third level of priority and the fourth level of priority, and so on.

3. According to predicted data processing time and data priority

The position of the data in the first sequence may be determined based on the predicted data processing time and the priority of the data. For example, when the priority of the data reaches and/or is higher than the designated priority, the position of the data in the first sequence may be determined only according to the priority; when the priority of the data is lower than the designated priority, then the position of the data in the first sequence may be determined based only on the predicted data processing time.

Still taking the first processing stage and the data a as an example, before or when the data a enters the first processing stage, the position of the data a in the first sequence may be determined as above, and the data a may be added to the corresponding position of the first sequence, so that any data that needs to enter the first processing stage may be added to the first sequence. It is to be noted that it is not excluded that the first sequence is empty at one or some positions.

S102: and updating the state of the data at regular time according to the state updating sequence.

For a data, its predicted processing time will typically approach its actual processing time. In this embodiment, updating the data state according to the first sequence specifically includes: each time of timing update, scanning specified data (namely single update amount) from the data of the 1 st bit, and checking whether each service detail of each data in the specified data is processed completely, namely executing a timing update task. For any data in the specified data, if all the service details of the data are processed, the state of the data is updated successfully; if all the service details of the data are not processed (namely, the data are not processed), or if the service details are blocked or the processing is failed (namely, the data processing is wrong), the status update of the data is unsuccessful. If the data fails to update the status because it has not been processed, the data is retained in the sequence for subsequent scanning.

In this embodiment, the data whose status is updated successfully at each timing update is shifted out of the first sequence. Assuming that the state update of the data a is successfully shifted out of the first sequence, if the data a enters the next processing stage, the data a may enter the state update sequence corresponding to the next processing stage.

As can be seen, the less processing time actually required for data, the less processing time for data prediction, and the earlier the position in the sequence (bit 1 is the most advanced position), the faster the state update can be obtained, and the data state update efficiency can be improved.

Further, after any timing update, the data in the non-first position of the first sequence before the timing update advances by one position, that is, the data in the 2 nd bit before the timing update advances to the 1 st bit after the timing update, the data in the 3 rd bit before the timing update advances to the 2 nd bit after the timing update, … …, and the data in the m-2 nd bit before the timing update advances to the m-1 th bit after the timing update. For the data on the mth bit before the timing update, since the prediction processing time of the data on the mth bit is generally long, the data on the mth bit before the timing update may not fully advance to the m-1 th bit after the timing update. The following rules may be followed: for any data in the mth bit, the data B is not recorded as data B, the timing update interval is recorded as T, the processing time predicted by the data B is recorded as T, and if the time elapsed from the addition of the mth bit to the ith timing update is T ', T-c is less than or equal to T' + (m-1). times.t is less than or equal to T + c, and c is a specified number, the data B advances to the m-1 th bit after the ith timing update. Where (m-1) × t is the time required for data B to advance from the mth bit to the 1 st bit. By this rule, the time from the addition of the m-th bit to the advance to the 1 st bit of the data B can be made to be close to or even equal to the processing time of the prediction of the data B.

It can be seen that for any one of the first m-1 positions of the first sequence, there may be two sources of data thereon, namely, data assigned to that position by the method in S101, and data that is advanced to that position by a position that is subsequent to that position. For the mth position of the first sequence, the data source thereon is allocated by the method in S101. It can be seen that the amount of data at each position in the first sequence may be constantly changing, and thus the amount of data at bit 1 may be more or less than or equal to the amount of a single update at the time of a timing update. One case may be that only the data on bit 1 is scanned, no matter how much the amount of data on bit 1 is at the time of the timing update; alternatively, if the number of 1 st bits of data is smaller than the single update amount at the time of the timing update, the data at the 2 nd and subsequent positions may be scanned in the order of the positions of the first sequence.

The data on bit 1 may be sorted before each timing update, regardless of the source of the data on bit 1. In particular, the data may be ordered according to creation time of the data and/or time of entering the first processing stage and/or time of entering the 1 st bit and/or priority, with earlier creation time and/or time of entering the first processing stage and/or higher priority data ordered further forward. On the basis of sorting the data on the 1 st bit, the data on other positions can also be sorted in the same way. On the basis of sorting the data at the single position of the first sequence, every time the timing is updated, the data is scanned by a single update amount from the 1 st data of the 1 st bit. Similarly, only the data on the 1 st bit may be scanned, or if the number of the data on the 1 st bit is smaller than the single update amount at the time of the timing update, the data on the 2 nd bit and the following positions may be scanned, and for the 2 nd bit or the following positions, as long as the data thereon is sorted, the data thereon may be scanned in sequence.

The timing update procedure is further explained below:

assuming that the timing update interval is 5 seconds, i.e. the first sequence is scanned every 5 seconds, the time interval of each position of the first sequence also spans 5 seconds, i.e. bit 1 corresponds to the time interval: t is more than 0 and less than or equal to 5; the first bit corresponds to a time interval: t is more than 5 and less than or equal to 10; … …, respectively; the mth bit corresponds to a time interval: (m-1). times.5 is more than t and less than or equal to mx 5. Still taking data a as an example, consider several cases (not considering the case of traffic detail processing error):

(1) data a is not initially assigned to bit 1. Assuming that the processing time of the predicted data a in the first processing stage is 15 seconds, the 3 rd bit is added when the data a enters the first processing stage, and at the same time, the data a starts the processing in the first processing stage. If only the first designated data of the 1 st bit of the first sequence is scanned for each timing update, after the data a is added into the first sequence, the data a can enter the 1 st bit after two timing updates. The third time the data a is added to the first sequence, the data a may be scanned. The time required from the data A being added into the first sequence to the data A being added into the first sequence for the third timing update is more than or equal to 15 seconds, and the time required from the data A being added into the first sequence to the data A being scanned for the first time is more than or equal to the time required from the data A being added into the first sequence to the data A being added into the first sequence for the third timing update, that is, the time is more than or equal to the predicted processing time of the data A, so that the data A is scanned after being added into the first sequence, and the data A is already processed when being scanned, no matter whether the data A is scanned by the third timing update or the data A is scanned by a certain timing update later, and the data A can be successfully updated when being scanned for the first time. Even if the data a is not processed when it is scanned for the first time, the processing time required for the data a after this scanning is short because the time from when the data a is added to the first sequence until when the data a is scanned for the first time is equal to or longer than the predicted processing time for the data a. Even if the data of the 1 st bit before each timing scan is reordered, the data a is scanned next because the creation time of the data a and/or the time for entering the first processing stage is unchanged, and by that time, the data a is usually processed, so that the status update is successful.

Since the data on bit 1 can be sorted according to the creation time and/or the time of entering the first processing stage, after the data a enters bit 1, even if new data is added to bit 1 due to the short predicted processing time, since the creation time and/or the time of entering the first processing stage of data a is earlier, the data a can be ranked earlier in bit 1 and can be scanned and updated more quickly.

(2) Considering the case where the sequence positions are assigned in accordance with the predicted processing time, assuming that data a is initially assigned to the 1 st bit, only the first specified data of the 1 st bit of the first sequence is scanned for each timing update. If the data a is scanned at the first time of the timing update after the data a is allocated to the position, the data a can be allocated to the 1 st bit, which means that the processing time predicted by the data a is not long and is equal to or less than the timing update interval, and therefore the data a is normally processed and the state can be updated when the data a is scanned at the first time. Even if the data a is not processed when being scanned for the first time, the processing time of the data a is shorter after the scanning. Even if the data of the 1 st bit before each timing scan is reordered, the data a is scanned next because the creation time of the data a and/or the time for entering the first processing stage is unchanged, and by that time, the data a is usually processed, so that the status update is successful.

(3) Assuming that data a is initially assigned to bit 1, data a is not scanned at the first timing update thereafter, and since the creation time of data a and/or the time to enter the first processing stage does not change, the ordering of data a will advance at the next timing update, be more easily scanned, and by time reference (2), data a will typically have been processed, and the status update will be successful.

(4) If the priority of the data needs to be considered, the location of the high priority data allocation may be earlier and scanned faster. Although some data have high priority and are allocated in the front, the predicted processing time is long, and the data can be updated successfully after being scanned for multiple times, and the updating resources are occupied in the multiple scans. However, taking into account the priority factor, it is beneficial and may be necessary in some cases to enable higher priority data to be updated more quickly.

It can be seen that, in this embodiment, regardless of the predicted processing time of the data, the data can be assigned to an appropriate sequence position, and on the one hand, the position of the data in the sequence with the smaller predicted processing time can be earlier, so that the status update can be obtained more quickly; on the other hand, the time required by the data from the time when the data is added to the sequence to the time when the data is scanned is more consistent with the processing time required by the data, so that the interval time from the time when the data is processed to the time when the data is updated can be shortened, and the processed data can be updated in a state more quickly; in another aspect, the processing time and priority can be balanced and balanced, so the embodiment has better universality. On the basis, the embodiment is beneficial to ensuring that the scanned data is processed and can or needs to be subjected to state updating when the timing updating is performed each time. By the embodiment, the data state updating efficiency can be improved.

S103: for any of the data, if the data status update is unsuccessful up to a specified number of times, moving the data out of the status update sequence.

One possible scenario is that the failure of a status update when data is scanned is due to some non-temporal error (e.g., the aforementioned traffic profile is stuck or the process fails), which is not automatically corrected over time, and even if scanned again, will still fail the status update. Still taking data a as an example, if the non-temporal error occurs when data a is scanned, data a is shifted out of the sequence.

In this embodiment, whether the non-temporal error occurs in the data may be found by checking the service logic of the service details of the data, and whether the data needs to be shifted out of the sequence may also be determined by the number of times that the status update is unsuccessful. Still taking data a as an example, normally, according to the content of this embodiment, data a should be successfully updated after one or several scans. If the state updating of the data a still fails after the specified scanning, it can be determined that the data a has the above non-temporal error, and the data a can be shifted out of the sequence.

For the data with the non-temporal error, the data does not complete the status update through the timing scanning, and the data with the status update failure due to the non-temporal error is removed in this embodiment, so that the timing update resource can be released in time, and the data status update efficiency is improved.

The third embodiment of the present specification includes, in addition to the contents of the first and/or second embodiment: the data may pass through a plurality of processing stages, each processing stage may correspond to a state update sequence, the data that is successfully updated in the state update sequence corresponding to the previous processing stage is added to the state update sequence corresponding to the next processing stage, and each state update sequence may adopt the above-described state update process. For example, as shown in fig. 4, the data with the 1 st bit successfully updated in the first sequence may enter a second sequence corresponding to the second processing stage, and the timing update process of the second sequence is the same as that of the first sequence.

Further, if the non-temporal error occurs in the data, a prompt may be performed, and it may be detected at regular time whether the status update is successful after the data is moved out of the sequence (for example, there may be a possibility that a human intervention is performed to process and update the status of the data after the prompt). If so, the data may be added to the state update sequence corresponding to the next processing stage of the processing stage corresponding to the state update sequence from which it was removed.

Based on the same idea, as shown in fig. 5, a fourth embodiment of the present specification provides a data status updating apparatus, including:

a queuing module 201, configured to determine a status update sequence of data;

a state updating module 202, configured to update the state of the data periodically according to the state updating sequence;

and the dequeuing module 203 is configured to, for any one of the data, move the data out of the status update sequence if the status update of the data is unsuccessful for a specified number of times.

Optionally, as shown in fig. 6, the apparatus further includes:

a time prediction module 204, configured to predict a processing time of any or specified data;

and/or the presence of a gas in the gas,

a priority determination module 205, configured to determine, for any or specified data, a priority of the data;

the queuing module 201 determines a status update sequence of data according to the predicted processing time and/or the priority.

Optionally, if the priority of the data reaches and/or is higher than the designated priority, the data is added to the status update sequence according to the priority only.

Optionally, the status update sequence has several positions in sequence, each position accommodating one or more data.

Optionally, determining the state update sequence of the data according to the predicted processing time includes:

each position of the state updating sequence corresponds to a certain time interval or time point;

determining the position of the data in the state update sequence according to the predicted processing time;

and/or the presence of a gas in the gas,

determining a state update sequence for the data based on the predicted processing time includes:

the position of the data with shorter processing time in the state updating sequence is closer to the front;

and/or the presence of a gas in the gas,

determining a state update sequence of data according to the priority comprises:

the higher the priority of the data, the earlier the position of the data in the state update sequence;

and/or the presence of a gas in the gas,

the higher the priority of the data is, the earlier the data is in the status update sequence, the highest priority data is in the first position of the status update sequence.

Optionally, the span of the time interval is a time interval between two adjacent timing updates;

or,

the span of the time interval is a multiple of the time interval of two adjacent timing updates;

and/or the presence of a gas in the gas,

the time interval spans no less than the time interval of two adjacent timing updates.

Optionally, the updating the state of the data according to the state updating sequence at regular time includes:

periodically updating the state of one or more data located at the first position of the state updating sequence;

or,

before each timing update, sequencing data at the first position or a plurality of positions including the first position of the state update sequence, and updating the state of one or more data positioned at the first position and sequenced in the front at a timing;

or,

starting from the data at the first position of the state updating sequence, updating the state of the designated data at regular time;

or,

before each timing update, sequencing the data at the first position or a plurality of positions including the first position of the state update sequence, and starting from the first data at the first position of the state update sequence, updating the state of the appointed data at a timing.

Optionally, the sorting the data located at the first position or a plurality of positions including the first position of the status update sequence includes:

data at the first position of the status update sequence is ordered according to creation time and/or priority.

Optionally, the queuing module 201 is further configured to:

and after the state of the data is updated regularly each time, advancing the data on the non-first position by one position.

Optionally, each processing stage of the data corresponds to a state update sequence, and the state update module 202 is further configured to: and updating the state of the data in each state updating sequence at regular time.

Optionally, the dequeue module 203 is further configured to:

and shifting the data with successful state updating out of the state updating sequence.

Optionally, the queuing module 201 is further configured to:

adding the data which is successfully updated in the state updating sequence corresponding to the previous processing stage into the state updating sequence corresponding to the next processing stage;

and/or the presence of a gas in the gas,

the dequeue module 203 is further configured to:

for any data in any state updating sequence, if the data state updating is unsuccessful for a specified time, the data is shifted out of the state updating sequence;

and/or the presence of a gas in the gas,

the dequeue module 203 is further configured to:

for any data in any state updating sequence, if the data state updating is unsuccessful for a specified time, moving the data out of the state updating sequence and prompting;

and/or the presence of a gas in the gas,

for any data in any state updating sequence, if the data state updating is unsuccessful for a specified time, the dequeuing module 203 shifts the data out of the state updating sequence in which the data is located; if the data is moved out of the state update sequence and the state update is successful, the queuing module 201 adds the data to the state update sequence next to the removed state update sequence.

Based on the same idea, a fifth embodiment of the present specification provides a data status updating apparatus, including:

at least one processor; and the number of the first and second groups,

a memory communicatively coupled to the at least one processor;

wherein,

determining a state update sequence of the data;

Based on the same idea, a sixth embodiment of the present specification provides a computer-readable storage medium storing computer-executable instructions, which when executed by a processor implement the steps of:

determining a state update sequence of the data;

While certain embodiments of the present disclosure have been described above, other embodiments are within the scope of the following claims. In some cases, the actions or steps recited in the claims may be performed in a different order than in the embodiments and still achieve desirable results. In addition, the processes depicted in the accompanying figures do not necessarily have to be in the particular order shown or in sequential order to achieve desirable results. In some embodiments, multitasking and parallel processing may also be possible or may be advantageous.

The embodiments in the present specification are described in a progressive manner, and the same and similar parts among the embodiments are referred to each other, and each embodiment focuses on the differences from the other embodiments. In particular, for the apparatus, device, and non-volatile computer-readable storage medium embodiments, since they are substantially similar to the method embodiments, the description is relatively simple, and in relation to the description, reference may be made to some portions of the description of the method embodiments.

The apparatus, the device, the nonvolatile computer readable storage medium, and the method provided in the embodiments of the present specification correspond to each other, and therefore, the apparatus, the device, and the nonvolatile computer storage medium also have similar advantageous technical effects to the corresponding method.

In the 90 s of the 20 th century, improvements in a technology could clearly distinguish between improvements in hardware (e.g., improvements in circuit structures such as diodes, transistors, switches, etc.) and improvements in software (improvements in process flow). However, as technology advances, many of today's process flow improvements have been seen as direct improvements in hardware circuit architecture. Designers almost always obtain the corresponding hardware circuit structure by programming an improved method flow into the hardware circuit. Thus, it cannot be said that an improvement in the process flow cannot be realized by hardware physical modules. For example, a Programmable Logic Device (PLD), such as a Field Programmable Gate Array (FPGA), is an integrated circuit whose Logic functions are determined by programming the Device by a user. A digital system is "integrated" on a PLD by the designer's own programming without requiring the chip manufacturer to design and fabricate application-specific integrated circuit chips. Furthermore, nowadays, instead of manually making an integrated Circuit chip, such Programming is often implemented by "logic compiler" software, which is similar to a software compiler used in program development and writing, but the original code before compiling is also written by a specific Programming Language, which is called Hardware Description Language (HDL), and HDL is not only one but many, such as abel (advanced Boolean Expression Language), ahdl (alternate Language Description Language), traffic, pl (core unified Programming Language), HDCal, JHDL (Java Hardware Description Language), langue, Lola, HDL, laspam, hardsradware (Hardware Description Language), vhjhd (Hardware Description Language), and vhigh-Language, which are currently used in most common. It will also be apparent to those skilled in the art that hardware circuitry that implements the logical method flows can be readily obtained by merely slightly programming the method flows into an integrated circuit using the hardware description languages described above.

The controller may be implemented in any suitable manner, for example, the controller may take the form of, for example, a microprocessor or processor and a computer-readable medium storing computer-readable program code (e.g., software or firmware) executable by the (micro) processor, logic gates, switches, an Application Specific Integrated Circuit (ASIC), a programmable logic controller, and an embedded microcontroller, examples of which include, but are not limited to, the following microcontrollers: ARC 625D, Atmel AT91SAM, Microchip PIC18F26K20, and Silicone Labs C8051F320, the memory controller may also be implemented as part of the control logic for the memory. Those skilled in the art will also appreciate that, in addition to implementing the controller as pure computer readable program code, the same functionality can be implemented by logically programming method steps such that the controller is in the form of logic gates, switches, application specific integrated circuits, programmable logic controllers, embedded microcontrollers and the like. Such a controller may thus be considered a hardware component, and the means included therein for performing the various functions may also be considered as a structure within the hardware component. Or even means for performing the functions may be regarded as being both a software module for performing the method and a structure within a hardware component.

The systems, devices, modules or units illustrated in the above embodiments may be implemented by a computer chip or an entity, or by a product with certain functions. One typical implementation device is a computer. In particular, the computer may be, for example, a personal computer, a laptop computer, a cellular telephone, a camera phone, a smartphone, a personal digital assistant, a media player, a navigation device, an email device, a game console, a tablet computer, a wearable device, or a combination of any of these devices.

For convenience of description, the above devices are described as being divided into various units by function, and are described separately. Of course, the functions of the various elements may be implemented in the same one or more software and/or hardware implementations of the present description.

As will be appreciated by one skilled in the art, the present specification embodiments may be provided as a method, system, or computer program product. Accordingly, embodiments of the present description may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, embodiments of the present description may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and so forth) having computer-usable program code embodied therein.

The description has been presented with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the description. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

In a typical configuration, a computing device includes one or more processors (CPUs), input/output interfaces, network interfaces, and memory.

The memory may include forms of volatile memory in a computer readable medium, Random Access Memory (RAM) and/or non-volatile memory, such as Read Only Memory (ROM) or flash memory (flash RAM). Memory is an example of a computer-readable medium.

Computer-readable media, including both non-transitory and non-transitory, removable and non-removable media, may implement information storage by any method or technology. The information may be computer readable instructions, data structures, modules of a program, or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), Static Random Access Memory (SRAM), Dynamic Random Access Memory (DRAM), other types of Random Access Memory (RAM), Read Only Memory (ROM), Electrically Erasable Programmable Read Only Memory (EEPROM), flash memory or other memory technology, compact disc read only memory (CD-ROM), Digital Versatile Discs (DVD) or other optical storage, magnetic cassettes, magnetic tape magnetic disk storage or other magnetic storage devices, or any other non-transmission medium that can be used to store information that can be accessed by a computing device. As defined herein, a computer readable medium does not include a transitory computer readable medium such as a modulated data signal and a carrier wave.

It should also be noted that the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.

This description may be described in the general context of computer-executable instructions, such as program modules, being executed by a computer. Generally, program modules include routines, programs, objects, components, data structures, etc. that perform particular tasks or implement particular abstract data types. The specification may also be practiced in distributed computing environments where tasks are performed by remote processing devices that are linked through a communications network. In a distributed computing environment, program modules may be located in both local and remote computer storage media including memory storage devices.

The embodiments in the present specification are described in a progressive manner, and the same and similar parts among the embodiments are referred to each other, and each embodiment focuses on the differences from the other embodiments. In particular, for the system embodiment, since it is substantially similar to the method embodiment, the description is simple, and for the relevant points, reference may be made to the partial description of the method embodiment.

The above description is only an example of the present specification, and is not intended to limit the present application. Various modifications and changes may occur to those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the scope of the claims of the present application.

Claims

1. A data status updating method is characterized in that,

determining a state update sequence of the data;

2. The method of claim 1, wherein determining a state update sequence for data comprises:

predicting the processing time of any or specified data; and/or the presence of a gas in the gas,

for any or specified data, determining the priority of the data;

determining a state update sequence of the data according to the predicted processing time and/or the priority.

3. A method according to claim 2, wherein the data is added to the status update sequence only according to priority if the priority of the data is at and/or above a specified priority.

4. The method of claim 2, wherein the sequence of state updates has a number of positions in sequence, each position housing one or more data.

5. The method of claim 4,

and/or the presence of a gas in the gas,

6. The method of claim 5,

the span of the time interval is the time interval of two adjacent timing updates;

or,

and/or the presence of a gas in the gas,

7. The method of claim 4, wherein periodically updating the state of the data according to the state update sequence comprises:

or,

8. The method of claim 7, wherein sorting the data at the first position or a plurality of positions including the first position of the status update sequence comprises:

9. The method of claim 7, wherein the method further comprises:

after the state of the data is updated regularly each time, the data on the non-first position advances by one position.

10. The method of claim 1, wherein the method further comprises:

each processing stage of the data corresponds to one state updating sequence, and the state of the data in each state updating sequence is updated at regular time.

11. The method of any one of claims 1 to 10, further comprising:

12. The method of claims 1 to 10, further comprising:

and/or the presence of a gas in the gas,

for any data in any state updating sequence, if the data state updating is unsuccessful for a specified time, the data is shifted out of the state updating sequence; and if the state updating is successful after the data is moved out of the state updating sequence, adding the data into the state updating sequence next to the removed state updating sequence.

13. A data status update apparatus, comprising:

14. The apparatus of claim 13, wherein the apparatus further comprises:

the time prediction module is used for predicting the processing time of any or appointed data;

and/or the presence of a gas in the gas,

the priority determining module is used for determining the priority of any or appointed data;

the queuing module determines a state update sequence of the data according to the predicted processing time and/or the priority.

15. The apparatus of claim 14,

and/or the presence of a gas in the gas,

16. The apparatus of claim 15, wherein the timing of the updating of the state of the data according to the state update sequence comprises:

or,

17. The apparatus of claim 16, wherein the queuing module is further configured to:

18. The apparatus of any of claims 13 to 17, wherein the dequeue module is further to:

19. A data status update apparatus, comprising:

at least one processor;

and the number of the first and second groups,

a memory communicatively coupled to the at least one processor;

wherein,

determining a state update sequence of the data;

20. A computer-readable storage medium having computer-executable instructions stored thereon which, when executed by a processor, perform the steps of:

determining a state update sequence of the data;