CN109586678B - Channel amplifier and method applied to channel amplifier - Google Patents

Abstract

The channel amplifier comprises an amplifier, a multiplexer and a switching circuit, wherein the channel amplifier selectively operates in a buffering stage or a comparison stage; when the channel amplifier is operated in a buffer stage, the switching circuit couples the output end of the amplifier to a first input end of the amplifier, so that a first input signal received by a second input end of the amplifier is transmitted to the first output end of the channel amplifier; when the channel amplifier operates in a comparison stage, the switching circuit transmits the first input signal at the first output terminal of the channel amplifier to the first input terminal of the amplifier for comparison with a second input signal received at the second input terminal of the amplifier, and outputs a comparison result to the output terminal of the amplifier.

Description

Channel amplifier and method applied to channel amplifier

technical field

The invention relates to a channel amplifier applied in a liquid crystal panel and a method for applying a channel amplifier.

Background technique

In the traditional application of LCD panels, the driving circuit will include a channel amplifier (channel operation amplifier) at the rear end of the driving circuit, which is used as a buffer to continuously output the front-end signal to the rear end. However, the channel amplifier in the general driving circuit Both have disadvantages such as signal distortion and noise enhancement caused by insufficient buffering capacity. If the buffering capacity of the channel amplifier is to be enhanced, it may lead to costs such as power consumption or increased circuit area.

Contents of the invention

One of the objectives of the present invention is to provide a channel amplifier and a method applied to the channel amplifier to solve the above problems.

According to an embodiment of the present invention, a channel amplifier is disclosed, comprising: an amplifier, a multiplexer and a switching circuit, the multiplexer is coupled to an output end of the amplifier and a first output of the channel amplifier between the terminals, and the switch circuit is coupled to the amplifier and the multiplexer, wherein the channel amplifier selectively operates in a buffer stage or a comparison stage; when the channel amplifier operates in a buffer stage, the switch circuit coupling the output terminal of the amplifier to a first input terminal of the amplifier, so that a first input signal received by a second input terminal of the amplifier is transmitted to the first input signal of the channel amplifier through the multiplexer an output terminal; when the channel amplifier operates in a comparison stage, the switching circuit transmits the first input signal on the first input terminal of the channel amplifier to the first input terminal of the amplifier and the first input terminal of the amplifier A second input signal received by the second input end is compared, and a comparison result is output to the output end of the amplifier.

According to an embodiment of the present invention, a method applied to a channel amplifier is disclosed, including: selectively enabling the channel amplifier to operate in a buffer stage and a comparison stage; when the channel amplifier operates in the buffer stage, An output terminal of an amplifier in the channel amplifier is coupled to a first input terminal of the amplifier, so that a first input signal received by a second input terminal of the amplifier passes through a multiplexer in the channel amplifier to a first output terminal of the channel amplifier; and when the channel amplifier is operating in the comparison phase, the first input signal on the first input terminal of the channel amplifier is transmitted to the first output terminal of the amplifier The input terminal is compared with a second input signal received by the second input terminal of the amplifier, and a comparison result is output to the output terminal of the amplifier.

Description of drawings

FIG. 1 is a schematic diagram of a channel amplifier according to an embodiment of the present invention.

FIG. 2 is a schematic diagram of the channel amplifier of FIG. 1 operating in a buffering stage.

FIG. 3 is a schematic diagram of the operation of the channel amplifier according to FIG. 1 in a comparison stage.

FIG. 4 is a timing diagram of a channel amplifier according to an embodiment of the present invention.

FIG. 5 is a schematic diagram of the channel amplifier of FIG. 1 operating in a buffering phase when switching polarities.

FIG. 6 is a schematic diagram of the channel amplifier of FIG. 1 operating in a comparison phase when switching polarities.

【Symbol Description】

100-channel amplifier

110, 210 DAC

120, 220 amplifiers

130 control circuit

140, 240 switching circuit

150 multiplexers

OUT, OUT1, OUT2 output terminals

Vp, Vout, Vp’, Vout’ output signal

IP, IP’ input signal

SW1-SW3 switches

IN1, IN2 input terminals

CTRL control signal

Detailed ways

Certain terms are used throughout the specification and appended claims to refer to particular elements. Those skilled in the art should understand that hardware manufacturers may use different terms to refer to the same component. This description and the appended claims do not use the difference in name as a way to distinguish components, but use the difference in function of components as a criterion for distinguishing. "Includes" mentioned throughout the specification and appended claims is an open-ended term, so it should be interpreted as "including but not limited to". In addition, the term "coupled" here includes any direct and indirect electrical connection means. Therefore, if it is described in the text that a first device is coupled to a second device, it means that the first device can be directly electrically connected to the second device. The second device, or indirectly electrically connected to the second device through other devices or connection means.

1 is a schematic diagram of a channel amplifier 100 according to an embodiment of the present invention. As shown in FIG. A control circuit 130, switching circuits 140 and 240, a multiplexer 150 and output terminals OUT1 and OUT2, wherein the digital-to-analog converter 110, the amplifier 120 and the switching circuit 140 form the positive pole in the differential circuit in the channel amplifier 100 of FIG. 1 Relatively, the digital-to-analog converter 210, the amplifier 220, and the switching circuit 240 form the negative polarity part of the differential circuit in the channel amplifier 100 of FIG. The circuit and the negative polarity circuit are symmetrical, so the subsequent paragraphs of the present invention only describe the positive polarity part of the circuit, and the operation of the negative polarity part of the circuit can be analogized from the positive polarity part of the circuit. The channel amplifier 100 can selectively operate in a buffer stage and a comparison stage. The amplifier 120 includes input terminals IN1, IN2 and an output terminal OUT, wherein the input terminal IN1 operates in the buffer stage, the comparison stage or is located at the pole according to the channel amplifier. During the conversion, the switches SW1, SW2 and SW3 included in the switching circuit 140 are respectively coupled to the output terminal OUT, the output terminal OUT1 of the channel amplifier 100, and the channel amplifier 100, wherein the switching states of the switches SW1-SW3 are controlled by the control circuit 130 according to The stage of operation of the channel amplifier 100 is controlled by the control signal CTRL, and the input terminal IN2 of the amplifier 120 is coupled to the digital-to-analog converter 110 for receiving an input signal from the digital-to-analog converter 110 when the channel amplifier 100 operates in each stage. IP, in addition, as the channel amplifier 100 operates in different stages, the multiplexer 150 is also controlled by the control signal CTRL sent by the control circuit 130. The switch state of will be discussed in detail in the subsequent paragraphs. The present invention does not limit the implementation of the digital-to-analog converters 110 and 210 , likewise, the present invention does not limit the implementation of the amplifiers 120 and 220 , the switches SW1 - SW3 and the multiplexer 150 .

FIG. 2 is a schematic diagram of the channel amplifier 100 operating in the buffer stage according to FIG. 1. As shown in FIG. 2, when the channel amplifier 100 operates in the buffer stage, the control circuit 130 controls the switch SW1 in the switching circuit 140 to be closed by the control signal CTRL, And the switches SW2 and SW3 are turned on, at this time, the input terminal IN1 of the amplifier 120 is coupled to the output terminal OUT of the amplifier 120 through the switch SW1, the amplifier 120 forms a buffer, and the input received from the digital-to-analog converter 110 The signal IP is transmitted to the output terminal OUT of the amplifier 120, and an output signal Vp is formed at the output terminal OUT of the amplifier 120. In addition, as shown in FIG. The converter 150 couples the output terminal OUT of the amplifier 120 to the output terminal OUT1 of the channel amplifier 100, and generates an output signal Vout on the output terminal OUT1. In other words, when the channel amplifier 100 operates in the buffer stage, by controlling The signal CTRL controls the switching circuit 140 and the multiplexer 150 to transmit the input signal IP generated by the digital-to-analog converter 110 to the output terminal OUT1 of the channel amplifier 100 to form an output signal Vout.

Fig. 3 is a schematic diagram according to the channel amplifier of Fig. 1 operating in the comparison stage, as shown in Fig. 3, when the channel amplifier 100 is operated in the comparison stage, the control circuit 130 controls the switch SW2 in the switching circuit 140 to be closed by the control signal CTRL, and The switches SW1 and SW3 are turned on. At this time, the input terminal IN1 of the amplifier 120 is coupled to the output terminal OUT1 of the channel amplifier 100 through the switch SW2, and the output signal Vout on the output terminal OUT1 in the previous buffer stage is transmitted to the output terminal of the amplifier 120. The input terminal IN1 and the amplifier 120 form a comparator for comparing the output signal Vout with the input signal IP received by the input terminal IN2 from the digital-to-analog converter 110 at this time, and the comparison result is sent to the output terminal OUT of the amplifier 120 to form an output signal Vp; in addition, the control circuit 130 controls the multiplexer 150 to disconnect the multiplexer 150 through the control signal CTRL, that is, the multiplexer 150 is no longer coupled to the output terminal OUT of the amplifier 120 and the output terminal of the channel amplifier 100 Between OUT1, in this embodiment, the control circuit 130 can turn off the power supply of the multiplexer 150 through the control signal CTRL, however, this is not a limitation of the present invention, in other embodiments, the control signal CTRL can be used to control the amplifier 120 A switch (not shown in the figure) of the path between the output terminal OUT of the channel amplifier 100 and the output terminal OUT1 of the channel amplifier 100, so that the output signal Vp at this time is not coupled to the output terminal OUT1 through the multiplexer 150, those skilled in the art The implementation of disconnecting the multiplexer 150 should be easy to understand, and the details are omitted here. In other words, when the channel amplifier 100 is operating in the comparison stage, the switching circuit 140 and the multiplexer 150 are controlled by the control signal CTRL to transmit the output signal Vout generated on the output terminal OUT1 in the previous buffer stage to the input terminal of the amplifier 120 IN1 is compared with the input signal IP received by the input terminal IN2 of the amplifier 120 at this time, and the comparison result is generated at the output terminal OUT of the amplifier 120 .

4 is a timing diagram of the channel amplifier 100 according to an embodiment of the present invention. It can be seen from FIG. 2 that when the channel amplifier 100 is operating in the buffer stage, the control signal CTRL controls the switch SW1 in the switching circuit 140 to be closed, and the switches SW2-SW3 To be turned on, and the output terminal OUT of the amplifier 120 is coupled to the output terminal OUT1 of the channel amplifier 100 through the multiplexer 150. At this time, the amplifier 120 forms a buffer, so that the input signal IP of the digital-to-analog converter 110 is transmitted to the channel amplifier. The output terminal OUT1 of 100 forms the output signal Vout. For example, as shown in FIG. 4, if the input signal IP is a voltage signal of 9.2 volts, the output signal Vp and the output signal Vout is a voltage signal with a voltage of 9.2 volts; it can be seen from FIG. 3 that when the channel amplifier 100 is operating in the comparison stage, the control signal CTRL controls the switch SW2 in the switching circuit 140 to be closed, and the switches SW1 and SW3 to be open, and will The multiplexer 150 is disconnected, so that the output signal Vout originally generated at the 9.2 volt voltage signal on the output terminal OUT1 is coupled to the input terminal IN1 of the amplifier 120. At this time, the amplifier 120 forms a comparator. For example, if the digital analog The input signal IP of the converter 110 is a voltage signal of 17.8 volts. The amplifier 120 compares the input signal IP with the output signal Vout of the previous buffer stage. Since the input signal IP (17.8 volts) is greater than the output signal Vout (9.2 volts), this The time amplifier 120 outputs the comparison result with a logic value of 1 and an amplitude of 18 volts at the output terminal OUT to form an output signal Vp; then, when the channel amplifier 100 is operating in the buffer stage again, the control signal CTRL controls the switch in the switching circuit 140 SW1 is closed, switches SW2-SW3 are open, and the output terminal OUT of the amplifier 120 is coupled to the output terminal OUT1 of the channel amplifier 100 through the multiplexer 150. At this time, the amplifier 120 forms a buffer, so that the amplitude is 17.8 volts The input signal IP is transmitted to the output terminal OUT1 of the channel amplifier 100 to form the output signal Vout, and since the output signal Vp was a voltage signal with an amplitude of 18 volts in the previous comparison stage, when the channel amplifier 100 operates in the buffer stage again, the output signal Vp can quickly drop from a voltage signal with an amplitude of 18 volts to a voltage signal with an amplitude of 17.8 volts. Similarly, the time for the output signal Vout on the output terminal OUT1 to rise from 9.2 volts to 17.8 volts can also be increased. In this way, By charging the output terminal OUT of the amplifier 120 to 18V in advance, the problem of insufficient buffer capacity of the channel amplifier mentioned in the prior art can be solved. It should be noted that in the embodiment of FIG. 4 , the time periods of the buffer phase and the comparison phase, and the signal strengths of the output signal Vp and the output signal Vout are just examples and are not a limitation of the present invention.

In the actual application of the liquid crystal panel, the positive polarity part of the circuit, that is, the voltage signal of the circuit part formed by the digital-to-analog converter 110, the amplifier 120 and the switching circuit 140 in the channel amplifier 100 is between 9 volts and 18 volts, relatively, The negative polarity part of the circuit, that is, the voltage signal of the circuit part formed by the digital-to-analog converter 210, the amplifier 220 and the switching circuit 240 in the channel amplifier 100 is between 0 volts and 9 volts, and those skilled in the art should be able to easily understand the negative polarity part The operation of the circuit is briefly described as follows. Referring to FIG. 2 and FIG. 3 again, when the channel amplifier 100 is operating in the buffer stage, the operation of the negative polarity part of the circuit also passes the input signal IP' of the digital-to-analog converter 210 through the amplifier 220 to generate an output signal Vp' is at the output terminal OUT of the amplifier 220. In addition, the output signal Vp' is coupled to the output terminal OUT2 of the channel amplifier 100 through the multiplexer 150 to generate an output signal Vout' at the output terminal OUT2. When the channel amplifier When the 100 operation is in the comparison phase, the operation of the negative polarity part of the circuit will couple the output signal Vout' on the output terminal OUT2 to the input terminal IN2 of the amplifier 220 through the switching circuit 240 to be compared with the input received from the digital-to-analog converter 210 at this time. Compared with the signal IP', relative to the operation of the positive polarity part of the circuit, the comparison result Vp' generated on the output terminal OUT of the amplifier 220 at this time will be a voltage signal with a logic value of 0 and an amplitude of 0, so that when the channel amplifier 100 operates again During the buffering stage, the voltage signal on the output terminal OUT2 of the channel amplifier 100 can rise from the voltage intensity with an amplitude of 0 to the signal intensity of the input signal IP′ at a relatively fast speed.

In the actual application of the liquid crystal panel, in order to avoid the polarization of the liquid crystal, the polarity must be changed in a timely manner. FIG. 5 is a schematic diagram of the channel amplifier 100 operating in the buffer stage according to FIG. When the amplifier 100 is operating in the buffer stage, the control circuit 130 controls the switch SW1 in the switching circuit 140 to be closed through the control signal CTRL, and the switches SW2 and SW3 are turned on. At this time, the input terminal IN1 of the amplifier 120 is coupled to the amplifier 120 through the switch SW1. The output terminal OUT of the amplifier 120 forms a buffer, and transmits the input signal IP received from the digital-to-analog converter 110 to the output terminal OUT of the amplifier 120, and forms an output signal Vp at the output terminal OUT of the amplifier 120, In addition, as shown in FIG. 5 , the control circuit 130 also controls the multiplexer 150 through the control signal CTRL, so that the multiplexer 150 couples the output terminal OUT of the amplifier 120 to the output terminal OUT2 of the channel amplifier 100, and at the output terminal An output signal Vout is generated on OUT2. In other words, when the channel amplifier 100 is operating in the buffer stage, the switching circuit 140 and the multiplexer 150 are controlled by the control signal CTRL, and the input signal IP generated by the digital-to-analog converter 110 is transmitted. to the output terminal OUT2 of the channel amplifier 100 to form an output signal Vout.

FIG. 6 is a schematic diagram of the channel amplifier of FIG. 1 operating in the comparison phase when the polarity is switched. As shown in FIG. The switch SW3 is closed, and the switches SW1 and SW2 are opened. At this time, the input terminal IN1 of the amplifier 120 is coupled to the output terminal OUT2 of the channel amplifier 100 through the switch SW3, and the output signal Vout on the output terminal OUT2 in the previous buffer stage is It is sent to the input terminal IN1 of the amplifier 120, and the amplifier 120 forms a comparator for comparing the output signal Vout with the input signal IP received by the input terminal IN2 from the digital-to-analog converter 110 at this time, and the comparison result is transmitted to the amplifier 120. The output terminal OUT forms an output signal Vp; in addition, the control circuit 130 controls the multiplexer 150 to disconnect the multiplexer 150 through the control signal CTRL, that is, the multiplexer 150 is no longer coupled to the output terminal OUT of the amplifier 120 and the channel between the output terminals OUT2 of the amplifier 100 . In other words, when the channel amplifier 100 is operating in the comparison stage, the switching circuit 140 and the multiplexer 150 are controlled by the control signal CTRL to transmit the output signal Vout generated on the output terminal OUT2 in the previous buffer stage to the input terminal of the amplifier 120 IN1 is compared with the input signal IP received by the input terminal IN2 of the amplifier 120 at this time, and the comparison result is generated at the output terminal OUT of the amplifier 120, so as to achieve the effect of polarity conversion. When the polarity conversion of the channel amplifier 100 The detailed circuit operation is the same as the embodiment shown in FIG. 2 and FIG. 3 , and those skilled in the art should be able to easily understand the implementation of polarity switching after reading the above paragraphs.

The above descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made according to the claims of the present invention shall fall within the scope of the present invention.

Claims (8)

1. A channel amplifier, comprising:

an amplifier;

a multiplexer coupled between the output of the amplifier and the first output of the channel amplifier;

a switching circuit coupled to the amplifier and the multiplexer; and

a control circuit;

wherein the channel amplifier selectively operates in a buffer phase or a compare phase; when the channel amplifier operates in the buffering stage, the switching circuit couples the output terminal of the amplifier to the first input terminal of the amplifier, so that the first input signal received by the second input terminal of the amplifier is transmitted to the first output terminal of the channel amplifier through the multiplexer; when the channel amplifier operates in the comparison stage, the switching circuit transmits the first input signal at the first output terminal of the channel amplifier to the first input terminal of the amplifier for comparison with a second input signal received at the second input terminal of the amplifier, and outputs a comparison result to the output terminal of the amplifier; and is

The control circuit is configured to transmit a control signal to the multiplexer when the channel amplifier operates in the comparison stage, so that the output terminal of the amplifier is not coupled to the first output terminal of the channel amplifier through the multiplexer, and transmit a control signal to the switching circuit, so that the output terminal of the amplifier is not coupled to the first input terminal of the amplifier.

2. The channel amplifier of claim 1, further comprising:

the digital-to-analog converter is used for generating the first input signal and the second input signal to the second input end of the amplifier.

3. A channel amplifier, comprising:

an amplifier;

a multiplexer coupled between the output of the amplifier and the first output of the channel amplifier;

a switching circuit coupled to the amplifier and the multiplexer; and

a control circuit;

when the multiplexer and the switching circuit receive the control signal and the channel amplifier operates in the buffering stage, the switching circuit couples the output end of the amplifier to the first input end of the amplifier, so that the first input signal received by the second input end of the amplifier is transmitted to the second output end of the channel amplifier through the multiplexer; and is provided with

The control circuit is configured to transmit a control signal to the multiplexer when the channel amplifier operates in the comparison stage, so that the output terminal of the amplifier is not coupled to the first output terminal of the channel amplifier through the multiplexer, and transmit a control signal to the switching circuit, so that the output terminal of the amplifier is not coupled to the first input terminal of the amplifier.

4. The channel amplifier of claim 3, wherein the switching circuit transmits the first input signal received by the second output of the channel amplifier in the buffering stage to the first input of the amplifier for comparison with the second input signal received by the second input of the amplifier and outputs the comparison result to the output of the amplifier when the multiplexer and the switching circuit receive the control signal and when the channel amplifier operates in the comparing stage.

5. A method applied to a channel amplifier, comprising:

selectively operating the channel amplifier in a buffer phase and a compare phase;

transmitting a control signal to the multiplexer; and

coupling an output terminal of an amplifier in the channel amplifier to a first input terminal of the amplifier when the channel amplifier operates in the buffering stage, so that a first input signal received by a second input terminal of the amplifier is transmitted to a first output terminal of the channel amplifier through the multiplexer in the channel amplifier; and

when the channel amplifier is operated in the comparison stage, transmitting the first input signal at the first input terminal of the channel amplifier to the first input terminal of the amplifier for comparison with a second input signal received at the second input terminal of the amplifier, and outputting a comparison result to the output terminal of the amplifier;

when the channel amplifier is operated in the comparison stage, the output end of the amplifier is controlled not to be coupled to the first output end of the channel amplifier through the multiplexer, and the output end of the amplifier is controlled not to be coupled to the first input end of the amplifier.

6. The method of claim 5, further comprising:

performing digital-to-analog conversion to generate the first input signal and the second input signal to the second input terminal of the amplifier.

7. A method applied to a channel amplifier, comprising:

selectively operating the channel amplifier in a buffer phase and a compare phase;

transmitting a control signal to the multiplexer; and

when the multiplexer receives the control signal and the channel amplifier operates in the buffering stage, the output end of the amplifier is coupled to the first input end of the amplifier, so that the first input signal received by the second input end of the amplifier is transmitted to the second output end of the channel amplifier through the multiplexer;

when the channel amplifier is operated in the comparison stage, the output end of the amplifier is controlled not to be coupled to the first output end of the channel amplifier through the multiplexer, and the output end of the amplifier is controlled not to be coupled to the first input end of the amplifier.

8. The method of claim 7, further comprising:

when the multiplexer receives the control signal and the channel amplifier operates in the comparison stage, the switching circuit transmits the first input signal received by the second output terminal of the channel amplifier in the buffering stage to the first input terminal of the amplifier for comparison with the second input signal received by the second input terminal of the amplifier, and outputs the comparison result to the output terminal of the amplifier.

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