CN109585376A - Semiconductor devices and its doping method - Google Patents
Semiconductor devices and its doping method Download PDFInfo
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- CN109585376A CN109585376A CN201811469448.2A CN201811469448A CN109585376A CN 109585376 A CN109585376 A CN 109585376A CN 201811469448 A CN201811469448 A CN 201811469448A CN 109585376 A CN109585376 A CN 109585376A
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- 238000002513 implantation Methods 0.000 claims abstract description 7
- 239000000758 substrate Substances 0.000 claims description 19
- 238000005468 ion implantation Methods 0.000 claims description 11
- 230000000717 retained effect Effects 0.000 claims description 2
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- 238000012545 processing Methods 0.000 description 7
- 239000000243 solution Substances 0.000 description 5
- 238000002955 isolation Methods 0.000 description 3
- 238000004380 ashing Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000000903 blocking effect Effects 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000002156 mixing Methods 0.000 description 2
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- 150000004767 nitrides Chemical class 0.000 description 1
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- 238000001259 photo etching Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
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- 230000000750 progressive effect Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000004062 sedimentation Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
- H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
- H10D84/0144—Manufacturing their gate insulating layers
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
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- H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
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- H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
- H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
- H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
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Abstract
The invention discloses a kind of semiconductor devices and its doping methods, the first etching barrier layer etching based on setting graphic structure is located at the grid layer on high voltage device regions, form first grid, based on first etching barrier layer and the first grid, carry out the first ion implanting, the first doped region is formed in the high voltage device regions, it is used as the exposure mask of the first ion implanting simultaneously using the first etching barrier layer and first grid, higher Implantation Energy when can stop the first ion implanting using the grid layer of lower thickness, to protect the active area of high voltage device regions during the first ion implanting, since grid layer is relatively thin, so that low-voltage device area realizes faster response speed, high voltage device regions and low-voltage device area can be combined, so that the two all has preferable performance, improve the performance of semiconductor devices, make Obtain the better performances of semiconductor devices entirety.
Description
Technical field
The present invention relates to semiconductor devices manufacture technology fields, more specifically, being related to a kind of semiconductor devices and its mixing
Miscellaneous method.
Background technique
With the continuous development of science and technology, more and more electronic equipments are widely used in daily life
And in work, the convenience of office is brought for daily life and work, becomes the indispensable weight of current people
Want tool.
Semiconductor devices is the main element that electronic equipment realizes various functional integrated circuits.Some functional circuits, such as electricity
Power management circuits or storage circuit need to use while having high tension apparatus to realize set-up function and performance parameter
The semiconductor devices of (such as high-pressure MOS) function and low-voltage device (low pressure MOS).It is needed in this way in same semiconductor device one
Integrated high voltage device region and low-voltage device area, to realize the function of high tension apparatus and the function of low-voltage device respectively.
The prior art is when making above-mentioned semiconductor device, and during forming light-duty doped drain, high voltage device regions are needed
Biggish energy injection is stopped using the grid layer of larger thickness, to protect the active area of high tension apparatus, but contradiction therewith
, low-voltage device area part needs to realize faster response device speed using relatively thin grid layer, in order to solve this problem, existing
There is technology, the thickness of a compromise is usually used in grid layer, which, which is less than high voltage device regions, needs that large energy is stopped to be infused
The optimal thickness entered will lead to high pressure greater than the optimal thickness that low-voltage device area needs to realize very fast response device speed in this way
The performance in device region and low-voltage device area has certain reduction, so that the overall performance of semiconductor devices is poor.
Summary of the invention
To solve the above-mentioned problems, technical solution of the present invention provides a kind of semiconductor devices and its doping method, improves
The performance of semiconductor devices.
To achieve the goals above, the invention provides the following technical scheme:
A kind of doping method of semiconductor devices, the doping method include:
One substrate is provided, there is high voltage device regions and low-voltage device area in the first surface of the substrate, described first
It is covered with gate dielectric layer on surface, is covered with grid layer on the surface of the gate dielectric layer；
The grid layer surface above the high voltage device regions forms the first etching resistance with the first graphic structure
Barrier；
Based on first etching barrier layer, the grid layer above the high voltage device regions is etched, forms the first grid
Pole；
Based on first etching barrier layer and the first grid, the first ion implanting is carried out, in the high-voltage device
The first doped region is formed in part area.
Preferably, in above-mentioned doping method, after forming first doped region, further includes:
Remove first etching barrier layer；
The grid layer surface above the low-voltage device area forms the second etching resistance with second graph structure
Barrier；
Based on second etching barrier layer, the grid layer above the low-voltage device area is etched, forms second gate
Pole；
Remove second etching barrier layer；
Based on the second grid, the second ion implanting is carried out, forms the second doped region in the low-voltage device area.
Preferably, in above-mentioned doping method, the grid layer on the high voltage device regions, which is formed, has the
First etching barrier layer of one graphic structure, comprising:
Not patterned first etching barrier layer is formed, the surface of the grid layer is covered；
Processing is patterned to first etching barrier layer, forms first etch stopper with the first graphic structure
Layer, the first etching barrier layer with the first graphic structure include first part and second part, and first part covers institute
First grid region is stated, second part covering is located at the grid layer region in the low-voltage device area.
Preferably, described to be based on first etching barrier layer in above-mentioned doping method, etch the high voltage device regions
The grid layer of top forms first grid, comprising:
The grid layer above the high voltage device regions is etched, the first part for retaining first etching barrier layer is covered
The part of grid pole layer of lid, as the first grid.
Preferably, described to be based on first etching barrier layer and the first grid in above-mentioned doping method, into
The first ion implanting of row, forms the first doped region in the high voltage device regions, comprising:
First ion implanting is carried out to the high voltage device regions, with the first grid and is covered described in its surface
Exposure mask of the first part of first etching barrier layer as first ion implanting, to form first doped region.
Preferably, in above-mentioned doping method, the grid layer surface above the low-voltage device area is formed
The second etching barrier layer with second graph structure, comprising:
Not patterned second etching barrier layer is formed, covers the first grid, first doped region top is exposed
The gate dielectric layer and the low-voltage device area above grid layer 24；
Processing is patterned to second etching barrier layer, forms second etch stopper with second graph structure
Layer, the second etching barrier layer with second graph structure include first part and second part, and first part covers institute
State second grid region, the grid that second part covers the first grid, high voltage device regions top is exposed
Dielectric layer.
Preferably, described to be based on second etching barrier layer in above-mentioned production method, etch the low-voltage device area
The grid layer of top forms second grid, comprising:
The grid layer in the low-voltage device area is etched, first part's covering of second etching barrier layer is retained
Part of grid pole layer, as the second grid.Preferably, in above-mentioned doping method, the gate dielectric layer includes covering institute
State the high pressure gate dielectric layer of high voltage device regions and the low pressure gate dielectric layer in the covering low-voltage device area, the high pressure gate medium
The thickness of layer is greater than the thickness of the low pressure gate dielectric layer.
Preferably, in above-mentioned doping method, the thickness of the grid layer is less than
The present invention also provides a kind of semiconductor devices, the semiconductor devices includes:
Substrate, the substrate have first surface；
High voltage device regions and low-voltage device area in the first surface；
Cover the gate dielectric layer of the first surface；
First grid and second grid on the gate dielectric layer, first grid are positioned over the high tension apparatus
The gate dielectric layer surface in area, the second grid are positioned over the gate dielectric layer surface in the low-voltage device area；
Wherein, the first grid is formed based on the first etching barrier layer etching grid layer with the first graphic structure,
It is formed based on first etching barrier layer with the first graphic structure and the first ion implanting of first grid progress described
First doped region.
Preferably, in above-mentioned semiconductor device, the injection depth of the high voltage device regions is greater than the low-voltage device area
Injection depth；There is the first doped region, the low-voltage device area has the second doped region in the high voltage device regions.
Preferably, in above-mentioned semiconductor device, the thickness of the first grid layer is less than
As can be seen from the above description, in the semiconductor devices and its doping method that technical solution of the present invention provides, based on tool
There is the first etching barrier layer etching of the first graphic structure to be located at the grid layer on high voltage device regions, forms first grid, be based on
First etching barrier layer and the first grid carry out the first ion implanting, and the is formed in the high voltage device regions
One doped region, in this way, be used as the exposure mask of the first ion implanting simultaneously using the first etching barrier layer and first grid, using compared with
The grid layer of thin thickness higher Implantation Energy when can stop the first ion implanting, to be protected during the first ion implanting
Protect the active area (region of high voltage device regions face first grid) of high voltage device regions.Meanwhile it can also pass through in subsequent process
The grid layer with lower thickness forms the second grid in low-voltage device area, so that low-voltage device area realizes faster response
Speed, it is seen that technical solution of the present invention can combine high voltage device regions and low-voltage device area so that the two all have compared with
Good performance, improves the performance of semiconductor devices, so that the better performances of semiconductor devices entirety.
Detailed description of the invention
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below
There is attached drawing needed in technical description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this
The embodiment of invention for those of ordinary skill in the art without creative efforts, can also basis
The attached drawing of offer obtains other attached drawings.
Fig. 1-Fig. 4 is a kind of process flow chart of the doping method of semiconductor devices in the prior art；
Fig. 5-Fig. 9 is a kind of flow diagram of doping method provided in an embodiment of the present invention；
Figure 10-Figure 17 is the process flow chart of another doping method provided in an embodiment of the present invention.
Specific embodiment
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation description, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.It is based on
Embodiment in the present invention, it is obtained by those of ordinary skill in the art without making creative efforts every other
Embodiment shall fall within the protection scope of the present invention.
With reference to Fig. 1-Fig. 4, Fig. 1-Fig. 4 is a kind of flow diagram of the doping method of semiconductor devices in the prior art,
The semiconductor devices is integrated with integrated high voltage device regions and low-voltage device area, which includes:
Firstly, as shown in Figure 1, providing a substrate 11.Be formed in the first surface of substrate 11 high voltage device regions 121 with
And low-voltage device area 122.First surface is covered with gate dielectric layer 13, and 13 surface of gate dielectric layer is covered with grid layer 14.It is being formed
Before grid layer 14, substrate 11 first surface formed shallow trench, the filled media material in shallow trench, formed shallow trench every
From structure 16.After forming grid layer 14, the first etching barrier layer 15 of preset pattern structure is formed on grid layer 14.
Then, it as shown in Fig. 2, being based on the equal 15 etching grid layer 14 of the first etching barrier layer, is formed and is located at high voltage device regions
First grid 141 on 121 and the second grid in low-voltage device area 122 142 remove the first etch stopper later
Layer 15.
Again as shown in figure 3, forming the second etching barrier layer 17 of preset pattern structure, the second etching barrier layer 17 covering the
The gate dielectric layer 13 exposed on two grids 142 and low-voltage device area carries out ion implanting, in high voltage device regions 121 later
The first doped region D1 is formed, then removes the second etching barrier layer 17.There are two the first doping for tool in same high tension apparatus region 121
Area D1, lightly doped drain (LDD) respectively as high tension apparatus and is lightly doped source region (LDS).
Again as shown in figure 4, forming the third etching barrier layer 18 of preset pattern, third etching barrier layer 18 covers the first grid
The gate dielectric layer 13 exposed on pole 141 and high voltage device regions carries out ion implanting, the shape in low-voltage device area 122 later
At the second doped region D2 finally, removal third etching barrier layer 18.The injection depth of second doped region D2 is less than the first doped region
The injection depth of D1.There are two the second doped region D2 for tool in same low-voltage device region 122, respectively as gently mixing for low-voltage device
It miscellaneous drain region (LDD) and is lightly doped source region (LDS).
As it can be seen that, in the biggish first doped region D1 of formation injection depth, being only through in the mode shown in Fig. 1-Fig. 4
First grid 141 is used as exposure mask, in order to stop larger Implantation Energy, the grid layer 14 using larger thickness is needed, such as background skill
Described in art, grid layer 14 stops the larger Implantation Energy in high voltage device regions and realizes low-voltage device area compared with fast-response speed in order to balance
The demand of degree, grid layer 14 are needed using compromise thickness.In general, in order to preferably stop the larger injection energy in high voltage device regions
Amount, needs 14 thickness of grid layer to be greater thanAnd in order to realize that low-voltage device area has faster response speed, need grid
The thickness of pole layer 14 is less thanAnd compromise thickness in the prior art is usuallyIn this way, will lead to high-voltage device
The equal decrease to some degree of performance in part area and low-voltage device area, so that the overall performance of semiconductor devices is poor.
To solve the above-mentioned problems, it the embodiment of the invention provides a kind of semiconductor devices and its doping method, simplifies
Manufacture craft reduces the production cost, and can also combine the performance of high voltage device regions and low-voltage device area, improves semiconductor
The overall performance of device.
In order to make the foregoing objectives, features and advantages of the present invention clearer and more comprehensible, with reference to the accompanying drawing and specific real
Applying mode, the present invention is described in further detail.
With reference to Fig. 5-Fig. 9, Fig. 5-Fig. 9 is a kind of process flow chart of doping method provided in an embodiment of the present invention, this is mixed
Miscellaneous method is used for semiconductor devices, which includes the high voltage device regions integrated and low-voltage device area, the doping
Method includes:
Step S11: as shown in figure 5, providing a substrate 21.
There is high voltage device regions 221 and low-voltage device area 222, the first surface in the first surface of the substrate 21
On be covered with gate dielectric layer 23, be covered with grid layer 24 on the surface of the gate dielectric layer 23.Gate dielectric layer 23 can be raw for heat
Long oxide layer or high-temperature oxydation nitride layer.Gate dielectric layer 23 includes high pressure gate dielectric layer 231 and low pressure gate dielectric layer 232.It is high
Gate dielectric layer 231 is pressed to cover the surface of high voltage device regions 221, low pressure gate dielectric layer 232 covers the surface in low-voltage device area 222.
The thickness of high pressure gate dielectric layer 231 is greater than the thickness of low pressure gate dielectric layer 232.Grid layer 24 on high voltage device regions 221
It is same layer structure with the grid layer 24 being located in low-voltage device area 222, thickness is identical.Grid layer 24 can be polysilicon.Institute
It states and is also formed with fleet plough groove isolation structure 26 on substrate 21.
Ion implantation technology as substrate 21, can first passed through in the first surface of substrate 21 using semiconductor crystal wafer
High voltage device regions 221 are formed, form high pressure gate dielectric layer 231 on the surface of high voltage device regions 221.Pass through etching technics shape again
At shallow trench, filled media is formed in shallow trench, and then forms fleet plough groove isolation structure 26.Again in the first surface of substrate 21
Interior formed by ion implantation technology is located at low-voltage device area 222, and low pressure gate medium is formed on the surface in low-voltage device area 222
Layer 232.The more of the high pressure gate dielectric layer 231 and the low pressure gate dielectric layer 232 are covered finally, being formed by depositing operation
Crystal silicon, as grid layer 24.
High voltage device regions 221, low-voltage device area 222, fleet plough groove isolation structure 26, gate dielectric layer 23 are formed based on substrate 21
And the concrete technology method of grid layer 24 can be set according to demand, the embodiment of the present invention is not especially limited.
Wherein, high voltage device regions 221 and low-voltage device area 222 are the different active area of doping concentration parameter.
Step S12: as shown in Figure 6 and Figure 7, the grid layer surface above the high voltage device regions, which is formed, has the
First etching barrier layer of one graphic structure.
In the step, 24 surface of the grid layer above the high voltage device regions 221, which is formed, has the first figure
First etching barrier layer 25 of shape structure, comprising:
Firstly, first etching barrier layer 25 covers institute as shown in fig. 6, forming not patterned first etching barrier layer 25
State the surface of grid layer 24.
Then, as shown in fig. 7, being patterned processing to first etching barrier layer 25, being formed has the first figure
First etching barrier layer 25 of structure, with the first graphic structure the first etching barrier layer 25 include first part 251 and
Second part 252, first part 251 cover 241 region of first grid, and the covering of second part 252 is located at described low
24 region of the grid layer on voltage device region 222.The process does not etch the first etching barrier layer 25 and is located at low-voltage device
The part (second part 252) of 222 top of area, the first etching barrier layer 25 of etching are located at the part of 221 top of high voltage device regions,
Retain first etching barrier layer of part (first part 251) on 241 region surface of first grid.
In the embodiment of the present invention, each etching barrier layer is photoresist layer, and graphical treatment includes traditional exposure and shows
Shadow processing.
Step S13: as shown in figure 8, being based on first etching barrier layer 25,221 top of high voltage device regions is etched
The grid layer 24, formed first grid 241.
It is described to be based on first etching barrier layer 25 in the step, etch the described of 221 top of high voltage device regions
Grid layer 24 forms first grid 241, comprising: the grid layer 24 for etching 221 top of high voltage device regions retains institute
The part of grid pole layer that the first part 251 of the first etching barrier layer 25 covers is stated, as the first grid 241.Set the step
Etching in rapid is to etch for the first time, is etched by first time, the grid layer 24 of graphical 221 top of high voltage device regions, in height
First grid 241 is formed above voltage device region 221.
Step S14: as shown in figure 9, being based on first etching barrier layer 25 and the first grid 241, the is carried out
One ion implanting forms the first doped region D1 in the high voltage device regions 221.
It is described to be based on first etching barrier layer 25 and the first grid 241 in the step, carry out the first ion
Injection, forms the first doped region D1 in the high voltage device regions 221, comprising: carries out described the to the high voltage device regions 221
One ion implanting, with the first part 251 of the first grid 241 and first etching barrier layer 25 for covering its surface work
For the exposure mask of first ion implanting, to form the first doped region D1.
With reference to Figure 10-Figure 17, Figure 10-Figure 17 is the process flow of another doping method provided in an embodiment of the present invention
Figure, the doping method after forming the first doped region D1, further comprise on the basis of above-mentioned doping method:
Step S15: as shown in Figure 10, first etching barrier layer 25 is removed.
Ashing can be passed sequentially through and wet-cleaning removes first etching barrier layer 25, is i.e. removal first part
251 and second part 252.
As preferred embodiment, semiconductor devices can be set to two high voltage device regions 221, and one kind is N-type high pressure
Device region, another kind are p-type high voltage device regions.N-type high voltage device regions and p-type high voltage device regions need respectively through a Fig. 8-
Process shown in Figure 10 to form corresponding first grid 241 and the first doped region D1, then executes subsequent step, is formed
The second grid 242 in low-voltage device area 222.Be only in the embodiment of the present invention by taking a kind of forming process of high voltage device regions as an example into
Row explanation.
Step S16: as is illustrated by figs. 11 and 12, the grid layer surface above the low-voltage device area 222 is formed
The second etching barrier layer 27 with second graph structure.
In the step, the grid layer surface above the low-voltage device area 222, which is formed, has second graph
Second etching barrier layer 27 of structure, comprising:
Firstly, as shown in figure 11, forming not patterned second etching barrier layer 27, the second etching barrier layer 27 covers institute
It states in first grid 241, the gate dielectric layer 23 that the top the first doped region D1 is exposed and the low-voltage device area 222
Side grid layer 24, that is to say, that at this point, the second etching barrier layer 27 covering by first time etch after grid layer 24 and its
The gate dielectric layer 23 of exposing.
Then, as shown in figure 12, processing is patterned to second etching barrier layer 27, being formed has second graph
Second etching barrier layer 27 of structure, with second graph structure the second etching barrier layer 27 include first part 271 and
Second part 272, first part 271 cover 242 region of second grid, and second part 272 covers the first grid
The gate dielectric layer 23 exposed above pole 241, the high voltage device regions 221.The etching process does not etch the second etch stopper
Layer 27 is located at the part (second part 272) of 221 top of high voltage device regions, and the second etching barrier layer 27 of etching is located at low-voltage device
The part of 222 top of area, retains second etching barrier layer of part (first part 271) on 242 region surface of second grid.
Step S17: as shown in figure 13, being based on second etching barrier layer 27, etches 222 top of low-voltage device area
The grid layer 24, formed second grid 242.
It is described to be based on second etching barrier layer in the step, etch the grid above the low-voltage device area
Layer 24 forms second grid 242, comprising: etches the grid layer in the low-voltage device area, retains the second etching resistance
The part of grid pole layer of first part's covering of barrier, as the second grid.The etching set in the step is carved as second
Erosion is etched by second, the grid layer 24 of graphical 222 top of low-voltage device area, and the is formed above low-voltage device area 222
Two grids 242.
Step S18: as shown in figure 14, second etching barrier layer 27 is removed.
In the step, the minimizing technology of the second etching barrier layer 27 is identical as the first etching barrier layer process of removal,
It passes sequentially through ashing and wet-cleaning removes second etching barrier layer 27.It, can be with after removing the second etching barrier layer 27
Oxidation processes are carried out to grid layer 24, grid layer 24 is etched by etching for the first time and second, and etching surface has defect, leads to
Peroxidating processing, eliminates surface defect.
Equally, as preferred embodiment, semiconductor devices can be set to Liang Ge low-voltage device area 222, and one kind is N-type
Low-voltage device area, another kind are p-type low-voltage device area.Liang Zhong low-voltage device area 222 can pass through the second etch stopper of same layer
Layer 27, to form respective second grid 241.
Step S19: as shown in Figure 15 and Figure 16, it is based on the second grid 242, the second ion implanting is carried out, described
The second doped region D2 is formed in low-voltage device area 222.
In the step, it is based on the second grid 242, carries out the second ion implanting, the shape in the low-voltage device area 222
Include: at the second doped region D2
Firstly, as shown in figure 15, forming the third etching barrier layer 28 with third graphic structure.Specifically, being initially formed
Not patterned third etching barrier layer 28, when not graphical, third etching barrier layer covers first grid 241 and second gate
Pole, and cover the gate dielectric layer 23 that the grid layer 24 after first time etching and second etch exposes.Again by
Three etching barrier layers 28 are patterned processing, form the third etching barrier layer 28 with third graphic structure, graphical to locate
After reason, third etching barrier layer 28 covers the gate dielectric layer 23 of first grid 241 and the top of high voltage device regions 221, exposes the
The gate dielectric layer 23 of 222 top of two grids 242 and low-voltage device area.The exposure development technology pattern of photoetching process can be passed through
Change the third etching barrier layer 28.
Then, it is that exposure mask carries out the second ion implanting with second grid 242, forms second in low-voltage device area 222 and mix
Miscellaneous area D2.
The energy of first ion implanting is greater than the energy of the second ion implanting, and the depth of the first doped region D1 of formation is greater than
The depth of second doped region D2.
Such as above-mentioned as preferred embodiment, semiconductor devices can have Liang Ge low-voltage device area 222, and one kind is N-type
Low-voltage device area, another kind are p-type low-voltage device area, therefore Liang Zhong low-voltage device area 222 needs to carry out ion implanting respectively, therefore two
Kind low-voltage device area 222 needs to carry out ion implanting respectively, and N-type low-voltage device area and p-type low-voltage device area need to pass through respectively
Process shown in Figure 15-Figure 17, to form corresponding second doped region D2.It is only with a kind of low in the embodiment of the present invention
It is illustrated for the forming process of the corresponding second doped region D2 in voltage device region.
As can be seen from the above description, in doping method provided in an embodiment of the present invention, pass through the first etching barrier layer 25
First part 251 forms first grid 241, first part 251 and first grid 241 by the first etching barrier layer 251
It is used as exposure mask simultaneously, forms the first doped region D1, it is only necessary to which the grid layer 24 of lower thickness can both be blocked in high voltage device regions
The 221 larger ion implantation energies carried out, that is, realize the blocking demand of the larger ion implantation energy in high voltage device regions 221, together
When realize using relatively thin grid layer 24 formed second grid 242, realize the rapid response to customer's need in low-voltage device area 222, make
It obtains high voltage device regions 221 and low-voltage device area 222 all has preferable performance, ensure that semiconductor devices integrally has preferably
Performance.
Although the more excellent value of the gate layer thickness that integrated low-voltage device needs has standard in the industry, pass through above-mentioned compromise
When Thickness Mode makes semiconductor devices, for setting the semiconductor devices of technological parameter, need repeatedly to make test to select
One thickness of preferably compromising, causes cost of manufacture higher, and technical scheme can satisfy the grid of low-voltage device needs
Standard, the relatively macroion Implantation Energy blocking of high voltage device regions can pass through grid layer and its surface to the more excellent value of thickness degree in the industry
The first etching barrier layer realize, determine this thickness without repeatedly production test, reduce the production cost.The embodiment of the present invention
In, the thickness of the grid layer 24 can be made to be less thanSuch as can beOrOr
Technical solution of the present invention integrates high voltage device regions and low-voltage device area by relatively thin grid layer, and improving, semiconductor devices is whole
While body performance, relatively thin grid layer is prepared, the use of the sedimentation time and material of grid layer can be reduced, improved efficiency,
It further reduces the cost.
Based on the above embodiment, another embodiment of the present invention additionally provides a kind of semiconductor devices, as shown in figure 17, described
Semiconductor devices includes: substrate 21, and the substrate 21 has first surface；High voltage device regions in the first surface
221 and low-voltage device area 222；Cover the gate dielectric layer 23 of the first surface；First on the gate dielectric layer 23
Grid 241 and second grid 242, first grid 241 are positioned over 23 surface of gate dielectric layer of the high voltage device regions 221,
The second grid 242 is positioned over 23 surface of gate dielectric layer in the low-voltage device area 222.
Wherein, the first grid is formed based on the first etching barrier layer etching grid layer with the first graphic structure
241, based on the first etching barrier layer and the first ion implanting shape of progress of the first grid 241 with the first graphic structure
At the first doped region D1.In this way, first grid 241 and second grid can be prepared using the grid layer of lower thickness
242, by the first etching barrier layer and first grid 241 simultaneously as the exposure mask for forming the first doped region D1, in reality
While existing high voltage device regions 221 stop larger ion implantation energy demand, the quick sound in low-voltage device area 222 can also be realized
Answer demand.
The first grid 241 and the second grid 242 are prepared by same grid layer；The high voltage device regions 221
Injection depth be greater than the low-voltage device area 222 injection depth；The low-voltage device area 222 has the second doped region D2.
Optionally, the first grid 241 and the second grid 242 are prepared by same grid layer.
Optionally, the thickness of the first grid layer is less thanThe semiconductor devices includes two kinds of high voltage device regions
221, one kind is N-type high voltage device regions, and another kind is p-type high voltage device regions.There are respective correspondence in two kinds of high voltage device regions 221 respectively
First grid 241 and the first doped region D1.Equally, which includes Liang Zhong low-voltage device area 222, and one kind is N
Type low-voltage device area, another kind are p-type low-voltage device area.There is corresponding second grid in Liang Zhong low-voltage device area 222 respectively
The 242 and second doped region D2.It is only to show a kind of high voltage device regions 221 and a kind of low-voltage device area 222 in Figure 17.
What the structure of semiconductor devices described in the embodiment of the present invention can be formed with reference to doping method described in above-described embodiment
Semiconductor device structure, details are not described herein.
Each embodiment in this specification is described in a progressive manner, the highlights of each of the examples are with other
The difference of embodiment, the same or similar parts in each embodiment may refer to each other.For partly being led disclosed in embodiment
For body device, since it is corresponding with doping method disclosed in embodiment, so be described relatively simple, related place referring to
Doping method part explanation.
It should also be noted that, herein, relational terms such as first and second and the like are used merely to one
Entity or operation are distinguished with another entity or operation, without necessarily requiring or implying between these entities or operation
There are any actual relationship or orders.Moreover, the terms "include", "comprise" or its any other variant are intended to contain
Lid non-exclusive inclusion, so that article or equipment including a series of elements not only include those elements, but also
It including other elements that are not explicitly listed, or further include for this article or the intrinsic element of equipment.Do not having
In the case where more limitations, the element that is limited by sentence "including a ...", it is not excluded that in the article including above-mentioned element
Or there is also other identical elements in equipment.
The foregoing description of the disclosed embodiments enables those skilled in the art to implement or use the present invention.
Various modifications to these embodiments will be readily apparent to those skilled in the art, as defined herein
General Principle can be realized in other embodiments without departing from the spirit or scope of the present invention.Therefore, of the invention
It is not intended to be limited to the embodiments shown herein, and is to fit to and the principles and novel features disclosed herein phase one
The widest scope of cause.
Claims (11)
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| CN111370371A (en) * | 2020-03-18 | 2020-07-03 | 长江存储科技有限责任公司 | A kind of preparation method of semiconductor device |
| CN111863724A (en) * | 2019-04-24 | 2020-10-30 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and method of forming the same |
| CN112103347A (en) * | 2020-11-17 | 2020-12-18 | 晶芯成(北京)科技有限公司 | Method for manufacturing semiconductor structure |
| CN112366179A (en) * | 2020-10-15 | 2021-02-12 | 长江存储科技有限责任公司 | Semiconductor device structure and preparation method |
| CN112968056A (en) * | 2021-02-23 | 2021-06-15 | 长江存储科技有限责任公司 | Semiconductor structure and manufacturing method thereof |
| CN113488537A (en) * | 2021-05-26 | 2021-10-08 | 武汉新芯集成电路制造有限公司 | Semiconductor device and method of forming the same |
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| CN113809009A (en) * | 2021-09-18 | 2021-12-17 | 长江存储科技有限责任公司 | Method of forming polysilicon gate and semiconductor device including the same |
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