CN109561574B - Impedance test, circuit board processing, circuit board production method and test assembly - Google Patents
Impedance test, circuit board processing, circuit board production method and test assembly Download PDFInfo
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- CN109561574B CN109561574B CN201811585856.4A CN201811585856A CN109561574B CN 109561574 B CN109561574 B CN 109561574B CN 201811585856 A CN201811585856 A CN 201811585856A CN 109561574 B CN109561574 B CN 109561574B
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- 238000012360 testing method Methods 0.000 title claims abstract description 155
- 238000012545 processing Methods 0.000 title claims abstract description 17
- 238000004519 manufacturing process Methods 0.000 title abstract description 14
- 238000001514 detection method Methods 0.000 claims abstract description 122
- 238000003672 processing method Methods 0.000 claims abstract description 5
- 238000005530 etching Methods 0.000 claims description 16
- 238000000034 method Methods 0.000 claims description 15
- 238000003475 lamination Methods 0.000 claims description 12
- 238000010030 laminating Methods 0.000 claims description 11
- 239000000463 material Substances 0.000 claims description 3
- 239000002994 raw material Substances 0.000 claims description 3
- 238000007689 inspection Methods 0.000 claims 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 abstract description 17
- 229910052802 copper Inorganic materials 0.000 abstract description 15
- 239000010949 copper Substances 0.000 abstract description 15
- 230000008021 deposition Effects 0.000 abstract description 13
- 238000009713 electroplating Methods 0.000 abstract description 12
- 238000010998 test method Methods 0.000 abstract description 10
- 238000010586 diagram Methods 0.000 description 4
- 239000011889 copper foil Substances 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 238000005259 measurement Methods 0.000 description 2
- 238000012544 monitoring process Methods 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 238000002360 preparation method Methods 0.000 description 2
- 238000004904 shortening Methods 0.000 description 2
- 238000013519 translation Methods 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000005553 drilling Methods 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 238000003384 imaging method Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 238000004080 punching Methods 0.000 description 1
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0266—Marks, test patterns or identification means
- H05K1/0268—Marks, test patterns or identification means for electrical inspection or testing
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
- H05K1/0218—Reduction of cross-talk, noise or electromagnetic interference by printed shielding conductors, ground planes or power plane
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/115—Via connections; Lands around holes or via connections
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Electromagnetism (AREA)
- Structure Of Printed Boards (AREA)
- Measurement Of Resistance Or Impedance (AREA)
Abstract
The invention relates to an impedance test method, a circuit board processing method, a circuit board production method and a test assembly, wherein the impedance test method comprises the following steps: s110, providing a test circuit board, wherein the test circuit board is provided with a first detection hole, a second detection hole, a first shielding layer, an impedance line and a second shielding layer which are sequentially arranged in a spacing and stacking mode; s120, a first conductive column is arranged in the first detection hole and is in conductive connection with the first shielding layer and the second shielding layer; a second conductive column is arranged in the second detection hole and electrically connected with the impedance line; s130, testing the impedance between the first conductive column and the second conductive column; the first conductive column can be used as a testing end for conducting and connecting the first shielding layer and the second shielding layer, and the second conductive column can be used as a testing end for the impedance line, so that the processing time of copper deposition electroplating of the first detection hole and the second detection hole can be saved, and the impedance testing period of the testing circuit board can be further shortened.
Description
Technical Field
The invention relates to the technical field of circuit board impedance testing, in particular to an impedance testing method, a circuit board processing method, a circuit board production method and a testing assembly.
Background
Along with the development of a signal circuit to high speed, the high-speed electronic product has higher and higher requirements on the impedance precision of a printed circuit board, and the high-precision impedance not only requires a set of complete high-precision design method and strict production control requirements, but also requires that impedance data can be timely and accurately monitored. In current impedance monitoring, an impedance connection strip (coupoun) with the same line width, copper thickness, dielectric thickness and lamination structure as the in-board impedance line design is commonly used in impedance control of a conventional circuit board to reflect the impedance situation in a graph. Because the impedance test needs to measure an open-circuit impedance line without a network and a corresponding bottom layer, in the current impedance connecting bar (coupoun) test, the measurement and the monitoring of the impedance of the inner layer can be carried out only after the outer layer is etched. Then, in the processing of the circuit board, the outer layer etching procedure is close to the end sound relative to the whole processing flow, and a plurality of procedures are carried out between the complete forming (laminating procedure) of the inner layer impedance transmission line structure and the outer layer etching, wherein the procedures comprise drilling, glue removing, plasma, plate drying, copper deposition, electroplating, outer layer light imaging and the like, and the required time is long. Particularly, when the first plate monitors the inner layer impedance, the measurement can be carried out only after the outer layer etching is finished, if the inner layer impedance cannot be monitored in time, and when the inner layer impedance is detected to be unqualified after the outer layer etching, the production delivery cycle and the processing cost are greatly lost.
Disclosure of Invention
Based on the above, the invention provides an impedance test method to overcome the defects of the prior art, and solves the problem of long impedance test period; the circuit board processing method improves the impedance test precision; the circuit board production method shortens the production delivery cycle; and the test component solves the problem of long impedance test period.
An impedance testing method comprising the steps of: s110, providing a test circuit board, wherein the test circuit board is provided with a first detection hole, a second detection hole, a first shielding layer, an impedance line and a second shielding layer which are sequentially arranged in a spacing and stacking mode; s120, a first conductive column is arranged in the first detection hole and is in conductive connection with the first shielding layer and the second shielding layer; a second conductive column is arranged in the second detection hole and electrically connected with the impedance line; and S130, testing the impedance between the first conductive pillar and the second conductive pillar.
Compared with the mode that the first shielding layer and the second shielding layer are in conductive connection by generally adopting copper deposition and electroplating of the inner wall of the first detection hole and the mode that the impedance line test end is led out by copper deposition and electroplating of the second detection hole, the first conductive column can be used as the test end for conductive connection of the first shielding layer and the second shielding layer, and the second conductive column can be used as the test end for the impedance line, so that the processing time for electroplating the first detection hole and the second detection hole by copper deposition can be saved, and the impedance test period of the test circuit board can be further shortened.
In one embodiment, the S130, testing the impedance between the first conductive pillar and the second conductive pillar specifically includes the following steps: and the first test port is electrically connected with the first conductive column and the impedance tester, the second test port is electrically connected with the second conductive column and the impedance tester, and the test value of the impedance tester is read. In the impedance test, the first test port and the second test port of the impedance tester are electrically connected with the first conductive column and the second conductive column to test the impedance of the circuit board in a simple mode, and the impedance tester and the test circuit board can be ensured to be electrically connected well by controlling the first test port and the first conductive column and the second test port and the second conductive column to be electrically connected well.
A circuit board processing method comprises the following steps: s210, providing a circuit board, wherein the circuit board is provided with a first shielding layer, an impedance line and a second shielding layer which are sequentially arranged in a spacing and stacking mode; s220, arranging a first target for positioning a first detection hole and a second target for positioning a second detection hole on the circuit board; and S230, forming a first detection hole on the circuit board according to the position of the first target and forming a second detection hole on the circuit board according to the position of the second target so as to obtain the test circuit board applied to the impedance test method. The mode of locating the first detection hole by the first target and locating the second detection hole by the second target can improve the hole opening precision of the first detection hole and the second detection hole, and further ensure that the first conductive column, the second conductive column, the first shielding layer, the impedance line and the second shielding layer are reliably electrically connected in the impedance test.
In one embodiment, the step S220 of arranging the first target for positioning the first detection hole and the second target for positioning the second detection hole on the circuit board specifically includes the following steps: and arranging a first target and a second target which are on the same layer with the impedance line in the circuit board, wherein the first target and the second target both correspond to the impedance line. Because the first target and the second target both correspond to the impedance line, the position relation between the first detection hole and the impedance line, the second detection hole and the impedance line can be controlled, and the reliability of the impedance test can be ensured.
In one embodiment, the step S220 of providing the first target for positioning the first detection hole and the target for positioning the second detection hole on the circuit board further includes the following steps: the third target and the fourth target which are on the same layer as the first shielding layer are arranged in the circuit board, the fifth target and the sixth target which are on the same layer as the second shielding layer are arranged in the circuit board, the third target corresponds to the first target and is used for positioning the first detection hole, the fourth target corresponds to the second target and is used for positioning the second detection hole, the fifth target corresponds to the first target and is used for positioning the first detection hole, and the sixth target corresponds to the second target and is used for positioning the second detection hole. The hole opening precision of the first detection hole and the second detection hole can be guaranteed by the mode that the first target, the third target and the fifth target are used for opening the first detection hole and the second target, the fourth target and the sixth target are used for opening the second detection hole.
In one embodiment, the first, third and fifth targets are stacked in a stack, and the second, fourth and sixth targets are stacked in a stack. The lamination translation condition among the first shielding layer, the impedance line and the second shielding layer can be judged by observing the corresponding lamination condition of the first target, the third target and the fifth target and the corresponding lamination condition of the second target, the fourth target and the sixth target, and then the opening positions of the first detection hole and the second detection hole are controlled, so that the accuracy of the impedance test is ensured.
In one embodiment, the step S230 of opening a first detection hole on the circuit board according to the position of the first target and opening a second detection hole on the circuit board according to the position of the second target specifically includes the following steps: the first detection hole which penetrates through the first target, the third target and the fifth target is formed in the circuit board by adopting an X-ray; and arranging a second detection hole which penetrates through the second target, the fourth target and the sixth target on the circuit board by adopting an X-ray. When the first detection hole and the second detection hole are processed by using the X-ray punching, the position relation among the first shielding layer, the impedance line and the second shielding layer can be observed by using the X-ray, and the hole opening precision of the first detection hole and the second detection hole can be further improved.
A test assembly applied to the impedance test method comprises a first conductive column and a second conductive column, wherein the first conductive column is installed in a first detection hole and is in conductive connection with a first shielding layer and a second shielding layer, and the second conductive column is installed in a second detection hole and is electrically connected with an impedance line.
The test assembly comprises a first conductive column, a second conductive column, a first shielding layer, a second shielding layer, an impedance line, a first conductive hole, a second detection hole, an impedance line and a test end, wherein the first conductive column is arranged in the first detection hole and is in conductive connection with the first shielding layer and the second shielding layer, the second conductive column is electrically connected with the impedance line, the impedance test of the test circuit board can be completed by testing the impedance between the first conductive column and the second conductive column, compared with the mode that the first shielding layer and the second shielding layer are in conductive connection by generally adopting copper deposition and electroplating of the inner wall of the first detection hole and the test end of the impedance line is led out by the copper deposition and electroplating of the second detection hole, the first conductive column can be used as the test end of the impedance line, so that the processing time of the copper deposition and electroplating of the first detection hole and the.
In one embodiment, a first insulating layer corresponding to the first shielding layer and a second insulating layer corresponding to the second shielding layer are disposed on the second conductive pillars, the second conductive pillars are insulated from the first shielding layer by the first insulating layer, and the second conductive pillars are insulated from the second shielding layer by the second insulating layer. In the impedance test, the first conductive columns can be insulated from the impedance lines by arranging the first test holes deviating from the impedance lines, and the second conductive columns can be insulated from the first shielding layer and the second shielding layer by the first insulating layer and the second insulating layer.
A circuit board production method comprises the following steps: s310, producing all layers of materials forming the finished circuit board in batches according to the finished circuit board; s320, preparing a test circuit board according to the preset etching parameters and the preset laminating parameters; s330, performing impedance test on the test circuit board by using the impedance test method of any one of claims 1-2; when the impedance test of the sample test circuit board is qualified, the etching parameters and the laminating parameters in the S320 are adopted for the rest of the raw materials of each layer to produce a finished circuit board; when the impedance test of the sample test circuit board fails, the etching parameters or the lamination parameters preset in the step S320 are modified and the step S320 is repeated.
According to the circuit board production method, when the circuit boards are produced in batch, the etching parameters and the laminating parameters which enable the impedance test to be qualified are obtained by using the preparation sample test circuit board, so that the phenomenon that the rejection rate of the circuit boards is high due to unqualified impedance test when the circuit boards are produced in batch through laminating can be avoided. Meanwhile, the impedance test is carried out on the test circuit board by adopting the circuit board impedance test method, so that the impedance test time of the test circuit board can be effectively shortened, and the time for obtaining the lamination parameters which can make the impedance test qualified is further shortened. This method is advantageous in shortening the production lead time.
Drawings
Fig. 1 is a schematic structural diagram of a circuit board according to an embodiment;
FIG. 2 is a schematic diagram of an impedance test of the circuit board of FIG. 1;
FIG. 3 is a schematic structural diagram of a circuit board according to yet another embodiment;
fig. 4 is a schematic diagram of an impedance test of the circuit board in fig. 3.
Description of reference numerals:
100. the testing device comprises a circuit board, 110, a testing circuit board, 111, first detection holes, 112, second detection holes, 113, a first shielding layer, 114, an impedance line, 115, a second shielding layer, 121, a first target, 122, a second target, 123, a third target, 124, a fourth target, 125, a fifth target, 126, a sixth target, 210, a first conductive column, 220, a second conductive column, 221, a first insulating layer, 222 and a second insulating layer.
Detailed Description
To facilitate an understanding of the invention, the invention will now be described more fully with reference to the accompanying drawings. Preferred embodiments of the present invention are shown in the drawings. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
It will be understood that when an element is referred to as being "secured to" another element, it can be directly on the other element or intervening elements may also be present. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" another element, there are no intervening elements present. The terms "vertical," "horizontal," "left," "right," and the like as used herein are for illustrative purposes only and do not represent the only embodiments.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.
Referring to fig. 1 and 2, in one embodiment, an impedance testing method is provided, which includes the following steps: s110, providing a test circuit board 110, wherein the test circuit board 110 is provided with a first detection hole 111, a second detection hole 112, a first shielding layer 113, an impedance line 114 and a second shielding layer 115 which are sequentially arranged in a spacing and overlapping mode; s120, filling the first conductive pillar 210 in the first detection hole 111, where the first conductive pillar 210 conductively connects the first shielding layer 113 and the second shielding layer 115; the second conductive pillar 220 is installed in the second detection hole 112, and the second conductive pillar 220 is electrically connected to the impedance line 114; s130, testing the impedance between the first conductive pillar 210 and the second conductive pillar 220.
In the impedance testing method, the first conductive pillar 210 installed in the first detection hole 111 is electrically connected to the first shielding layer 113 and the second shielding layer 115, the second conductive pillar 220 is electrically connected to the impedance line 114, and the impedance test of the test circuit board 110 can be completed by testing the impedance between the first conductive pillar 210 and the second conductive pillar 220. Compared with the method of using copper deposition and electroplating to connect the first shielding layer 113 and the second shielding layer 115 by connecting the inner wall of the first detection hole 111 and the test end of the impedance line 114 by electroplating the inner wall of the second detection hole 112, the first conductive pillar 210 can be used as the test end of connecting the first shielding layer 113 and the second shielding layer 115, and the second conductive pillar 220 can be used as the test end of the impedance line 114, so that the impedance test period of the test circuit board 110 can be shortened by saving the processing time of copper deposition and electroplating the first detection hole 111 and the second detection hole 112.
In an embodiment, the step S130 of testing the impedance between the first conductive pillar 210 and the second conductive pillar 220 specifically includes the following steps: the first conductive pillar 210 is electrically connected to the first test port of the impedance tester, and the second conductive pillar 220 is electrically connected to the second test port of the impedance tester, so as to read the test value of the impedance tester. In the impedance test, the first test port and the second test port are electrically connected with the first conductive pillar 210 and the second conductive pillar 220 to test the impedance of the test circuit board 110 in a simple manner; and the impedance tester can be electrically connected to the test circuit board 110 well by controlling the first test port to be electrically connected to the first conductive pillar 210 and the second test port to be electrically connected to the second conductive pillar 220.
In another embodiment, a method for processing a circuit board is provided, which includes the steps of: s210, providing a circuit board 100, wherein the circuit board 100 is provided with a first shielding layer 113, an impedance line 114 and a second shielding layer 115 which are sequentially arranged in a spacing and stacking mode; s220, arranging a first target 121 for positioning a first detection hole 111 and a second target 122 for positioning a second detection hole 112 on the circuit board 100; s230, opening a first detection hole 111 on the circuit board 100 according to the position of the first target 121 and opening a second detection hole 112 on the circuit board 100 according to the position of the second target 122 to obtain the test circuit board 110 applied to the impedance test method described in any of the above embodiments. The first target 121 is used to position the first detection hole 111 and the second target 122 is used to position the second detection hole 112, so that the opening accuracy of the first detection hole 111 and the second detection hole 112 can be improved, and reliable electrical connection among the first conductive pillar 210, the second conductive pillar 220, the first shielding layer 113, the impedance line 114, and the second shielding layer 115 in the impedance test can be ensured.
In an embodiment, the step S220 of disposing the first target 121 for positioning the first detection hole 111 and the second target 122 for positioning the second detection hole 112 on the circuit board 100 specifically includes the following steps: a first target 121 and a second target 122 are disposed in the same layer as the impedance line 114 in the wiring board 100, and the first target 121 and the second target 122 both correspond to the impedance line 114. Because the first target 121 and the second target 122 both correspond to the impedance line 114, the position relationship between the first detection hole 111 and the impedance line 114 and the position relationship between the second detection hole 112 and the impedance line 114 can be controlled, so that the reliability of the impedance test can be ensured.
In one embodiment, the step S220 of providing the first target 121 for positioning the first detection hole 111 and the target for positioning the second detection hole 112 on the circuit board 100 further includes the following steps: the third target 123 and the fourth target 124 are disposed in the same layer as the first shielding layer 113 in the circuit board 100, the fifth target 125 and the sixth target 126 are disposed in the same layer as the second shielding layer 115 in the circuit board 100, the third target 123 corresponds to the first target 121 and is used for positioning the first detection hole 111, the fourth target 124 corresponds to the second target 122 and is used for positioning the second detection hole 112, the fifth target 125 corresponds to the first target 121 and is used for positioning the first detection hole 111, and the sixth target 126 corresponds to the second target 122 and is used for positioning the second detection hole 112. The accuracy of the first detection hole 111 and the second detection hole 112 can be ensured by forming the first detection hole 111 by the first target 121, the third target 123 and the fifth target 125, and forming the second detection hole 112 by the second target 122, the fourth target 124 and the sixth target 126.
In one embodiment, the first, third and fifth targets 121, 123 and 125 are stacked, and the second, fourth and sixth targets 122, 124 and 126 are stacked. The lamination translation condition among the first shielding layer 113, the impedance line 114 and the second shielding layer 115 can be judged by observing the corresponding lamination condition of the first target 121, the third target 123 and the fifth target 125, and the corresponding lamination condition of the second target 122, the fourth target 124 and the sixth target 126, so as to control the opening positions of the first detection hole 111 and the second detection hole 112, thereby ensuring the accuracy of the impedance test.
As shown in fig. 1 and 2, when the third target 123 and the fourth target 124 which are on the same layer as the first shielding layer 113, and the fifth target 125 and the sixth target 126 which are on the same layer as the second shielding layer 115 are disposed in the circuit board 100, the first detection hole 111 is formed according to the first target 121, the third target 123, and the fifth target 125, and the second detection hole 112 is formed at the end of the second target 122, the fourth target 124, and the sixth target 126. When the first and second shielding layers 113 and 115 are copper layers disposed on the core plate, the processing of the third, fourth, fifth and sixth targets 123, 124, 125 and 126 may be completed in the inner layer pattern etching of the core plate. As shown in fig. 3 and 4, when the first shielding layer 113 and the second shielding layer 115 are laminated by using copper foils and no targets are etched on the copper foils, in order to reduce the number of processing steps of the third target 123, the fourth target 124, the fifth target 125, and the sixth target 126, the circuit board 100 may be provided with the first detection hole 111 and the second detection hole 112 corresponding to only the first target 121 and the second target 122.
In an embodiment, the step S230 of opening the first detection hole 111 on the circuit board 100 according to the position of the first target 121, and opening the second detection hole 112 on the circuit board 100 according to the position of the second target 122 specifically includes the following steps: the first detection hole 111 penetrating through the first target 121, the third target 123 and the fifth target 125 is formed in the circuit board 100 by using an X-ray; the second detection hole 112 passing through the second target 122, the fourth target 124 and the sixth target 126 is formed on the circuit board 100 by using an X-ray. When the first detection hole 111 and the second detection hole 112 are punched by using the X-ray, the position relationship among the first shielding layer 113, the impedance line 114, and the second shielding layer 115 can be observed by using the X-ray, and the accuracy of opening the first detection hole 111 and the second detection hole 112 can be further improved. Of course, in other embodiments, the first detection hole 111 and the second detection hole 112 may be drilled.
In another embodiment, a testing assembly applied to the impedance testing method in any of the above embodiments is provided, which includes a first conductive pillar 210 and a second conductive pillar 220, wherein the first conductive pillar 210 is configured to be mounted in the first detecting hole 111 and electrically connected to the first shielding layer 113 and the second shielding layer 115, and the second conductive pillar 220 is configured to be mounted in the second detecting hole 112 and electrically connected to the impedance line 114.
In the testing assembly, during the impedance test, the first conductive pillar 210 installed in the first detecting hole 111 is electrically connected to the first shielding layer 113 and the second shielding layer 115, the second conductive pillar 220 is electrically connected to the impedance line 114, the impedance test of the test circuit board 110 can be completed by testing the impedance between the first conductive pillar 210 and the second conductive pillar 220, compared with the way of using the copper deposition and plating of the inner wall of the first detecting hole 111 to connect the first shielding layer 113 and the second shielding layer 115 in a conductive manner, and the copper deposition and plating of the inner wall of the second detecting hole 112 to lead out the testing terminal of the impedance line 114, the first conductive pillar 210 can be used as the testing terminal for connecting the first shielding layer 113 and the second shielding layer 115 in a conductive manner, the second conductive pillar 220 can be used as the testing terminal of the impedance line 114, therefore, the processing time of the first detection hole 111 and the second detection hole 112 of the copper deposition electroplating can be saved, and the impedance test period of the test circuit board 110 is further shortened.
In one embodiment, a first insulating layer 221 corresponding to the first shielding layer 113 and a second insulating layer 222 corresponding to the second shielding layer 115 are disposed on the second conductive pillar 220, the second conductive pillar 220 is insulated from the first shielding layer 113 by the first insulating layer 221, and the second conductive pillar 220 is insulated from the second shielding layer 115 by the second insulating layer 222. In the impedance test, the first conductive pillar 210 and the impedance line 114 can be insulated by opening a first test hole deviating from the impedance line 114, and the second conductive pillar 220 can be insulated from the first shielding layer 113 and the second shielding layer 115 by the first insulating layer 221 and the second insulating layer 222.
In another embodiment, a method for manufacturing a circuit board is provided, which includes the steps of: s310, producing all layers of materials forming the finished circuit board in batches according to the finished circuit board; s320, preparing a test circuit board according to the preset etching parameters and the preset laminating parameters; s330, performing impedance test on the test circuit board by using the impedance test method of any one of claims 1-2; when the impedance test of the sample test circuit board is qualified, the etching parameters and the laminating parameters in the S320 are adopted for the rest of the raw materials of each layer to produce a finished circuit board; when the impedance test of the sample test circuit board fails, the etching parameters or the lamination parameters preset in the step S320 are modified and the step S320 is repeated.
According to the circuit board production method, when the circuit boards are produced in batch, the etching parameters and the laminating parameters which enable the impedance test to be qualified are obtained by using the preparation sample test circuit board, so that the phenomenon that the rejection rate of the circuit boards is high due to unqualified impedance test when the circuit boards are produced in batch through laminating can be avoided. Meanwhile, the impedance test is carried out on the test circuit board by adopting the circuit board impedance test method, so that the impedance test time of the test circuit board can be effectively shortened, and the time for obtaining the lamination parameters which can make the impedance test qualified is further shortened. This method is advantageous in shortening the production lead time.
The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.
Claims (10)
1. An impedance testing method is characterized by comprising the following steps:
s110, providing a test circuit board, wherein the test circuit board is provided with a first detection hole, a second detection hole, a first shielding layer, an impedance line and a second shielding layer which are sequentially arranged in a spacing and stacking mode;
s120, a first conductive column is arranged in the first detection hole and is in conductive connection with the first shielding layer and the second shielding layer; a second conductive column is arranged in the second detection hole and electrically connected with the impedance line; the second conductive column is provided with a first insulating layer corresponding to the first shielding layer and a second insulating layer corresponding to the second shielding layer, the second conductive column is insulated from the first shielding layer through the first insulating layer, and the second conductive column is insulated from the second shielding layer through the second insulating layer;
and S130, testing the impedance between the first conductive pillar and the second conductive pillar.
2. The impedance testing method according to claim 1, wherein the S130 testing the impedance between the first conductive pillar and the second conductive pillar specifically includes the following steps:
and the first test port is electrically connected with the first conductive column and the impedance tester, the second test port is electrically connected with the second conductive column and the impedance tester, and the test value of the impedance tester is read.
3. A method of processing a circuit board including the impedance testing method of claim 1, comprising the steps of:
s210, providing a circuit board, wherein the circuit board is provided with a first shielding layer, an impedance line and a second shielding layer which are sequentially arranged in a spacing and stacking mode;
s220, arranging a first target for positioning a first detection hole and a second target for positioning a second detection hole on the circuit board;
and S230, forming a first detection hole on the circuit board according to the position of the first target and forming a second detection hole on the circuit board according to the position of the second target to obtain a test circuit board.
4. The processing method of the circuit board according to claim 3, wherein the step S220 of arranging a first target for positioning a first detection hole and a second target for positioning a second detection hole on the circuit board specifically includes the following steps:
and arranging a first target and a second target in the same layer with the impedance line in the circuit board.
5. The method for processing a circuit board according to claim 4, wherein the step S220 of providing the first target for positioning the first detection hole and the target for positioning the second detection hole on the circuit board further comprises the steps of:
the third target and the fourth target which are on the same layer as the first shielding layer are arranged in the circuit board, the fifth target and the sixth target which are on the same layer as the second shielding layer are arranged in the circuit board, the third target corresponds to the first target and is used for positioning the first detection hole, the fourth target corresponds to the second target and is used for positioning the second detection hole, the fifth target corresponds to the first target and is used for positioning the first detection hole, and the sixth target corresponds to the second target and is used for positioning the second detection hole.
6. The method for processing a circuit board according to claim 5, wherein the first target, the third target and the fifth target are stacked correspondingly, and the second target, the fourth target and the fifth target are stacked correspondingly.
7. The method for processing the circuit board according to claim 6, wherein the step S230 of opening a first inspection hole on the circuit board according to the position of the first target and opening a second inspection hole on the circuit board according to the position of the second target specifically includes the following steps:
the first detection hole which penetrates through the first target, the third target and the fifth target is formed in the circuit board by adopting an X-ray; and arranging a second detection hole which penetrates through the second target, the fourth target and the sixth target on the circuit board by adopting an X-ray.
8. A testing assembly applied to the impedance testing method according to any one of claims 1 to 2, comprising a first conductive pillar and a second conductive pillar, wherein the first conductive pillar is configured to be installed in the first detecting hole and electrically connect the first shielding layer and the second shielding layer, and the second conductive pillar is configured to be installed in the second detecting hole and electrically connect with the impedance line.
9. The test assembly of claim 8, wherein the first conductive post is insulated from the impedance line by opening a first test hole offset from the impedance line.
10. A method of producing a wiring board including the impedance testing method of claim 1, characterized by comprising the steps of:
s310, producing all layers of materials forming the finished circuit board in batches according to the finished circuit board;
s320, preparing a test circuit board according to the preset etching parameters and the preset laminating parameters;
s330, carrying out impedance test on the test circuit board;
when the impedance test of the sample test circuit board is qualified, the etching parameters and the laminating parameters in the S320 are adopted for the rest of the raw materials of each layer to produce a finished circuit board;
when the impedance test of the sample test circuit board fails, the etching parameters or the lamination parameters preset in the step S320 are modified and the step S320 is repeated.
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| CN112188725B (en) * | 2020-09-25 | 2021-10-08 | 深圳市景旺电子股份有限公司 | Impedance test module of printed circuit board and manufacturing method of printed circuit board |
| US20240402236A1 (en) * | 2023-06-05 | 2024-12-05 | Delta Electronics (Shanghai) Co., Ltd. | Shielding-type insulation detection structure |
| CN119902115A (en) * | 2025-03-28 | 2025-04-29 | 苏州元脑智能科技有限公司 | Power supply detection component, monitoring circuit, method, electronic device, product and medium |
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| CN101043790A (en) * | 2006-03-23 | 2007-09-26 | 日本电气株式会社 | Multilayer printed wiring board and method of measuring characteristic impedance |
| CN105228378A (en) * | 2015-08-31 | 2016-01-06 | 北大方正集团有限公司 | A kind of circuit board and impedance method for measurement thereof |
| CN205450113U (en) * | 2015-12-28 | 2016-08-10 | 广州兴森快捷电路科技有限公司 | PCB impedance probe |
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|---|---|---|---|---|
| CN101043790A (en) * | 2006-03-23 | 2007-09-26 | 日本电气株式会社 | Multilayer printed wiring board and method of measuring characteristic impedance |
| CN105228378A (en) * | 2015-08-31 | 2016-01-06 | 北大方正集团有限公司 | A kind of circuit board and impedance method for measurement thereof |
| CN205450113U (en) * | 2015-12-28 | 2016-08-10 | 广州兴森快捷电路科技有限公司 | PCB impedance probe |
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