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CN109545856B - Transistor based on cation transverse motion and preparation and control method thereof - Google Patents

Transistor based on cation transverse motion and preparation and control method thereof Download PDF

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CN109545856B
CN109545856B CN201811402789.8A CN201811402789A CN109545856B CN 109545856 B CN109545856 B CN 109545856B CN 201811402789 A CN201811402789 A CN 201811402789A CN 109545856 B CN109545856 B CN 109545856B
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electrode layer
gate electrode
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metal oxide
bottom gate
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CN109545856A (en
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唐秀凤
罗坚义
廖慧珍
黄景诚
陈国新
莫钊鹏
马定邦
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Wuyi University Fujian
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    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/60Insulated-gate field-effect transistors [IGFET]
    • H10D30/611Insulated-gate field-effect transistors [IGFET] having multiple independently-addressable gate electrodes influencing the same channel
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
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    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10KORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K10/00Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having potential barriers
    • H10K10/40Organic transistors
    • H10K10/46Field-effect transistors, e.g. organic thin-film transistors [OTFT]
    • H10K10/462Insulated gate field-effect transistors [IGFETs]
    • H10K10/481Insulated gate field-effect transistors [IGFETs] characterised by the gate conductors
    • H10K10/482Insulated gate field-effect transistors [IGFETs] characterised by the gate conductors the IGFET comprising multiple separately-addressable gate electrodes
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
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    • H10K71/12Deposition of organic active material using liquid deposition, e.g. spin coating

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Abstract

本发明涉及一种基于阳离子横向运动的晶体管及其制备和控制方法。所述晶体管包括绝缘基片、底栅电极层、金属氧化物层、源电极层、漏电极层、顶栅电极层和含有阳离子的电解质层;所述底栅电极层设于绝缘基片表面;所述金属氧化物层覆盖于底栅电极层表面,露出底栅电极层表面的两侧区域不被覆盖,用于连接外电路以在底栅电极层中产生横向电流;所述源、漏电极层分别设于金属氧化物层表面一侧相对的两端,且互不接触,两者之间的区域形成导电沟道;所述顶栅电极层设于金属氧化物层表面的另一侧,且不与源、漏电极层接触;所述电解质层设于金属氧化物层表面,并与顶栅电极层接触,且不与源、漏电极层接触。

Figure 201811402789

The invention relates to a transistor based on lateral motion of cations and a method for its preparation and control. The transistor comprises an insulating substrate, a bottom gate electrode layer, a metal oxide layer, a source electrode layer, a drain electrode layer, a top gate electrode layer and an electrolyte layer containing cations; the bottom gate electrode layer is arranged on the surface of the insulating substrate; The metal oxide layer covers the surface of the bottom gate electrode layer, and the areas on both sides of the surface of the bottom gate electrode layer are not covered, and are used to connect external circuits to generate lateral current in the bottom gate electrode layer; the source and drain electrodes The layers are respectively arranged at opposite ends of one side of the surface of the metal oxide layer without contacting each other, and the area between the two forms a conductive channel; the top gate electrode layer is arranged on the other side of the surface of the metal oxide layer, and not in contact with the source and drain electrode layers; the electrolyte layer is arranged on the surface of the metal oxide layer and in contact with the top gate electrode layer, and not in contact with the source and drain electrode layers.

Figure 201811402789

Description

Transistor based on cation transverse motion and preparation and control method thereof
Technical Field
The invention relates to the field of artificial synapse transistors, in particular to a transistor based on cation lateral motion and a preparation method and a control method thereof.
Background
The traditional computer is based on the micro-processing chip technology of a von Neumann computer architecture, and is characterized in that information storage and information processing are separated from calculation, and as information expands, people enter an artificial intelligence era. The traditional computer can not process complex information in real time with small power consumption like the brain, and has powerful learning, memorizing and parallel computing functions. Therefore, the study of human brain or brain-like computing has become a focus of research in the scientific community in recent years. Most of current researches are only focused on simulating and simulating the large-scale neural network of the human brain, the adopted simulated neural network chip is still based on the traditional CMOS process technology, even the integration level of the chip is further improved, the chip still stays in the original computer framework, data disappear after power failure, the bionic memory function cannot be realized, and the gap with the human brain is large.
Various emerging ideas and components are proposed to emulate neuronal and inter-neuronal synaptosomal nodes, including an ionic liquid-based artificial synapse transistor. In the ionic liquid synaptic transistor, short-term memory and long-term memory of human brain can be simulated. These functions are the basis for operation, learning and memory of the neuron system, but the simulation of the pulse signals transmitted and received between neurons to realize the operation and analysis of the human brain requires not only the artificial synapse transistor to simulate the memory function of the human brain, but also the switching, excitation and inhibition, parallel computation and the like of the nerve-like function, and at present, no such ionic liquid artificial synapse transistor can integrate the above functions.
Disclosure of Invention
In view of the above, an object of the present invention is to provide a transistor based on lateral movement of cations, which can simulate not only the short-term and long-term memory functions of the human brain but also the switching and suppression functions of the human brain.
The purpose of the invention is realized by the following technical scheme: a transistor based on cation lateral movement comprises an insulating substrate, a bottom gate electrode layer, a metal oxide layer, a source electrode layer, a drain electrode layer, a top gate electrode layer and an electrolyte layer; the bottom gate electrode layer is arranged on the surface of the insulating substrate; the metal oxide layer covers the surface of the bottom gate electrode layer, and two side areas exposed out of the surface of the bottom gate electrode layer are not covered and are used for being connected with an external circuit to generate transverse current in the bottom gate electrode layer; the source electrode layer and the drain electrode layer are respectively arranged at two opposite ends of one side of the surface of the metal oxide layer and are not in contact with each other, a conductive channel is formed in an area between the source electrode layer and the drain electrode layer, and the direction of the conductive channel is not parallel to the direction of the transverse current; the top gate electrode layer is arranged on the other side of the surface of the metal oxide layer and is not in contact with the source electrode layer and the drain electrode layer; the electrolyte layer is an electrolyte layer containing cations, is arranged on the surface of the metal oxide layer, is in contact with the top gate electrode layer, and is not in contact with the source electrode layer and the drain electrode layer.
Compared with the prior art, the invention can apply voltage between the top gate electrode layer and the bottom gate electrode layer, thereby injecting positive ions in the electrolyte layer into the metal oxide layer, and the resistance of the conductive channel is reduced along with the increase of the applied voltage, and the process can simulate the short-term and long-term memory functions of the human brain; meanwhile, transverse current can be introduced into the bottom gate electrode layer, a magnetic field is formed between the interface of the electrolyte layer and the metal oxide layer by the transverse current, cations in the conducting channel can migrate to one side, far away from the conducting channel, of the metal oxide layer along the current direction under the action of the magnetic field, so that the resistance of the conducting channel is increased, and the process can simulate the switching and inhibiting functions in human brain-like calculation.
Further, the direction of the conductive channel is perpendicular to the direction of the lateral current flow.
Further, in the direction along the conductive channel, the length of the metal oxide layer is greater than the width of the bottom gate electrode layer, and the length of the conductive channel is less than the width of the bottom gate electrode layer.
Go toStep (b), the metal oxide layer is WO3Film or MoO3The film has a thickness of 100 to 800 nm.
Further, the cation is a lithium ion or a hydrogen ion.
The invention also provides a preparation method of the transistor based on the cation transverse motion, which comprises the following steps:
s1: depositing a bottom gate electrode layer on the surface of the insulating substrate;
s2: depositing a metal oxide layer on the surface of the bottom gate electrode layer, covering the metal oxide layer on the surface of the bottom gate electrode layer, wherein two side areas exposed out of the surface of the bottom gate electrode layer are not covered and are used for being connected with an external circuit to generate transverse current in the bottom gate electrode layer;
s3: depositing a source electrode layer and a drain electrode layer at two opposite ends of one side of the surface of the metal oxide layer respectively to ensure that the source electrode layer and the drain electrode layer are not contacted with each other, forming a conductive channel in an area between the source electrode layer and the drain electrode layer, wherein the direction of the conductive channel is not parallel to the direction of the transverse current;
s4: depositing a top gate electrode layer on the other side of the surface of the metal oxide layer, so that the top gate electrode layer is not in contact with the source electrode layer and the drain electrode layer;
s5: and spin-coating an electrolyte layer containing cations on the surface of the metal oxide layer, so that the electrolyte layer is in contact with the top gate electrode layer and is not in contact with the source electrode layer and the drain electrode layer.
The invention also provides a control method of the transistor based on the cation transverse motion, which comprises the following steps:
w1: loading voltage between the top gate electrode layer and the bottom gate electrode layer to inject cations in the electrolyte layer into the metal oxide layer, so that the resistance value of a conductive channel between the source electrode layer and the drain electrode layer is reduced, and the transistor is in an open state; removing the voltage loaded between the top gate electrode layer and the bottom gate electrode layer, and temporarily and stably retaining the injected cations in the metal oxide layer;
w2: introducing transverse current vertical to the conducting channel into the bottom gate electrode layer, so that cations staying in the conducting channel migrate along the current direction and are gathered to one side, away from the conducting channel, of the metal oxide layer, the resistance value of the conducting channel is increased, and the transistor is in a closed state;
w3: the lateral current in the bottom gate electrode layer is removed, causing the cations to re-enter the conduction channel in a self-diffusing manner, causing the resistance of the conduction channel to drop and the transistor to be in an on state.
Further, the amount of cations injected from the electrolyte layer to the metal oxide layer is controlled by controlling the time for which the voltage is applied; the resistance value of the conductive channel is inversely proportional to the number of cations residing in the conductive channel.
Further, the cations injected into the metal oxide layer spontaneously escape into the electrolyte layer after staying for a sufficient time.
Further, the magnitude of the transverse current is 0.05-0.2A.
For a better understanding and practice, the invention is described in detail below with reference to the accompanying drawings.
Drawings
Fig. 1 is a schematic structural view of a transistor based on lateral motion of cations according to example 1.
Fig. 2 is a transistor output characteristic curve under the control of the top gate electrode layer applied voltage of example 1.
Fig. 3 is a graph showing the output characteristics of the transistor under the control of the bottom gate electrode layer lateral current in example 1.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention. In addition, the technical features involved in the embodiments of the present invention described below may be combined with each other as long as they do not conflict with each other.
Example 1
Please refer to fig. 1, which is a schematic structural diagram of a transistor based on lateral movement of cations according to the present embodiment. The transistor based on the lateral movement of cations comprises an insulating substrate 1, a bottom gate electrode layer 3, a metal oxide layer 2, a source electrode layer 5, a drain electrode layer 6, a top gate electrode layer 4 and an electrolyte layer 7.
The bottom gate electrode layer 3 is disposed on the surface of the insulating substrate 1, in this embodiment, the bottom gate electrode layer 3 covers the middle portion of the insulating substrate 1, the area of the bottom gate electrode layer is smaller than that of the insulating substrate 1, and an area not covered by the bottom gate electrode layer 3 is exposed in the longitudinal direction of the insulating substrate 1. The insulating substrate 1 may be a glass substrate, and the bottom gate electrode layer 3 may be a metal conductive layer.
The metal oxide layer 2 covers the surface of the bottom gate electrode layer 3, and two side areas exposed out of the surface of the bottom gate electrode layer 3 are not covered and are used for being connected with an external circuit to generate transverse current in the bottom gate electrode layer 3. In this embodiment, the length of the metal oxide layer 2 in the lateral direction is smaller than the length of the bottom gate electrode layer 3 in the lateral direction, so that the left and right sides of the bottom gate electrode layer 3 are exposed and not covered. The length of the metal oxide layer 2 in the longitudinal direction is greater than the length of the bottom gate electrode layer 3 in the longitudinal direction, and a portion thereof exceeding the length of the bottom gate electrode layer 3 is in contact with the insulating substrate 1. The metal oxide layer 2 may be a metal oxide thin film, preferably WO3Film or MoO3The film preferably has a thickness of 100 to 800 nm.
The source electrode layer 5 and the drain electrode layer 6 are respectively arranged at two opposite ends of one side of the surface of the metal oxide layer 2, and are not in contact with each other, and a conductive channel is formed in the region between the two. In this embodiment, the source electrode layer 5 and the drain electrode layer 6 are respectively disposed at two longitudinal ends of the left side of the surface of the metal oxide layer 2, and the edges thereof extend to the outside of the metal oxide layer 2, but do not contact with the insulating substrate 1. The conductive channel between the source electrode layer 5 and the drain electrode layer 6 is along the longitudinal direction, and the length of the conductive channel is smaller than the longitudinal width of the bottom gate electrode layer 3, so that the conductive channel is completely positioned above the bottom gate electrode layer 3 to receive the transverse current drive in the bottom gate electrode layer 3.
The top gate electrode layer 4 is disposed on the other side of the surface of the metal oxide layer 2, and is not in contact with the source electrode layer 5 and the drain electrode layer 6. In this embodiment, the top gate electrode layer 4 is disposed above the right side of the surface of the metal oxide layer 2.
The electrolyte layer 7 is a cation-containing electrolyte layer, is provided on the surface of the metal oxide layer 2, is in contact with the top gate electrode layer 4, and is not in contact with the source electrode layer 5 and the drain electrode layer 6. In this embodiment, the electrolyte may be a liquid electrolyte, a gel electrolyte or a solid electrolyte, and the cation is preferably lithium ion or hydrogen ion.
The preparation method of the transistor based on the lateral movement of the cations comprises the following steps:
(1) and depositing a metal conductive layer on the non-conductive glass substrate to serve as a bottom gate electrode layer.
(2) Longitudinally depositing a metal oxide layer on the bottom gate electrode layer by masking (WO)3And the thin film spans the bottom gate electrode layer, so that the metal oxide layer covers the middle area of the surface of the bottom gate electrode layer, and the two side areas exposed out of the surface of the bottom gate electrode layer are not covered and are used for being connected with an external circuit to generate transverse current in the bottom gate electrode layer.
(3) And respectively depositing a source electrode layer and a drain electrode layer at two opposite ends of the left side of the surface of the metal oxide layer, so that the source electrode layer and the drain electrode layer are not contacted with each other, forming a longitudinal conductive channel in the region between the source electrode layer and the drain electrode layer, wherein the direction of the conductive channel is vertical to the direction of the transverse current.
(4) And depositing a top gate electrode layer on the right side of the surface of the metal oxide layer through magnetron sputtering, so that the top gate electrode layer is not in contact with the source electrode layer and the drain electrode layer.
(5) Spin coating a colloid electrolyte layer (PC-LiClO) containing cations on the surface of the metal oxide layer4) And contacting the electrolyte layer with the top gate electrode layer and not with the source electrode layer and the drain electrode layer.
The control method of the transistor based on the lateral movement of the positive ions comprises the following steps:
(1) loading voltage between the top gate electrode layer and the bottom gate electrode layer to inject cations in the electrolyte layer into the metal oxide layer, so that the resistance value of a conductive channel between the source electrode layer and the drain electrode layer is reduced, and the transistor is in an open state; and removing the voltage loaded between the top gate electrode layer and the bottom gate electrode layer, and temporarily and stably retaining the injected cations in the metal oxide layer. The amount of cations injected from the electrolyte layer to the metal oxide layer can be controlled by controlling the time for which the voltage is applied, and the resistance value of the conductive channel is inversely proportional to the amount of cations residing in the conductive channel.
(2) And introducing transverse current vertical to the conducting channel into the bottom gate electrode layer, so that cations staying in the conducting channel migrate along the current direction and are gathered to one side of the metal oxide layer far away from the conducting channel, the resistance value of the conducting channel is increased, and the transistor is in an off state. The magnitude of the transverse current is preferably 0.05-0.2A.
(3) The lateral current in the bottom gate electrode layer is removed, causing the cations to re-enter the conduction channel in a self-diffusing manner, causing the resistance of the conduction channel to drop and the transistor to be in an on state. The cations injected into the metal oxide layer spontaneously escape into the electrolyte layer after staying for a sufficient period of time.
Please refer to fig. 2, which is a characteristic curve of the output of the transistor under the control of the top gate electrode loading voltage in the present embodiment. Under the condition that the bottom gate electrode layer is grounded, voltages (0-3V) with different magnitudes are applied to the top gate electrode layer for 10s, and after the voltage of the top gate electrode layer is removed, an I-V characteristic curve between the source electrode layer and the drain electrode layer in the device is tested, as shown in FIG. 2. It can be seen that as the applied voltage increases, the resistance of the conduction channel between the source and drain electrode layers decreases, because the number of cations injected into the conduction channel from the electrolyte layer increases, resulting in a decrease in the resistance of the conduction channel. The process can simulate the memory function of the human brain under different external stimuli, and when the stimuli applied in the learning process are larger, the relevance and the memory between two neurons are stronger.
Please refer to fig. 3, which is a characteristic curve of the transistor output under the control of the bottom gate electrode layer lateral current in the present embodiment. Firstly, applying a voltage of 3V on the top gate electrode layer for 60s, then removing the voltage of the top gate electrode layer, introducing transverse currents (0-0.2A) with different sizes into the bottom gate electrode layer, forming a magnetic field between the electrolyte layer and the metal oxide layer by the transverse currents, and enabling ions in the conductive channel to migrate along the current direction and gather to the other side of the metal oxide layer far away from the conductive channel under the action of the magnetic field, so that the resistance of the conductive channel is rapidly increased, and finally the source electrode layer and the drain electrode layer are in an off state. This process can simulate the on-off switching and suppression functions in human-like brain computing.
Compared with the prior art, the transistor based on the cation transverse motion can simulate the short-term and long-term memory function of the human brain, can also simulate the switch switching and inhibiting functions of the human brain, and has better application prospect.
The above-mentioned embodiments only express several embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention.

Claims (10)

1.一种基于阳离子横向运动的晶体管,其特征在于,包括绝缘基片、底栅电极层、金属氧化物层、源电极层、漏电极层、顶栅电极层和电解质层;所述底栅电极层设于所述绝缘基片表面;所述金属氧化物层覆盖于所述底栅电极层表面,露出所述底栅电极层表面的两侧区域不被覆盖,用于连接外电路以在所述底栅电极层中产生横向电流;所述源电极层和漏电极层分别设于所述金属氧化物层表面一侧相对的两端,且互不接触,两者之间的区域形成导电沟道,该导电沟道的方向与所述横向电流的方向互不平行;所述顶栅电极层设于所述金属氧化物层表面的另一侧,且不与所述源电极层和漏电极层接触;所述电解质层为含有阳离子的电解质层,其设于所述金属氧化物层表面,并与所述顶栅电极层接触,且不与所述源电极层和漏电极层接触。1. a transistor based on lateral motion of cations, is characterized in that, comprises insulating substrate, bottom gate electrode layer, metal oxide layer, source electrode layer, drain electrode layer, top gate electrode layer and electrolyte layer; Described bottom gate electrode The electrode layer is arranged on the surface of the insulating substrate; the metal oxide layer covers the surface of the bottom gate electrode layer, and the areas on both sides of the surface of the bottom gate electrode layer are not covered, and are used for connecting external circuits to A lateral current is generated in the bottom gate electrode layer; the source electrode layer and the drain electrode layer are respectively arranged at opposite ends of one side of the surface of the metal oxide layer, and do not contact each other, and the area between the two forms a conductive layer The direction of the conductive channel and the direction of the lateral current are not parallel to each other; the top gate electrode layer is provided on the other side of the surface of the metal oxide layer, and is not connected to the source electrode layer and the leakage current. The electrode layer is in contact; the electrolyte layer is an electrolyte layer containing cations, which is provided on the surface of the metal oxide layer, and is in contact with the top gate electrode layer, but not in contact with the source electrode layer and the drain electrode layer. 2.根据权利要求1所述的基于阳离子横向运动的晶体管,其特征在于,所述导电沟道的方向与所述横向电流的方向垂直。2 . The transistor based on lateral motion of cations according to claim 1 , wherein the direction of the conductive channel is perpendicular to the direction of the lateral current. 3 . 3.根据权利要求2所述的基于阳离子横向运动的晶体管,其特征在于,在沿所述导电沟道的方向上,所述金属氧化物层的长度大于所述底栅电极层的宽度,所述导电沟道的长度小于所述底栅电极层的宽度。3 . The transistor based on lateral motion of cations according to claim 2 , wherein in the direction along the conductive channel, the length of the metal oxide layer is greater than the width of the bottom gate electrode layer, so the The length of the conductive channel is smaller than the width of the bottom gate electrode layer. 4.根据权利要求1所述的基于阳离子横向运动的晶体管,其特征在于,所述金属氧化物层为WO3薄膜或MoO3薄膜,其厚度为100~800nm。4 . The transistor based on lateral motion of cations according to claim 1 , wherein the metal oxide layer is a WO 3 thin film or a MoO 3 thin film, and its thickness is 100-800 nm. 5 . 5.根据权利要求1所述的基于阳离子横向运动的晶体管,其特征在于,所述阳离子为锂离子或氢离子。5 . The transistor based on lateral motion of cations according to claim 1 , wherein the cations are lithium ions or hydrogen ions. 6 . 6.一种基于阳离子横向运动的晶体管的制备方法,其特征在于,包括以下步骤:6. A method for preparing a transistor based on lateral motion of cations, comprising the following steps: S1:在绝缘基片表面沉积底栅电极层;S1: deposit a bottom gate electrode layer on the surface of the insulating substrate; S2:在所述底栅电极层表面沉积金属氧化物层,使所述金属氧化物层覆盖于所述底栅电极层表面,露出所述底栅电极层表面的两侧区域不被覆盖,用于连接外电路以在所述底栅电极层中产生横向电流;S2: depositing a metal oxide layer on the surface of the bottom gate electrode layer, so that the metal oxide layer covers the surface of the bottom gate electrode layer, and the regions on both sides of the surface of the bottom gate electrode layer that are exposed are not covered, using for connecting external circuits to generate lateral currents in the bottom gate electrode layer; S3:在所述金属氧化物层表面一侧相对的两端分别沉积源电极层和漏电极层,使所述源电极层和漏电极层互不接触,两者之间的区域形成导电沟道,该导电沟道的方向与所述横向电流的方向互不平行;S3: deposit a source electrode layer and a drain electrode layer on the opposite ends of the surface of the metal oxide layer, so that the source electrode layer and the drain electrode layer are not in contact with each other, and the area between the two forms a conductive channel , the direction of the conductive channel and the direction of the lateral current are not parallel to each other; S4:在所述金属氧化物层表面的另一侧沉积顶栅电极层,使所述顶栅电极层不与所述源电极层和漏电极层接触;S4: depositing a top gate electrode layer on the other side of the surface of the metal oxide layer, so that the top gate electrode layer is not in contact with the source electrode layer and the drain electrode layer; S5:在所述金属氧化物层表面旋涂含有阳离子的电解质层,使所述电解质层与所述顶栅电极层接触,且不与所述源电极层和漏电极层接触。S5: Spin coating an electrolyte layer containing cations on the surface of the metal oxide layer, so that the electrolyte layer is in contact with the top gate electrode layer and not in contact with the source electrode layer and the drain electrode layer. 7.权利要求1~5任一项所述的基于阳离子横向运动的晶体管的控制方法,其特征在于,包括以下步骤:7. The control method for a transistor based on lateral motion of cations according to any one of claims 1 to 5, characterized in that it comprises the following steps: W1:在顶栅电极层和底栅电极层之间加载电压,使电解质层中的阳离子注入至金属氧化物层,引起源电极层和漏电极层之间的导电沟道的电阻值下降,晶体管处于打开状态;撤去顶栅电极层和底栅电极层之间加载的电压,注入的阳离子暂时稳定停留在金属氧化物层内;W1: A voltage is applied between the top gate electrode layer and the bottom gate electrode layer, so that cations in the electrolyte layer are injected into the metal oxide layer, causing the resistance value of the conductive channel between the source electrode layer and the drain electrode layer to decrease, the transistor In the open state; the voltage loaded between the top gate electrode layer and the bottom gate electrode layer is removed, and the injected cations temporarily stay in the metal oxide layer stably; W2:在底栅电极层中通入垂直于导电沟道的横向电流,使停留在导电沟道内的阳离子沿着电流方向迁移并聚集到金属氧化物层远离导电沟道的一侧,导致导电沟道的电阻值上升,晶体管处于关闭状态;W2: A lateral current perpendicular to the conductive channel is passed into the bottom gate electrode layer, so that the cations staying in the conductive channel migrate along the current direction and gather to the side of the metal oxide layer away from the conductive channel, resulting in the conductive channel The resistance value of the channel rises, and the transistor is turned off; W3:撤去底栅电极层中的横向电流,使阳离子以自扩散的方式重新回到导电沟道内,引起导电沟道的电阻值下降,晶体管处于打开状态。W3: Remove the lateral current in the bottom gate electrode layer, so that the cations return to the conductive channel by self-diffusion, causing the resistance value of the conductive channel to drop, and the transistor is in an open state. 8.根据权利要求7所述的控制方法,其特征在于,通过控制加载电压的时间控制从电解质层注入至金属氧化物层的阳离子数量;所述导电沟道的电阻值与停留在导电沟道内的阳离子数量成反比。8 . The control method according to claim 7 , wherein the number of cations injected from the electrolyte layer to the metal oxide layer is controlled by controlling the time of the applied voltage; the resistance value of the conductive channel is related to the resistance value of the conductive channel staying in the conductive channel. 9 . The number of cations is inversely proportional. 9.根据权利要求7所述的控制方法,其特征在于,注入至金属氧化物层的阳离子停留足够长时间后自发脱出到电解质层中。9 . The control method according to claim 7 , wherein the cations injected into the metal oxide layer stay in the metal oxide layer for a long enough time and then spontaneously come out into the electrolyte layer. 10 . 10.根据权利要求7所述的控制方法,其特征在于,所述横向电流的大小为0.05~0.2A。10 . The control method according to claim 7 , wherein the magnitude of the lateral current is 0.05-0.2A. 11 .
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US11916121B2 (en) * 2020-06-29 2024-02-27 Taiwan Semiconductor Manufacturing Company Limited Tri-gate orthogonal channel transistor and methods of forming the same

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104835835A (en) * 2015-03-18 2015-08-12 南京华印半导体有限公司 Solid electrolyte film transistor and manufacturing method thereof
CN108336145A (en) * 2018-01-29 2018-07-27 中国科学院微电子研究所 Artificial neuron structure, preparation method thereof and signal and time extraction method
CN108807546A (en) * 2017-05-02 2018-11-13 中国科学院宁波材料技术与工程研究所 Oxide thin film transistor and its manufacturing method

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102870040B (en) * 2010-03-25 2015-07-08 康涅狄格大学 Formation of conjugated polymers for solid-state devices
US9147615B2 (en) * 2014-02-14 2015-09-29 International Business Machines Corporation Ambipolar synaptic devices
US9812568B2 (en) * 2016-02-04 2017-11-07 Board Of Regents, The University Of Texas System Ionic barristor

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104835835A (en) * 2015-03-18 2015-08-12 南京华印半导体有限公司 Solid electrolyte film transistor and manufacturing method thereof
CN108807546A (en) * 2017-05-02 2018-11-13 中国科学院宁波材料技术与工程研究所 Oxide thin film transistor and its manufacturing method
CN108336145A (en) * 2018-01-29 2018-07-27 中国科学院微电子研究所 Artificial neuron structure, preparation method thereof and signal and time extraction method

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
Electrolyte-Gated WO3 Transistors: Electrochemistry, Structure, and Device Performance;Xiang Meng,et al;《The Journal of Physical Chemistry C》;20150827;第119卷(第37期);全文 *
Self-Bleaching Behaviors in Black-to-Transmissive Electrochromic Polymer Thin Films;Jiazhi He, et al;《ACS Applied Materials & Interfaces》;20170909;第9卷(第39期);全文 *

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