CN109545734B - Semiconductor structure and method of forming the same - Google Patents
Semiconductor structure and method of forming the same Download PDFInfo
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- CN109545734B CN109545734B CN201710866764.2A CN201710866764A CN109545734B CN 109545734 B CN109545734 B CN 109545734B CN 201710866764 A CN201710866764 A CN 201710866764A CN 109545734 B CN109545734 B CN 109545734B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5386—Geometry or layout of the interconnection structure
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
- H10D30/027—Manufacture or treatment of FETs having insulated gates [IGFET] of lateral single-gate IGFETs
- H10D30/0273—Manufacture or treatment of FETs having insulated gates [IGFET] of lateral single-gate IGFETs forming final gates or dummy gates after forming source and drain electrodes, e.g. contact first technology
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
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Abstract
A semiconductor structure and a method of forming the same, wherein the method comprises: providing a substrate, wherein the substrate comprises gate regions, and source-drain doped regions are arranged in the substrate between the gate regions; forming an electric connection layer on the source drain doping region; forming a grid structure and a dielectric layer on the substrate, wherein the grid structure is positioned on the grid region substrate, and the dielectric layer covers the electric connection layer and the exposed part of the grid structure; and removing the dielectric layer on the source drain doped region until the electric connection layer is exposed to form a contact hole, wherein the side wall of the contact hole is exposed to the grid structure. The method can reduce the difficulty of forming the contact hole.
Description
Technical Field
The present invention relates to the field of semiconductor manufacturing, and more particularly, to a semiconductor structure and a method for forming the same.
Background
An important semiconductor device is a MOS (metal-oxide-semiconductor) transistor whose basic structure includes: a semiconductor substrate; a gate structure located on a surface of the semiconductor substrate; a source region in the semiconductor substrate on one side of the gate structure and a drain region in the semiconductor substrate on the other side of the gate structure.
As the feature size is further reduced, the distance between adjacent gate structures is reduced, so that the process of forming contact holes for connecting the source region, the drain region and the upper metal line in the gap between the gate structures becomes difficult, and thus a process of forming self-aligned contact holes is introduced.
At present, a method for preparing a self-aligned contact hole, which is commonly used, includes: forming a grid structure on the surface of the semiconductor substrate; forming a side wall on the surface of the side wall of the grid structure; forming a protective layer on the top surface of the gate structure; forming an interlayer dielectric layer covering the semiconductor substrate, the protective layer and the side wall; and forming a contact hole penetrating the thickness of the interlayer dielectric layer in the interlayer dielectric layer, wherein the contact hole is positioned between the adjacent gate structures.
However, the formation of self-aligned contact holes is difficult.
Disclosure of Invention
The invention provides a semiconductor structure and a forming method thereof, which are used for improving the performance of a semiconductor device.
To solve the above technical problem, the present invention provides a method for forming a semiconductor structure, including: providing a substrate, wherein the substrate comprises gate regions, and source-drain doped regions are arranged in the substrate between the gate regions; forming an electric connection layer on the source drain doping region; forming a grid structure and a dielectric layer on the substrate, wherein the grid structure is positioned on the grid region substrate, and the dielectric layer covers the electric connection layer and the exposed part of the grid structure; and removing the dielectric layer on the source drain doped region until the electric connection layer is exposed to form a contact hole, wherein the side wall of the contact hole is exposed to the grid structure.
Optionally, the thickness of the electrical connection layer is: 20 to 50 nanometers.
Optionally, the ratio of the thickness of the electrical connection layer to the height of the gate structure is: 1:3 to 1: 2.
Optionally, the aspect ratio of the contact hole is: 3: 1-8: 1.
Optionally, the dielectric layer includes a first dielectric layer and a second dielectric layer located on the first dielectric layer; the forming steps of the first dielectric layer, the second dielectric layer, the grid structure and the source-drain doped region comprise: forming a pseudo gate structure on the gate region substrate; forming the source-drain doped regions in the substrate on two sides of the pseudo gate structure; forming the first dielectric layer on the substrate and the source-drain doped region, wherein the first dielectric layer covers the side wall of the pseudo gate structure and exposes the top surface of the pseudo gate structure; removing the pseudo gate structure, and forming a pseudo gate opening in the first dielectric layer; forming a grid structure in the pseudo grid opening; and forming a second dielectric layer on the first dielectric layer and the grid structure.
Optionally, before forming the first dielectric layer, forming the electrical connection layer; the substrate comprises a fin portion, and the gate structure spans the fin portion.
Optionally, when the material of the electrical connection layer is metal, the forming step of the electrical connection layer includes: forming initial electric connection films on the substrate, the source-drain doped region, the side wall and the top surface of the pseudo gate structure; removing part of the initial electric connection film to form an electric connection film, wherein the top surface of the electric connection film is lower than that of the pseudo-gate structure; removing the electric connection film between the source drain doped regions along the direction vertical to the extending direction of the fin portion to form the electric connection layer; the metal includes: tungsten, aluminum, or copper.
Optionally, when the electrical connection layer includes a doped layer and a metal silicide layer on the doped layer, the forming step of the electrical connection layer includes: forming initial doped material layers on the substrate, the source-drain doped regions, the side wall and the top surface of the pseudo gate structure; removing part of the initial doped material layer to form an initial doped film, wherein the top surface of the initial doped film is lower than that of the pseudo gate structure; removing the initial doped film on the substrate between the source drain doped regions in the direction perpendicular to the extending direction of the fin portion to form the doped film; and carrying out metallization treatment on part of the doped film to form the doped layer and a metal silicide layer positioned on the doped layer.
Optionally, the material of the doping layer is a semiconductor material; the material of the doped layer comprises silicon, and the doped layer is provided with doped ions.
Optionally, the concentration of the doping ions is: 1.0e14atm/cm2～1e20atm/cm2。
Optionally, the gate structure includes: the gate electrode layer is positioned on the gate dielectric layer; the step of forming the contact hole further comprises: and removing the dielectric layer on the grid structure until the grid layer is exposed.
Optionally, after forming the contact hole, the forming method further includes: and forming a plug on the electric connection layer in the contact hole.
The present invention also provides a semiconductor structure comprising: a substrate including a gate region; the grid structure is positioned on the grid region substrate, and a source drain doped region is arranged in the substrate between the grid structures; the electric connection layer is positioned on the source drain doping region; and the dielectric layer is positioned on the substrate and the electric connection layer, a contact hole is formed in the dielectric layer, the bottom of the contact hole is exposed out of the top surface of the electric connection layer, and the side wall of the contact hole is exposed out of the grid structure.
Optionally, the thickness of the electrical connection layer is: 20 to 50 nanometers.
Optionally, the ratio of the thickness of the electrical connection layer to the height of the gate structure is: 1:3 to 1: 2.
Optionally, the aspect ratio of the contact hole is: 3: 1-8: 1.
Optionally, when the material of the electrical connection layer is metal, the material of the electrical connection layer includes: tungsten, aluminum, or copper.
Optionally, the electrical connection layer includes a doping layer and a metal silicide layer located on the doping layer; the material of the doped layer is a semiconductor material; the material of the doped layer comprises silicon, and doped ions are arranged in the doped layer; the material of the metal silicide layer comprises: titanium silicon compound or nickel silicon compound.
Optionally, the concentration of the doping ions is: 1.0e14atm/cm2～1e20atm/cm2。
Optionally, the semiconductor structure further includes: a plug located in the contact hole.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following beneficial effects:
in the forming method of the semiconductor structure provided by the technical scheme of the invention, before the dielectric layer is formed, an electric connection layer is formed and is used for realizing the electric connection between the source-drain doped region and the plug formed subsequently. Because the electric connection layer is positioned on the source-drain doped region, the depth-to-width ratio of the groove positioned between the grid structures on two sides of the source-drain doped region is smaller, so that the etching gas can reach the bottom of the groove in a larger amount, fewer by-products are accumulated at the bottom of the groove, and the bottom of the formed contact hole is easier to open. And forming a plug in the contact hole subsequently, so that the plug can be electrically connected with the source-drain doped region, and the performance of the semiconductor device is improved.
Drawings
FIGS. 1-3 are schematic structural diagrams illustrating steps of a method for forming a semiconductor structure;
fig. 4 to 32 are schematic structural diagrams of steps of a method for forming a semiconductor structure according to an embodiment of the present invention.
Detailed Description
As described in the background, the formation of the self-aligned contact hole is difficult.
Fig. 1 to 3 are schematic structural diagrams of steps of a method for forming a semiconductor structure.
Referring to fig. 1, a substrate 100 is provided, wherein the substrate 100 includes a gate region a; forming a dummy gate structure (not shown) on the gate region a substrate 100; forming a source-drain doped region 102 in the substrate 100 between the dummy gate structures; forming a first dielectric layer 103 on the substrate 100 and the source-drain doped region 102, wherein the first dielectric layer 103 covers the side wall of the dummy gate structure and exposes the top surface of the dummy gate structure; removing the dummy gate structure, and forming a dummy gate opening (not shown in the figure) in the first dielectric layer 103; forming a gate structure 101 in the dummy gate opening; a second dielectric layer 104 is formed on the first dielectric layer 103 and the gate structure 101.
Referring to fig. 2, a photoresist 105 is formed on the second dielectric layer 104, and a mask opening (not marked in the figure) is formed in the photoresist 105, the mask opening is located on the source/drain doped region 102, and a dimension of the mask opening along a direction parallel to the surface of the substrate 100 is greater than a distance between adjacent gate structures 101.
Referring to fig. 3, the photoresist 105 is used as a mask to etch the first dielectric layer 103 and the second dielectric layer 104 until the top surfaces of the source-drain doped regions 102 are exposed, contact holes 106 are formed in the first dielectric layer 103 and the second dielectric layer 104, and the side walls of the gate structures 101 are exposed by the contact holes 106; after the contact hole 106 is formed, the photoresist 105 is removed.
In the above method, as the integration of the semiconductor device is continuously improved, the distance between the adjacent gate structures 101 is continuously reduced, so that the aspect ratio of the trench formed between the adjacent gate structures 101 is gradually increased. The larger aspect ratio of the trench makes it more and more difficult to form the contact hole 106. Specifically, the process for etching the first dielectric layer 103 and the second dielectric layer 104 by using the photoresist 105 as a mask includes: and the etching gas in the dry etching process comprises fluorocarbon gas and oxygen. The fluorocarbon gas is highly prone to produce polymer during the dry etching process, while oxygen can consume the polymer. As the aspect ratio of the trench between adjacent gate structures 101 is increased, so that the amount of oxygen reaching the bottom of the trench is small, and the consumption capacity of the polymer by the oxygen is small, the residual polymer is accumulated at the bottom of the trench, so that the bottom of the formed contact hole 106 is not opened. And forming a plug in the contact hole 106 later, so that the plug is difficult to be electrically connected with the source-drain doped region 102, which is not beneficial to improving the performance of the semiconductor device.
In order to solve the technical problem, the invention provides a method for forming a semiconductor structure, which comprises the following steps: a source drain doped region is arranged in the substrate between the grid regions; forming a grid structure on the grid region substrate; forming an electric connection layer on the source drain doping region; and removing the dielectric layer on the source drain doped region until the electric connection layer is exposed to form a contact hole, wherein the side wall of the contact hole is exposed to the grid structure. The method can reduce the difficulty of forming the contact hole and is beneficial to improving the performance of the semiconductor device.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 4 to 32 are schematic structural diagrams of steps of a method for forming a semiconductor structure according to an embodiment of the present invention.
Referring to fig. 4 and 5, fig. 4 is a top view of fig. 5 with the isolation structure omitted, fig. 5 is a schematic cross-sectional view taken along line a-a1 of fig. 4, providing a substrate 200, wherein the substrate 200 includes a plurality of gate regions i; forming a dummy gate structure 203 on the substrate 200 of the gate region I, wherein a side wall 206 is arranged on the side wall of the dummy gate structure 203; and forming a source-drain doped region in the substrate 200 at two sides of the dummy gate structure 203 and the side wall 206.
In this embodiment, the substrate 200 includes a first region B for forming an NMOS transistor and a second region C for forming a PMOS transistor. A plurality of dummy gate structures 203 are respectively located on the substrate 200 in the gate region i in the first region B and the second region C.
In other embodiments, the substrate includes only a first region for forming an NMOS transistor; alternatively, the first region is used to form a PMOS transistor.
In this embodiment, the substrate 200 includes: a substrate 201 and a fin 202 on the substrate 201. In other embodiments, the substrate may also be a planar substrate, such as a silicon substrate, a germanium substrate, or a silicon germanium substrate.
In this embodiment, the material of the fin 202 and the substrate 201 is silicon. In other embodiments, the material of the fin and the substrate includes germanium or silicon germanium.
In the present embodiment, the step of forming the substrate 200 includes: providing an initial substrate; and patterning the initial substrate to form a substrate 201 and a fin part 202 located on the substrate 201.
The substrate also has an isolation structure (not shown) covering a portion of the sidewalls of the fin 202, and a top surface of the isolation structure is lower than a top surface of the fin 202.
In this embodiment, the isolation structure is made of silicon oxide. In other embodiments, the material of the isolation structure may also be silicon oxynitride.
The dummy gate structure 203 includes: a dummy gate dielectric layer (not shown) on a portion of the sidewalls and the top surface of the fin 202, and a dummy gate layer (not shown) on the dummy gate dielectric layer.
The material of the pseudo gate dielectric layer comprises: silicon oxide, the material of the dummy gate layer comprises: silicon.
In this embodiment, the number of the dummy gate structures 203 is three.
A mask layer (not shown) is arranged on the top of the dummy gate structure 203, and the mask layer is made of: silicon nitride. In other embodiments, the material of the mask layer includes: silicon oxynitride.
The forming process of the mask layer comprises the following steps: chemical vapor deposition process.
The mask layer is used as a mask for forming the dummy gate structure 203 by etching.
The sidewall of the dummy gate structure 203 has a sidewall 206. The material of the sidewall 206 includes: silicon nitride. The sidewall spacers 206 are used to define the position where a source-drain doped region is formed subsequently, and protect the sidewalls of the dummy gate structure 203.
In this embodiment, the source-drain doped region in the fin 202 on both sides of the first region B pseudo gate structure 203 is a first source-drain doped region 204, and the source-drain doped region in the fin 202 on both sides of the second region C pseudo gate structure 203 is a second source-drain doped region 205.
The forming step of the first source-drain doped region 204 includes: forming first source-drain openings in the fin portions 202 on two sides of the first region B pseudo gate structure 203; forming a first epitaxial layer in the first source drain opening; and doping first source-drain ions into the first epitaxial layer to form the first source-drain doped region 204.
The conductivity type of the material of the first epitaxial layer and the first source-drain ions is related to the type of the transistor.
In this embodiment, the first region B is used to form an NMOS transistor, and the material of the first epitaxial layer includes: silicon carbide or silicon, the first source-drain ions are N-type ions, such as: phosphorus ions or arsenic ions.
In other embodiments, the first region is used to form a PMOS transistor, and the material of the first epitaxial layer includes: silicon germanium or silicon, the first ions being P-type ions such as: boron ions.
The forming step of the second source-drain doped region 205 includes: forming second source-drain openings in the fin portions 202 on two sides of the second region C pseudo gate structure 203; forming a second epitaxial layer in the second source-drain opening; second source-drain ions are doped into the second epitaxial layer to form the second source-drain doped region 205.
The conductivity type of the material of the second epitaxial layer and the second source-drain ions is related to the type of the transistor.
In this embodiment, the second region C is used for forming a PMOS transistor, and the material of the second epitaxial layer includes: silicon germanium or silicon, the second source-drain ions are P-type ions, such as: boron ions.
In other embodiments, the second region is for forming an NMOS transistor, and the material of the second epitaxial layer includes: silicon carbide or silicon, the second source-drain ions are N-type ions, such as: phosphorus ions or arsenic ions.
Referring to fig. 6, a first stop layer 207 is formed on the substrate 200, the source-drain doped region and the dummy gate structure 203, and on the sidewall of the sidewall spacer 206.
Fig. 6 is a schematic structural diagram based on fig. 5.
The material of the first stop layer 207 includes: silicon nitride, the formation process of the first stop layer 207 includes: chemical vapor deposition process.
In this embodiment, the first stop layer 207 covers top surfaces of the first source-drain doped region 204 and the second source-drain doped region 205.
The first stop layer 207 is used as an etching stop layer when a contact hole is formed on the source-drain doped region in the following step.
Referring to fig. 7, the first stop layer 207 on the top of the source/drain doped region is removed to expose the top surface of the source/drain doped region.
Fig. 7 is a schematic structural diagram based on fig. 6.
In this embodiment, the removing the first stop layer 207 on the top of the source-drain doped region specifically means: the first stop layer 207 on top of the first source drain doped region 204 and the second source drain doped region 205 is removed.
In this embodiment, the first stop layer 207 on the top of the first source-drain doped region 204 and the top of the second source-drain doped region 205 are removed to expose the top surfaces of the first source-drain doped region 204 and the second source-drain doped region 205, which is beneficial to realizing the electrical connection between the electrical connection layer formed subsequently and the first source-drain doped region 204 and between the electrical connection layer and the second source-drain doped region 205.
The process for removing the first stop layer 207 on the top of the source-drain doped region includes: one or two of the dry etching process and the wet etching process are combined.
Removing the first stop layer 207 on the top of the source-drain doped region, including: and forming an electric connection layer on the source drain doped region. In this embodiment, the electrical connection layer includes: the doped layer and the metal silicide layer on the doped layer. Please refer to fig. 8 to fig. 31.
Referring to fig. 8, an initial doped material layer 208 is formed on the substrate 200 and the source/drain doped regions.
Fig. 8 is a schematic structural diagram based on fig. 7.
In the present embodiment, the material of the initial doped material layer 208 is a semiconductor material, the initial doped material layer 208 includes silicon, and the initial doped material layer 208 has doped ions therein.
In this embodiment, the material of the initial doped material layer 208 is a semiconductor material, so that metal contamination is small, which is beneficial to improving the performance of the semiconductor device.
The formation process of the initial electric-connection material film 208 includes: and (5) in-situ doping.
The concentration of the doping ions is as follows: 1.0e14atm/cm2～1e20atm/cm2。
The doped ions make the formed initial electrical connection film 208 have stronger conductivity, which is beneficial to improving the electrical characteristics of the electrical connection layer and the source-drain doped region formed subsequently.
In the embodiment, the doping ions in the initial doping material layer 208 in the first region B and the initial doping material layer in the second region C are the same, which is beneficial to reducing the complexity of the process and the cost.
In other embodiments, the conductivity type of the dopant ions in the initial doped material layer of the first region is the same as the conductivity type of the first source drain ions in the first source drain doped region; the conductivity type of the doped ions in the initial doped material layer of the second region is the same as the conductivity type of the second source drain ions in the second source drain doped region.
The thickness of the initial doped material layer 208 is: 150 nm to 250 nm, and the thickness of the initial doped material layer 208 determines the thickness of the subsequently formed initial doped film.
The initial doping material layer 208 is used for the subsequent formation of an initial doping film.
Referring to fig. 9, a portion of the initial doping material layer 208 is removed to form an initial doping film 258, wherein the top of the initial doping film 258 is lower than the top surface of the dummy gate structure 203.
Fig. 9 is a schematic structural diagram based on fig. 8.
The process of removing a portion of the initial doped material layer 208 includes: one or two of the dry etching process and the wet etching process are combined.
The initial doped film 258 on the source and drain doped regions is used for the subsequent formation of doped films.
The top of the initial doping film 258 is lower than the top surface of the dummy gate structure 203, which is beneficial to forming a contact hole subsequently.
The ratio of the thickness of the initial doped film 258 to the height of the dummy gate structure 203 is: 1:3 to 1: 2. The ratio of the thickness of the initial doped film 258 to the height of the dummy gate structure 203 determines the ratio of the thickness of the subsequently formed electrical connection layer to the height of the gate structure.
Referring to fig. 10 to 12, fig. 10 is a top view of fig. 11 and 12 with the isolation structure omitted, fig. 11 is a cross-sectional view taken along line a-a1 of fig. 10, fig. 12 is a cross-sectional view taken along line B-B1 of fig. 10, and after forming an initial doped film 258, a first material layer 209 is formed on the initial doped film 258; forming a first bottom anti-reflection layer (not shown) on the first material layer 209; after forming the first bottom anti-reflection layer, a first photoresist 210 is formed on the source drain doped region.
The cross-sectional direction of fig. 11 coincides with the cross-sectional direction of fig. 5.
The material of the first material layer 209 includes: amorphous carbon, the process of forming the first material layer 209 includes: and (4) spin coating. The first material layer 209 is used for transferring the pattern of the photoresist to the first material layer 209 in a subsequent step and is used as a mask layer for a subsequent etching process.
The material of the first bottom anti-reflection layer comprises: a bottom antireflective material. The first bottom anti-reflection layer is used for reducing refraction and reflection of light during subsequent exposure and development.
The first photoresist 210 is located on the source-drain doped region, which is beneficial to removing the initial doped film 258 between the source-drain doped region.
Referring to fig. 13 and 14, with the first photoresist 210 as a mask, the first bottom anti-reflection layer, the first material layer 209 (see fig. 12), and the initial doping film 258 (see fig. 12) are etched until the isolation structure (not shown) is exposed, and a doping film 211 is formed on the source and drain doping regions; after the doped film 211 is formed, the first photoresist 210 (see fig. 11), the first bottom anti-reflection layer, and the first material layer 209 (see fig. 11) are removed, exposing the top surface of the electrical connection layer 211.
Fig. 13 is a schematic configuration diagram based on fig. 11, and fig. 14 is a schematic configuration diagram based on fig. 12.
The process of etching the first bottom anti-reflection layer, the first material layer 209 and the initial doping film 258 by using the first photoresist 210 as a mask includes: one or two of the dry etching process and the wet etching process are combined.
The thickness of the doped film 211 is determined by the thickness of the initial doped film 208.
The thickness of the doped film 211 is: 20 nm to 50 nm, the thickness of the doped film 211 being chosen in the sense that: if the thickness of the doped film 211 is less than 20 nm, the depth-to-width ratio of the trench formed by the adjacent gate structures formed subsequently is larger, so that the difficulty of forming contact holes subsequently is larger; if the thickness of the doped film 211 is greater than 50 nm, the resistance of the doped film 211 is too high, which is not favorable for improving the performance of the semiconductor device.
The ratio of the thickness of the doped film 211 to the height of the dummy gate structure 203 is determined by the ratio of the thickness of the initial doped film 258 to the height of the dummy gate structure 203. The ratio of the thickness of the doped film 211 to the height of the dummy gate structure 203 is: 1:3 to 1: 2.
The significance of selecting the ratio of the thickness of the doped film 211 to the height of the dummy gate structure 203 is that: if the ratio of the thickness of the doped film 211 to the height of the dummy gate structure 203 is less than 1:3, the depth-to-width ratio of a groove formed by the subsequent adjacent gate structures is still larger, and the difficulty of forming a contact hole subsequently is still larger; if the ratio of the thickness of the doped film 211 to the height of the dummy gate structure 203 is greater than 1:2, the resistance of the doped film 211 is too large, which is not favorable for improving the performance of the semiconductor device.
The removal of the initial doped film 258 between the source and drain doped regions along a direction perpendicular to the extension direction of the fin 202 facilitates the subsequent formation of a dielectric layer on the doped film 211, wherein the dielectric layer is used for realizing the electrical isolation between the doped films 211.
The process of removing the first photoresist 209, the first bottom anti-reflection layer and the first material layer 209 includes: and (5) ashing.
The first photoresist 209, the first bottom anti-reflection layer and the first material layer 209 are removed to expose the top of the doped film 211, which is beneficial to forming a first dielectric layer on the doped film 211 subsequently.
Referring to fig. 15, a first dielectric film 212 is formed on the substrate 200 and the doped film 211, and on the sidewall and the top surface of the dummy gate structure 203.
Fig. 15 is a schematic configuration diagram based on fig. 13.
The material of the first dielectric film 212 comprises: silicon oxide, the forming process of the first dielectric film 212 comprises the following steps: chemical vapor deposition process. The first dielectric film 212 formed by the chemical vapor deposition process has a strong filling capability to the trench between the adjacent dummy gate structures 203, and the isolation performance of the first dielectric film 212 is good.
The first dielectric film 212 is used for forming a first dielectric layer in the following.
Referring to fig. 16, the first dielectric film 212 is planarized until the mask layer (not shown) on the top surface of the dummy gate structure 203 is exposed, so as to form a first dielectric layer 213.
Fig. 16 is a schematic configuration diagram based on fig. 15.
The process for planarizing the first dielectric film 212 includes: and (5) carrying out a chemical mechanical polishing process.
And flattening the first dielectric film 212 to expose the mask layer on the top of the dummy gate structure 203, so as to be beneficial to removing the dummy gate structure 203 subsequently.
Referring to fig. 17, the dummy gate structure 203 is removed, and a dummy gate opening (not shown) is formed in the first dielectric layer 213; forming an initial gate structure (not shown in the figure) in the dummy gate opening; removing a portion of the initial gate structure to form a gate structure 214 and a first opening (not shown) on the gate structure 214; a protective film 215 is formed within the first opening and on the first dielectric layer 213.
The step of removing the dummy gate structure 203 includes: removing the pseudo gate dielectric layer; and removing the dummy gate layer after removing the dummy gate dielectric layer.
The process for removing the pseudo gate dielectric layer comprises the following steps: one or two of the dry etching process and the wet etching process are combined.
The process for removing the dummy gate layer comprises the following steps: one or two of the dry etching process and the wet etching process are combined.
The initial gate structure includes: a gate dielectric layer and an initial gate layer on the gate dielectric layer.
The material of the gate dielectric layer comprises a high-K dielectric material, and the high-K dielectric material refers to a material with a dielectric constant larger than 3.9, such as: HfO2、HfSiON、HfAlO2、ZrO2Or Al2O3. The material of the initial gate layer is metalSuch as: tungsten.
The forming step of the gate structure 214 includes: and removing part of the initial gate layer to form a gate layer. The gate structure 214 includes: the gate dielectric layer and the gate electrode layer are positioned on the gate dielectric layer.
The process for removing part of the initial gate layer comprises the following steps: and (5) wet etching process.
The material of the protective film 215 includes: silicon nitride, the formation process of the protective film 215 includes: a chemical vapor deposition process or a physical vapor deposition process.
The protective film 215 is used for the subsequent formation of a protective layer.
Referring to fig. 18, the protective film 215 (see fig. 17) is planarized until the top surface of the first dielectric layer 213 is exposed, and a protective layer 216 is formed on the gate structure 214.
The process of planarizing the protective film 215 includes: and (5) carrying out a chemical mechanical polishing process.
The material of the protective layer 216 includes: silicon nitride, the protective layer 216 serving to protect the top surface of the gate structure 214.
Referring to fig. 19 to 21, fig. 19 is a top view of fig. 20 and 21 with the isolation structure omitted, fig. 20 is a cross-sectional view taken along line a-a1 of fig. 19, fig. 21 is a cross-sectional view taken along line B-B1 of fig. 19, and a second dielectric layer 217 is formed on the substrate 200, the protective layer 216 and the first dielectric layer 213; forming a second stop film 218 on the second dielectric layer 217; forming a second material layer 219 on the second stopper film 218; forming a second bottom anti-reflection layer (not shown) on the second material layer; and forming a second photoresist 220 on the second bottom anti-reflection layer between the source and drain doped regions.
The material of the second dielectric layer 217 comprises: silicon oxide, and the forming process of the second dielectric layer 217 comprises the following steps: chemical vapor deposition process.
The dielectric layer includes: a first dielectric layer 213 and a second dielectric layer 217 on the first dielectric layer 213.
The material of the second stopper film 218 includes: titanium nitride, the process of forming the second stopper film 218 includes: chemical vapor deposition process.
The second stop film 218 is used for the subsequent formation of a second stop layer.
The material, formation process and function of the second material layer 219 are the same as those of the first material layer 209, and are not described herein again.
The material of the second bottom anti-reflection layer is the same as that of the first bottom anti-reflection layer, and is not described herein.
The second photoresist 220 is used for a mask layer for a subsequent formation of a second stop layer.
Referring to fig. 22 to 24, fig. 22 is a top view of fig. 23 and fig. 24 omitting the isolation structure, fig. 23 is a schematic cross-sectional view taken along line AA1 of fig. 22, fig. 24 is a schematic cross-sectional view taken along line BB1 of fig. 22, and the second bottom anti-reflection layer, the second material layer 219 and the second stop film 218 are etched by using the second photoresist 220 as a mask until the top surface of the second dielectric layer 217 is exposed, and a second stop layer 221 is formed on the second dielectric layer 217 between the source and drain doped regions; after the second stop layer 221 is formed, the second photoresist 220, the second bottom anti-reflection layer and the second material layer 219 are removed to expose the top surface of the second stop layer 221.
Fig. 22 is a schematic configuration diagram based on fig. 19, fig. 23 is a schematic configuration diagram based on fig. 20, and fig. 24 is a schematic configuration diagram based on fig. 21.
The forming process of the second stop layer 221 includes: one or two of the dry etching process and the wet etching process are combined.
The process of removing the second photoresist 220, the second bottom anti-reflection layer and the second material layer 219 includes: and (5) ashing.
The second stop layer 221 is used for an etching stop layer in the subsequent formation of the second opening.
Referring to fig. 25 to 27, fig. 25 is a top view of fig. 26 and 27 with the isolation structure omitted, fig. 26 is a cross-sectional view taken along line AA1 of fig. 25, fig. 27 is a cross-sectional view taken along line BB1 of fig. 25, and a third material layer 222 is formed on the second dielectric layer 217 and the second stop layer 221; forming a third bottom anti-reflection layer (not shown) on the third material layer 222; a third photoresist 223 is formed on the third bottom anti-reflection layer.
Fig. 25 is a schematic configuration diagram based on fig. 22, fig. 26 is a schematic configuration diagram based on fig. 23, and fig. 27 is a schematic configuration diagram based on fig. 24.
The material, formation process and function of the third material layer 222 are the same as those of the first material layer 209, and are not described herein again.
The material of the third bottom anti-reflection layer is the same as that of the first bottom anti-reflection layer, and is not described herein.
The third photoresist 223 is used for forming a mask layer of a second opening later.
Referring to fig. 28, the third bottom anti-reflection layer, the third material layer 222, the second dielectric layer 217 and the first dielectric layer 213 are etched by using the third photoresist 223 as a mask until the doped film 211 is exposed, so as to form a second opening 224; after the second opening 224 is formed, the third photoresist 223, the third bottom anti-reflection layer and the third material layer 222 are removed to expose the top of the second dielectric layer 217.
Fig. 28 is a schematic configuration diagram based on fig. 26.
The forming process of the second opening 224 includes: one or two of the dry etching process and the wet etching process are combined.
In this embodiment, the second opening 224 located in the first region B is used for forming a first contact hole later, and the second opening 224 located in the second region C is used as a second contact hole of the second region C.
In other embodiments, the second opening in the first region is a first contact hole, and the second opening in the second region is a second contact hole.
Due to the fact that the doped film 211 is arranged on the source-drain doped region, the dielectric layer on the source-drain doped region is removed, the depth-to-width ratio of the formed second opening 224 is small, and specifically, the depth-to-width ratio of the second opening 224 is 3: 1-8: 1. The aspect ratio of the second opening 224 is selected in the sense that: if the aspect ratio of the second opening 224 is smaller than 3:1, the thickness of the doped film 211 is too thick, and the thickness of the doped film 211 is too thick, so that the resistance of the doped film 211 is large, which is not beneficial to improving the electrical performance of the semiconductor device; if the aspect ratio of the second opening 224 is greater than 8:1, the difficulty of removing the dielectric layer on the source/drain doped region is large.
The process of removing the third photoresist 223, the third bottom anti-reflection layer and the third material layer 222 includes: and (5) ashing.
After the second opening 224 is formed, the method further includes: and removing the second dielectric layer 217 on the first region I gate structure 214 to form a first contact hole, wherein the bottom of the first contact hole exposes the first region I gate structure 214 and the top surface of the doped film 211 on the first source drain doped region 204. The first contact hole formation step is specifically shown in fig. 29 to 30.
Referring to fig. 29, a fourth material layer 225 is formed in the second opening 224 (see fig. 28) and on the second dielectric layer 217; forming a fourth bottom anti-reflection layer (not shown) on the fourth material layer 225; a fourth photoresist 226 is formed on the fourth bottom anti-reflection layer, and a mask opening (not marked in the figure) is formed in the fourth photoresist 226, and the mask opening is located on the first region i gate structure 214, the first source/drain doping region 204, and the second region ii gate structure 214.
The material, formation process and function of the fourth material layer 225 are the same as those of the first material layer 209, and are not described herein again.
The material of the fourth bottom anti-reflection layer is the same as that of the first bottom anti-reflection layer, and is not described herein.
The fourth photoresist 226 is used as a mask layer for the subsequent formation of the first contact hole.
The mask opening is used to define the size and position of the first contact hole and the third contact hole.
Referring to fig. 30, the fourth bottom anti-reflection layer, the fourth material layer 225, the second dielectric layer 217 and the mask layer are etched by using the fourth photoresist 226 as a mask until the top surface of the gate layer is exposed, so as to form a first contact hole 227; after the first contact hole 227 is formed, the fourth photoresist 226, the fourth bottom anti-reflection layer and the fourth material layer 225 are removed, exposing the sidewall and the bottom surface of the second opening 224.
The forming process of the first contact hole 227 includes: one of a wet etching process and a dry etching process.
The first contact hole 227 is located on the first i-region gate structure 214 and the first source/drain doped region 204, and the first contact hole 227 is used for subsequently accommodating a first conductive plug.
During the formation of the first contact hole 227, the second dielectric layer 217 on top of the second region ii gate structure 214 is also removed, and a third contact hole 250 is formed in the dielectric layer 217 on the second region ii gate structure 214, wherein the third contact hole 250 is used for subsequently receiving a third conductive plug.
The second opening 224 is used to subsequently receive a second conductive plug.
Referring to fig. 31, the doped film 211 at the bottom of the first contact hole 227 and the second opening 224 is metalized to form a doped layer (not shown) and a metal silicide layer 228 on the doped layer.
In this embodiment, all the doped films 211 are metallized, that is: the metal silicide layer 228 is the electrical connection layer 270. In other embodiments, a portion of the electrical connection layer is metallized, the electrical connection layer comprising: the doped layer and the metal silicide layer on the doped layer.
In this embodiment, all the doping films 211 are metalized, which is beneficial to avoiding the problem of large resistance of the doping layer, and is further beneficial to improving the electrical performance of the semiconductor device.
The forming step of the metal silicide layer 228 includes: forming a metal layer on the second dielectric layer 217 and in the first contact hole 227, the second opening 224 and the third contact hole 250; annealing the metal layer; after the annealing treatment, the metal layer which is not reacted with the source/drain doped region is removed, and a metal silicide layer 228 is formed at the bottom of the first contact hole 227 and the second opening 224.
The material of the metal layer comprises: titanium or nickel. Accordingly, the material of the metal silicide layer 228 includes: titanium silicon compound or nickel silicon compound.
The metal silicide layer 228 at the bottom of the first contact hole 227 is used to reduce the contact resistance between the first source/drain doped region 204 and the subsequently formed first conductive plug. The metal silicide layer 228 at the bottom of the second opening 224 is used to reduce the contact resistance between the second source/drain doped region 205 and a subsequently formed second conductive plug.
In other embodiments, the material of the electrical connection layer is metal, and the forming step of the electrical connection layer includes: forming initial electric connection films on the substrate, the source-drain doped region, the side wall and the top surface of the pseudo gate structure; removing part of the initial electric connection film to form an electric connection film, wherein the top surface of the electric connection film is lower than that of the pseudo-gate structure; and removing the electric connection film on the substrate between the source drain doped regions in the direction perpendicular to the extending direction of the fin part to form the electric connection layer.
Referring to fig. 32, after the electrical connection layer 270 is formed, a first conductive plug 229 is formed in the first contact hole 227; forming a second conductive plug 230 within the second opening 224; the third plug 231 is formed within the third contact hole 250 (see fig. 30).
In this embodiment, the first conductive plug 229, the second conductive plug 230, and the third conductive plug 231 are formed at the same time. In other embodiments, the first, second, and third conductive plugs are not formed simultaneously.
In this embodiment, the forming steps of the first conductive plug 229, the second conductive plug 230, and the third conductive plug 231 include: forming a plug material layer in the first contact hole 227, the second opening 224 and the third contact hole 250 and on the second dielectric layer 217; planarizing the plug material layer until the top surface of the second dielectric layer 217 is exposed, forming a first conductive plug 229 in the first contact hole 227, forming a second conductive plug 230 in the second opening 224, and forming a third conductive plug 231 in the third contact hole 250.
The material of the plug material layer is metal, such as: tungsten.
The process of planarizing the plug material layer includes: and (5) carrying out a chemical mechanical polishing process.
Accordingly, an embodiment of the present invention further provides a semiconductor structure formed by the above method, with reference to fig. 31, including:
the substrate 200 comprises a grid electrode region I;
the grid structure 214 is positioned on the substrate 200 in the grid region I, and a source and drain doped region is arranged in the substrate 200 between the grid structures 214;
an electrical connection layer 270 on the source and drain doped regions;
and a dielectric layer on the substrate 200 and the electrical connection layer 270, the dielectric layer having a contact hole therein, the bottom of the contact hole exposing the top surface of the electrical connection layer 270.
The thickness of the electrical connection layer 270 is: 20 to 50 nanometers.
The ratio of the thickness of the electrical connection layer 270 to the height of the gate structure 214 is: 1:3 to 1: 2.
The aspect ratio of the second opening is: 3: 1-8: 1.
When the material of the electrical connection layer 270 is metal, the material of the electrical connection layer 270 includes: tungsten, aluminum, or copper.
The electrical connection layer 270 includes a doped layer and a metal silicide layer 228 on the doped layer; the material of the doped layer is a semiconductor material; the material of the doped layer comprises silicon, and doped ions are arranged in the doped layer; the material of the metal silicide layer 228 includes: titanium silicon compound or nickel silicon compound.
The semiconductor structure further includes: a plug located in the contact hole.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (12)
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| CN102903753A (en) * | 2011-07-29 | 2013-01-30 | 三星电子株式会社 | Semiconductor device including variable resistance material and manufacturing method thereof |
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| CN102903753A (en) * | 2011-07-29 | 2013-01-30 | 三星电子株式会社 | Semiconductor device including variable resistance material and manufacturing method thereof |
| CN106601685A (en) * | 2015-10-16 | 2017-04-26 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and preparation method thereof, and electronic device |
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