CN109541424B - Device for testing electric stress of PDFN (polymer dispersed non-leaded semiconductor) packaged MOS (metal oxide semiconductor) tube and switching power supply - Google Patents
Device for testing electric stress of PDFN (polymer dispersed non-leaded semiconductor) packaged MOS (metal oxide semiconductor) tube and switching power supply Download PDFInfo
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- CN109541424B CN109541424B CN201811187686.4A CN201811187686A CN109541424B CN 109541424 B CN109541424 B CN 109541424B CN 201811187686 A CN201811187686 A CN 201811187686A CN 109541424 B CN109541424 B CN 109541424B
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- 238000012360 testing method Methods 0.000 title claims abstract description 58
- 239000004065 semiconductor Substances 0.000 title claims abstract description 10
- 229910044991 metal oxide Inorganic materials 0.000 title claims abstract description 8
- 150000004706 metal oxides Chemical class 0.000 title claims abstract description 8
- 229920000642 polymer Polymers 0.000 title claims abstract description 7
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 12
- 229910052802 copper Inorganic materials 0.000 claims description 12
- 239000010949 copper Substances 0.000 claims description 12
- 238000005476 soldering Methods 0.000 claims description 6
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 4
- 238000004806 packaging method and process Methods 0.000 abstract description 5
- 238000009434 installation Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 2
- 230000020169 heat generation Effects 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 238000012356 Product development Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 150000003071 polychlorinated biphenyls Chemical class 0.000 description 1
- 238000009662 stress testing Methods 0.000 description 1
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/26—Testing of individual semiconductor devices
- G01R31/2601—Apparatus or methods therefor
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/40—Testing power supplies
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- General Physics & Mathematics (AREA)
- Testing Of Individual Semiconductor Devices (AREA)
Abstract
The invention relates to a device for testing electric stress of a PDFN (polymer dispersed non-leaded) packaging MOS (metal oxide semiconductor) tube and a switching power supply. The device comprises a double-layer PCB, wherein the double-layer PCB comprises a first connecting surface and a second connecting surface; the first connection face comprises a first drain connection region and a first gate connection region; the second connection surface comprises a second drain connection region, a second gate connection region and a second source connection region; the first drain electrode connecting region is connected with the second drain electrode connecting region through a through hole, and the first grid electrode connecting region is connected with the second grid electrode connecting region through a through hole; the first connecting surface of the double-layer PCB is connected to the mounting position of the MOS tube of the product to be tested, and the MOS tube is connected to the second connecting surface of the double-layer PCB. The invention aims at the test of the current and voltage stress of the compact product with high power density, avoids the damage of searching test points and connecting lines to the product or the test points, and reduces the test implementation difficulty and the test period.
Description
Technical Field
The invention relates to the field of testing of switching power supplies, in particular to a device for testing electric stress of a PDFN (polymer dispersed non-leaded) packaged MOS (metal oxide semiconductor) transistor and a switching power supply.
Background
Since the invention of switching power supply by human in the second half of the 20 th century, the technology has greatly pushed the development of power electronics. Due to their advantages of miniaturization, high efficiency, high power density, and high reliability, their applications have penetrated into the corners of human life. The process and integration of the corresponding power devices is also constantly being improved and enhanced. The power density of the switching power supply is also constantly refreshed.
Due to the continuous miniaturization of power devices and the application of multilayer PCBs in the field of power electronics, it is becoming more and more difficult to implement electrical stress testing of components, which is one of product reliability tests in the product development phase. At present, the method of cutting off PCB gold channels is mainly adopted to test the current stress for the test of the compact patch power device, and if a multilayer PCB board with high power density and electric through holes is encountered, the preparation work of wiring wastes time and easily causes the damage of the PCB or components.
Disclosure of Invention
The present invention provides a device for testing electrical stress of a PDFN packaged MOS transistor and a switching power supply, aiming at the above-mentioned defects of the prior art.
The technical scheme adopted by the invention for solving the technical problems is as follows: the device for testing the electrical stress of the PDFN (Polymer dispersed Fall) packaged MOS (Metal oxide semiconductor) tube is constructed and applied to the test of the MOS tube of a product to be tested, and comprises a double-layer PCB (printed Circuit Board), wherein the double-layer PCB comprises a first connecting surface and a second connecting surface;
the first connection face comprises a first drain connection region and a first gate connection region; the second connection surface comprises a second drain connection region, a second gate connection region, and a second source connection region;
the first drain electrode connecting region is connected with the second drain electrode connecting region through a through hole, and the first grid electrode connecting region is connected with the second grid electrode connecting region through a through hole;
the first connecting surface of the double-layer PCB is connected to the MOS tube mounting position of the product to be tested, and the MOS tube is connected to the second connecting surface of the double-layer PCB.
Further, in the device for testing electrical stress of a PDFN packaged MOS transistor according to the present invention, the first drain connection region is connected to a drain mounting location on the product to be tested for mounting a MOS transistor;
the first grid connection region is connected to a grid installation position on the product to be tested, wherein the grid installation position is used for installing an MOS (metal oxide semiconductor) tube.
Further, according to the device for testing the electrical stress of the PDFN package MOS tube, the first drain electrode connecting area is connected to a drain electrode mounting position for mounting the MOS tube on the product to be tested through soldering tin;
the first grid connection area is connected to a grid installation position used for installing an MOS tube on the product to be tested through soldering tin.
Further, according to the device for testing the electrical stress of the PDFN package MOS tube, the second source electrode connecting area is connected with the source electrode mounting position, used for mounting the MOS tube, on the product to be tested through a wire.
Further, according to the device for testing the electrical stress of the PDFN package MOS tube, the drain electrode of the MOS tube is connected with the second drain electrode connection region, the grid electrode of the MOS tube is connected with the second grid electrode connection region, and the source electrode of the MOS tube is connected with the second source electrode connection region.
Further, according to the device for testing the electrical stress of the PDFN package MOS transistor, the first drain connection region is connected with the second drain connection region through at least two through holes, and the first grid connection region is connected with the second grid connection region through at least two through holes.
Furthermore, according to the device for testing the electrical stress of the PDFN packaging MOS tube, the first drain electrode connecting area and the first grid electrode connecting area are copper layers;
the second drain connection region, the second gate connection region, and the second source connection region are copper layers.
Further, according to the device for testing the electrical stress of the PDFN package MOS transistor, the first drain electrode connection region is connected with the second drain electrode connection region through the copper through hole, and the first grid electrode connection region is connected with the second grid electrode connection region through the copper through hole.
Furthermore, the device for testing the electrical stress of the PDFN packaged MOS tube is a high-power MOS tube packaged by the PDFN.
In addition, the invention also provides a switching power supply, wherein the MOS tube in the switching power supply is tested by using the device for testing the electrical stress of the PDFN packaging MOS tube.
The device for testing the electrical stress of the PDFN packaging MOS tube and the switching power supply have the following beneficial effects that: the device comprises a double-layer PCB, wherein the double-layer PCB comprises a first connecting surface and a second connecting surface; the first connection face comprises a first drain connection region and a first gate connection region; the second connection surface comprises a second drain connection region, a second gate connection region and a second source connection region; the first drain electrode connecting region is connected with the second drain electrode connecting region through a through hole, and the first grid electrode connecting region is connected with the second grid electrode connecting region through a through hole; the first connecting surface of the double-layer PCB is connected to the mounting position of the MOS tube of the product to be tested, and the MOS tube is connected to the second connecting surface of the double-layer PCB. The invention aims at the test of the current and voltage stress of the compact product with high power density, avoids the damage of searching test points and connecting lines to the product or the test points, and reduces the test implementation difficulty and the test period.
Drawings
The invention will be further described with reference to the accompanying drawings and examples, in which:
FIG. 1 is a schematic structural diagram of a first connection surface of a device for testing electrical stress of a PDFN package MOS transistor according to the present invention;
fig. 2 is a schematic structural diagram of a second connection surface of the device for testing electrical stress of a PDFN packaged MOS transistor according to the present invention.
Detailed Description
For a more clear understanding of the technical features, objects and effects of the present invention, embodiments of the present invention will now be described in detail with reference to the accompanying drawings.
Refer to fig. 1 and 2.
The invention provides a device for testing the electrical stress of a PDFN (Polymer dispersed FN) packaged MOS (Metal oxide semiconductor) tube, which is applied to the test of the MOS tube of a product to be tested.
Referring to fig. 1, the first connection face 10 includes a first drain connection region 101 and a first gate connection region 102.
Referring to fig. 2, the second connection face 20 includes a second drain connection region 201, a second gate connection region 202, and a second source connection region 203.
The first drain connection region 101 is connected to the second drain connection region 201 through a via 30, and the first gate connection region 102 is connected to the second gate connection region 202 through a via 30;
the first connection surface 10 of the double-layer PCB is connected to the MOS tube mounting position of the product to be tested, and the MOS tube is connected to the second connection surface 20 of the double-layer PCB.
Further, in the device for testing the electrical stress of the PDFN package MOS tube, the first drain connection region 101 is connected to a drain mounting position for mounting the MOS tube on a product to be tested;
the first gate connection region 102 is connected to a gate mounting location on a product to be tested for mounting a MOS transistor.
Further, according to the device for testing the electrical stress of the PDFN package MOS tube, the first drain electrode connection area 101 is connected to a drain electrode installation position for installing the MOS tube on a product to be tested through soldering tin;
the first gate connection region 102 is connected to a gate mounting location for mounting a MOS transistor on a product to be tested by soldering.
Further, in the device for testing the electrical stress of the PDFN packaged MOS transistor of the present invention, the second source connection region 203 is connected to a source mounting location for mounting a MOS transistor on a product to be tested through a wire. Through the wire connection, the current stress between the source electrode and the drain electrode of the MOS tube can be measured. The current measuring instrument can be selected according to the requirement, and the detailed description is omitted here.
Further, according to the device for testing the electrical stress of the PDFN packaged MOS transistor of the present invention, the drain of the MOS transistor is connected to the second drain connection region 201, the gate of the MOS transistor is connected to the second gate connection region 202, and the source of the MOS transistor is connected to the second source connection region 203. When measuring the gate signal of the MOS transistor, a wire may be directly soldered to the second gate connection region 202. The voltage measuring instrument can be selected according to the requirement, and the detailed description is omitted.
Further, according to the device for testing the electrical stress of the PDFN packaged MOS transistor of the present invention, the first drain connection region 101 is connected to the second drain connection region 201 through at least two vias 30, and the first gate connection region 102 is connected to the second gate connection region 202 through at least two vias 30.
Furthermore, in the device for testing the electrical stress of the PDFN package MOS transistor, the first drain connection region 101 and the first gate connection region 102 are copper layers;
the second drain connection region 201, the second gate connection region 202 and the second source connection region 203 are copper layers.
It can be understood that the drain current of the MOS transistor can reach 50A-120A, and such a large current can cause a large amount of heat generation, so the present invention provides the first drain connection region 101 and the second drain connection region 201 with a large area, and the number of the through holes 30 connecting the first drain connection region 101 and the second drain connection region 201 is also large, thereby providing a larger current cross section and greatly reducing the heat generation problem caused by a large current.
The above-mentioned passing arrangement
Further, according to the device for testing the electrical stress of the PDFN packaged MOS transistor of the present invention, the first drain connection region 101 is connected to the second drain connection region 201 through a copper via, and the first gate connection region 102 is connected to the second gate connection region 202 through a copper via.
Furthermore, the device for testing the electrical stress of the PDFN packaged MOS tube is a high-power MOS tube packaged by the PDFN.
In addition, the invention also provides a switching power supply, wherein the MOS tube in the switching power supply is tested by using the device for testing the electrical stress of the PDFN packaging MOS tube.
The invention aims at the test of the current and voltage stress of the compact product with high power density, avoids the damage of searching test points and connecting lines to the product or the test points, and reduces the test implementation difficulty and the test period.
The above embodiments are merely illustrative of the technical concepts and features of the present invention, and the purpose of the embodiments is to enable those skilled in the art to understand the contents of the present invention and implement the present invention accordingly, and not to limit the protection scope of the present invention. All equivalent changes and modifications made within the scope of the claims of the present invention should be covered by the claims of the present invention.
Claims (9)
1. A device for testing the electrical stress of a PDFN (Polymer dispersed Fall) packaged MOS (Metal oxide semiconductor) transistor is applied to the electrical stress test of the MOS transistor of a product to be tested, and is characterized by comprising a double-layer PCB (printed Circuit Board), wherein the double-layer PCB comprises a first connecting surface (10) and a second connecting surface (20);
said first connection face (10) comprising a first drain connection region (101) and a first gate connection region (102); the second connection face (20) comprises a second drain connection region (201), a second gate connection region (202), and a second source connection region (203);
said first drain connection region (101) being connected to said second drain connection region (201) by a via (30), said first gate connection region (102) being connected to said second gate connection region (202) by a via (30);
the first connecting surface (10) of the double-layer PCB is connected to the MOS tube mounting position of the product to be tested, and the MOS tube is connected to the second connecting surface (20) of the double-layer PCB.
2. The device for testing electrical stress of a PDFN packaged MOS transistor as claimed in claim 1, wherein the first drain connection region (101) is connected to a drain mounting site on the product to be tested for mounting a MOS transistor;
the first grid connection region (102) is connected to a grid mounting position on the product to be tested for mounting an MOS tube.
3. The device for testing electrical stress of a PDFN packaged MOS transistor as claimed in claim 2, wherein the first drain connection region (101) is connected to a drain mounting site for mounting a MOS transistor on the product to be tested by soldering;
the first grid connection region (102) is connected to a grid mounting position for mounting an MOS tube on the product to be tested through soldering tin.
4. The device for testing the electrical stress of the PDFN package MOS transistor as recited in claim 1, wherein the second source connection region (203) is connected to a source mounting position for mounting a MOS transistor on the product to be tested by a wire.
5. The device for testing the electrical stress of the PDFN package MOS transistor as claimed in claim 1, wherein the drain of the MOS transistor is connected to the second drain connection region (201), the gate of the MOS transistor is connected to the second gate connection region (202), and the source of the MOS transistor is connected to the second source connection region (203).
6. The device for testing electrical stress of a PDFN packaged MOS transistor according to claim 1, wherein said first drain connection region (101) is connected to said second drain connection region (201) by at least two vias (30), and said first gate connection region (102) is connected to said second gate connection region (202) by at least two vias (30).
7. The device for testing electrical stress of a PDFN packaged MOS transistor according to claim 1, wherein the first drain connection region (101) and the first gate connection region (102) are copper layers;
the second drain connection region (201), the second gate connection region (202), and the second source connection region (203) are copper layers.
8. The device for testing electrical stress of a PDFN packaged MOS transistor according to claim 1, wherein said first drain connection region (101) is connected to said second drain connection region (201) through a copper via (30), and said first gate connection region (102) is connected to said second gate connection region (202) through a copper via (30).
9. The device of claim 1, wherein the MOS transistor is a high power MOS transistor of the PDFN package.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811187686.4A CN109541424B (en) | 2018-10-10 | 2018-10-10 | Device for testing electric stress of PDFN (polymer dispersed non-leaded semiconductor) packaged MOS (metal oxide semiconductor) tube and switching power supply |
| PCT/CN2019/080860 WO2020073625A1 (en) | 2018-10-10 | 2019-04-01 | Device for testing electrical stress of pdfn package mos transistor, and switching power supply |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811187686.4A CN109541424B (en) | 2018-10-10 | 2018-10-10 | Device for testing electric stress of PDFN (polymer dispersed non-leaded semiconductor) packaged MOS (metal oxide semiconductor) tube and switching power supply |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN109541424A CN109541424A (en) | 2019-03-29 |
| CN109541424B true CN109541424B (en) | 2020-02-21 |
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| CN201811187686.4A Active CN109541424B (en) | 2018-10-10 | 2018-10-10 | Device for testing electric stress of PDFN (polymer dispersed non-leaded semiconductor) packaged MOS (metal oxide semiconductor) tube and switching power supply |
Country Status (2)
| Country | Link |
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| CN (1) | CN109541424B (en) |
| WO (1) | WO2020073625A1 (en) |
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2018
- 2018-10-10 CN CN201811187686.4A patent/CN109541424B/en active Active
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2019
- 2019-04-01 WO PCT/CN2019/080860 patent/WO2020073625A1/en active Application Filing
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| CN2595067Y (en) * | 2002-12-27 | 2003-12-24 | 烟台东方电子信息产业股份有限公司 | Voltage limiting circuit of small-power switch power supply |
| CN101010804A (en) * | 2004-07-30 | 2007-08-01 | 先进微装置公司 | Technique for evaluating local electrical characteristics in semiconductor devices |
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| Publication number | Publication date |
|---|---|
| CN109541424A (en) | 2019-03-29 |
| WO2020073625A1 (en) | 2020-04-16 |
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