CN109521666B - Time-to-digital converter based on delay locked loop - Google Patents

Abstract

The invention relates to a time-to-digital converter based on a delay-locked loop, comprising: a delay-locked loop, which is used for receiving a reference clock signal, delaying the reference clock signal to generate a clock cluster signal with equal intervals and the same frequency, and outputting the reference clock signal and Equally spaced and co-frequency clock cluster signals; an integer time detection array, connected to the delay-locked loop, for receiving a reference clock signal, counting the reference clock signal, and outputting integer time data; a fractional time detection array, connected to the delay lock The phase loop is used to receive the equally-spaced co-frequency clock cluster signal, start signal and stop signal, quantify the start signal and stop signal based on the equal-spaced co-frequency clock cluster signal, and output fractional time data. The time-to-digital converter of the embodiment of the present invention improves the accuracy and stability of the measurement, improves the anti-interference ability of the TDC, simplifies the complexity of the decoding circuit, and reduces the power consumption area of the TDC.

Description

A Time-to-Digital Converter Based on Delay-Locked Loop

technical field

The invention belongs to the technical field of laser radar optical signal receiver systems, in particular to a time-to-digital converter based on a delay phase locked loop.

Background technique

In 1960, the world's first laser came out, and in 1961 the laser was first used in the ranging system. Due to a series of excellent optical properties of lasers such as high collimation, high monochromaticity, high power density and high coherence, various ranging technologies for different scenarios and different ranges are constantly being introduced. From as small as the micron-scale range close to the laser wavelength, centimeter-scale object shapes and target object distances from several kilometers to tens of kilometers, as large as the distance between the earth and satellites and even the moon, lasers can be used to accurately measure. And with the development of science and technology, the application scope of lidar is more and more extensive, such as navigation and collision avoidance of automobiles or spacecraft, three-dimensional space overview scanning, meteorological detection, geological detection and so on. According to the current public reports, major research institutions of driverless cars such as Google, Ford, Baidu, etc. all use scanning lidar to collect data; when the car is driving at high speed, the distance and relative distance between the two vehicles are scanned in real time through lidar. The speed provides obstacle information for the driving system, which can reduce the probability of accidents.

The laser radar uses the laser transmitter to emit laser light on the object to be detected, and the laser echo reflected by the target object is received by the avalanche photodiode operating in linear mode and converted into a current signal, and then the front-end analog receiver converts the avalanche photoelectric The pulse current generated by the diode is linearly converted into a voltage signal, and then the time-of-flight information of the pulse is obtained by a time-to-digital conversion circuit. The time-of-flight information of the pulse essentially expresses the actual distance between the detected object and the lidar. Therefore, the performance of the time-to-digital converter directly determines the accuracy of lidar ranging.

The current pulse wave lidar has been developed from the initial single-channel detection (see Figure 1) to multi-line scanning detection, and even large area array detection, which makes the time-to-digital conversion circuit also need to be area array, if using traditional The traditional time-to-digital conversion method is not only less accurate, but also has high power consumption for large-area integration, which is far from meeting the practical application of vehicle-mounted lidar.

SUMMARY OF THE INVENTION

In order to solve the above problems in the prior art, the present invention provides a time-to-digital converter based on a delay-locked loop. The technical problem to be solved by the present invention is realized by the following technical solutions:

An embodiment of the present invention provides a time-to-digital converter based on a delay-locked loop, comprising:

a delay-locked loop for receiving a reference clock signal, delaying the reference clock signal to generate an equally spaced co-frequency clock cluster signal, and outputting the reference clock signal and the equally spaced co-frequency clock cluster signal;

an integer time detection array, connected to the delay-locked loop, for receiving the reference clock signal, counting the reference clock signal, and outputting integer time data;

The fractional time detection array is connected to the delay-locked loop, and is used to receive the equally spaced co-frequency clock cluster signal, start signal and stop signal, and use the equally spaced co-frequency clock cluster signal as a reference to compare the start signal and the stop signal. The stop signal is quantized to output fractional time data.

In an embodiment of the present invention, it also includes:

a decoder, connected to the integer-time detection array and the fractional-time detection array, for decoding the address signal and outputting an address code;

an integrated compensation processing module, connected to the decoder, the integer time detection array and the fractional time detection array, for performing integration compensation processing on the integer time data and the fractional time data, and according to the address The code output integrates the compensation data.

In one embodiment of the present invention, the integer time detection array includes a counter and a register, wherein,

the counter is configured to count the reference clock signal when the start signal is received; and output the integer time data when the stop signal is received;

The register, connected to the counter, is used for buffering the integer time data.

In an embodiment of the present invention, the register is further connected to the decoder and the integrated compensation processing module, for outputting the integer time data to the integrated compensation processing module according to the address code.

In one embodiment of the present invention, the fractional time detection array includes a start fraction measurement array and a stop fraction measurement array, wherein,

The start fraction measurement array is connected to the delay-locked loop and the integrated compensation processing module, and is used to quantify the start signal based on the equal-spaced co-frequency clock cluster signal, and output the first fractional time data;

The stop fraction measurement array is connected to the delay-locked loop and the integrated compensation processing module, and is used for quantizing the stop signal based on the equally spaced co-frequency clock cluster signal, and outputting second fractional time data.

In an embodiment of the present invention, the stop fraction measurement array is further connected to the decoder, for outputting the second fractional time data to the integrated compensation processing module according to the address code.

In an embodiment of the present invention, the decoder is configured to decode the address signal when receiving the stop signal quantization completion signal.

Another embodiment of the present invention provides a time-to-digital conversion method based on a delay-locked loop, comprising the steps of:

receiving a reference clock signal, delaying the reference clock signal to generate an equally spaced co-frequency clock cluster signal, and outputting the reference clock signal and the equally spaced co-frequency clock cluster signal;

Counting the reference clock signal and outputting integer time data;

Receive the start signal and the stop signal, and quantify the start signal and the stop signal on the basis of the same-frequency clock cluster signal at the same interval, and output fractional time data;

When receiving the stop signal quantization completion signal, the address signal is decoded, and the address code is output;

Perform integrated compensation processing on the integer time data and the fractional time data, and output integrated compensation data according to the address code.

In an embodiment of the present invention, the reference clock signal is counted to output integer time data, including:

When the start signal is received, the reference clock signal is counted; and when the stop signal is received, the integer time data is output according to the address code.

In an embodiment of the present invention, the start signal and the stop signal are quantized based on the equal-spaced co-frequency clock cluster signals, and fractional time data is output, including:

The start signal is quantized based on the same-frequency clock cluster signal at the same interval, and the first fractional time data is output;

The stop signal is quantized based on the clock cluster signal at the same interval and the same frequency, and the second fractional time data is output according to the address code.

Compared with the prior art, the beneficial effects of the present invention:

1. The present invention uses an integer time detection array and a fractional time detection array to perform multi-channel measurement on the multi-phase clock generated by the Delay-Locked Loop (DLL), which greatly improves the accuracy and stability of the measurement. , the anti-interference ability of the time-to-digital converter (TDC) is improved, and the measurement output of the integer time detection array and fractional time detection array is one-hot code, which simplifies the complexity of the decoding circuit and reduces the overall TDC. The power consumption area has broad application prospects in the field of area array detection lidar.

2. The delay-locked loop of the present invention has the advantages of low jitter, low phase noise and feedback stability, which makes it have good robustness, so that a stable delay can be generated, which solves the problems in TDC due to the manufacturing process, power supply voltage and environment. The problem of clock delay variation caused by temperature changes; and the DLL is optimized for delay, load matching and area power consumption, which can provide a stable multi-phase clock signal with a small area power consumption.

Description of drawings

1 is a schematic diagram of a waveform of a single-channel detection digital clock converter provided by the prior art;

2 is a schematic block diagram of a digital-to-time converter based on a delay-locked loop provided by an embodiment of the present invention;

3 is a schematic diagram of a module of a delay-locked loop provided by an embodiment of the present invention;

FIG. 4 is a schematic structural diagram of a digital-to-time converter based on a delay-locked loop provided by an embodiment of the present invention.

Detailed ways

The present invention will be described in further detail below with reference to specific embodiments, but the embodiments of the present invention are not limited thereto.

Example 1

Referring to FIG. 2, FIG. 2 is a schematic block diagram of a digital-to-time converter based on a delay-locked loop provided by an embodiment of the present invention, including: a delay-locked loop 100 and a TDC measurement part, wherein,

The delay-locked loop 100 receives the reference clock signal, delays the reference clock signal to generate an equally spaced co-frequency clock cluster signal, and outputs the reference clock signal and the equally spaced co-frequency clock cluster signal;

Further, please refer to FIG. 3 , which is a schematic block diagram of a delay-locked loop provided by an embodiment of the present invention. The delay-locked loop 100 is composed of a phase detector 101 , a charge pump 102 , a filter 103 and a delay chain 104 The phase detector 100 receives the reference clock signal and the delayed clock signal (for example, the delayed clock signal is delayed by one clock cycle), compares the phases of the reference clock signal and the delayed clock signal, and outputs a phase difference between the two input signals proportional to the pulse signal; the charge pump 102 is a voltage controllable charge pump, the charge pump 102 receives the above-mentioned pulse signal, and determines whether to pump the charge into the filter 103 or the charge from the filter 103 according to the pulse signal generated by the phase detector 101 The filter 103 receives the voltage signal, processes the voltage signal according to the loop requirements, generates a loop control signal to control the delay chain 104, and determines the delay period of the delay chain 104 until the output Stable control signal; when the control signal of the filter 103 is stable, the delay chain 104 receives the stable control signal, delays the reference clock signal according to the control signal, outputs the reference clock signal to the integer time detection array, and outputs a set of etc. The interval co-frequency clock signal is to the fractional time detection array, and the last delay clock signal in the equally-spaced co-frequency clock signal is output to the phase detector 101 for comparison with the reference clock signal; when the control signal of the filter 103 is unstable, At this time, the delay chain 104 outputs the unequally spaced co-frequency clock signal, and the unequally spaced co-frequency clock signal returns to the phase detector 101 for re-delaying.

Further, the reference clock signal is one signal, and the equally spaced co-frequency clock cluster signals are a group of multi-phase clock signals based on the reference clock signal and sequentially delayed by the same clock period, and the frequency of the group of multi-phase clock signals is the same, This group of multi-phase clock signals includes at least two equally spaced and same-frequency clock signals; for example, if the first delayed clock signal is separated from the reference clock signal by 312ps, the second delayed clock signal is separated from the first delayed clock signal by 312ps. Also 312ps, the interval between the third delayed clock signal and the second delayed clock signal is also 312ps, and so on.

Further, the frequency of the equally spaced and same frequency clock cluster signal is the same as the frequency of the reference clock signal.

The delay-locked loop of the embodiment of the present invention has the advantages of low jitter, low phase noise, feedback stability, etc., so that it has good robustness, so that a stable delay can be generated, which solves the problem in TDC due to the manufacturing process, power supply voltage and environment. The problem of clock delay variation caused by temperature change; and, the DLL consists of a phase detector, charge pump, filter and controllable delay chain, these modules are optimized for delay, load matching and area power consumption, and can be used in a small area Power consumption provides a stable multiphase clock signal.

The TDC measurement part is used to measure the laser time of flight (TOF), and is composed of an integer time detection array 200 and a fractional time detection array 300. The integer time detection array 200 is connected to the delay-locked loop 100 for receiving the reference clock signal, and for the reference clock The signal is counted, and the integer time data is output, and the output integer time data is multi-bit data, including at least two data; the fractional time detection array 300 is connected to the delay-locked loop 100, and is used for receiving equally-spaced co-frequency clock cluster signals and start signals and the stop signal, the start signal and the stop signal are quantized by using the same-frequency clock cluster signal at equal intervals, and fractional time data is output.

Further, the integer time detection array 200 includes several integer time detection points, the fractional time detection array 300 includes several fractional time detection points, and the integer time detection array 200 and the fractional time detection array 300 are respectively connected with the photoelectric conversion in the lidar receiver Arrays of cells (avalanche diodes, APDs) correspond one-to-one.

Further, the fractional time detection array 300 is composed of an edge detection circuit and a decoding circuit of the multi-phase clock sampling signal (ie, the equally spaced and co-frequency clock cluster signal in the embodiment of the present invention).

The embodiment of the present invention adopts the integer time detection array and the fractional time detection array to perform multi-channel measurement on the multi-phase clock generated by the DLL, which greatly improves the accuracy and stability of the measurement and improves the resistance of the time-to-digital converter (TDC). Interference ability, and the measurement output of the integer time detection array and fractional time detection array is one-hot code, which simplifies the complexity of the decoding circuit and reduces the power consumption area of the overall TDC. The application prospect is broad.

Please refer to FIG. 4. FIG. 4 is a schematic structural diagram of a digital-to-time converter based on a delay-locked loop provided by an embodiment of the present invention, wherein a “/” on a signal line indicates that the signal is multi-bit data, and a signal line on the signal line The absence of "/" indicates that the signal is one-bit data; the digital clock converter includes a delay-locked loop 100 , an integer-time detection array 200 and a fractional-time detection array 300 .

Further, the integer time detection array 200 includes a counter 201 and a register 202,

The counter 201 receives the start signal, the stop signal and the reference clock signal. When the counter 201 receives the start signal, the counter 201 starts to count the reference clock signal; when the counter 201 receives the stop signal, the counter 201 stops counting the reference clock signal, and output the integer time data obtained by counting to the register 202; specifically, since the stop signal is a group of data, and the counter can only store one data, when the counter receives the first stop signal, it records the current reference clock The count of the signal obtains the first integer time data, and outputs the first integer time data to the register; when the counter receives the intermediate stop signal, the count of the current reference clock signal is recorded to obtain the first integer time data, and This first integer time data is output to the register; when the counter receives the last stop signal, the counter stops counting the reference clock and outputs the last integer time data to the register.

In one embodiment of the present invention, since the DLL receives the reference clock signal and outputs the above-mentioned reference clock signal and the clock cluster signal of the same frequency at equal intervals, the counter can receive the reference clock signal provided by the DLL, and can also directly receive the reference clock signal provided by the DLL. The reference clock signal through the DLL.

The register 202 is connected to the register 201 for receiving integer time data and buffering the integer time data in the register 202 .

In the embodiment of the present invention, the integer time detection array adopts counter multiplexing, which can not only improve the accuracy of measurement, but also improve the efficiency of measurement; the use of registers to cache integer time data can facilitate the system to read and clear data.

Further, the fractional time detection array 300 includes a start fractional time detection array 301 and a stop fractional time detection array 302, wherein,

The Start fractional time detection array 301 is connected to the delay-locked loop and the integrated compensation processing module, and is used for receiving the start signal and the equally spaced co-frequency clock cluster signal; when receiving the start signal, the Start fractional time detection array 301 uses the equally spaced co-frequency clocks The cluster signal is used as a reference to determine the relative position of the start signal and the cluster signal of the same frequency clock at equal intervals, so as to quantify the start signal, and quantify to obtain the first fractional time data, the Start fractional time detection array 301 outputs the first fractional time data, the first fractional time data is Fractional time data is multi-bit data, including at least two data.

The stop fractional time detection array 302 is connected to the delay-locked loop and the integrated compensation processing module, and is used for receiving the stop signal with the same frequency clock cluster signal at equal intervals; when receiving the stop signal, the stop fractional time detection array 302 has the same frequency at equal intervals The clock cluster signal is used as a reference to determine the relative position of the stop signal and the clock cluster of the same frequency at equal intervals, so as to quantify the stop signal, and quantify to obtain second fractional time data. The Stop fractional time detection array 302 outputs the second fractional time data, and the second Fractional time data is multi-bit data, including at least two data.

In a specific embodiment, when the system controls the laser transmitter to emit laser light, the start signal will be triggered, and the start signal will start the counter in the TDC and the Start fractional time detection array to start timing; when the laser is reflected back by the target, it will pass through the photoelectric conversion module to generate the stop signal. , the stop signal on the one hand makes the counter stop counting, and on the other hand reaches the Stop fractional time detection array for quantization. After the quantization is completed, the TDC stops timing and outputs the quantized value of the time interval between the start signal and the stop signal.

In a specific embodiment, the start signals that trigger the start of timing of all TDC channels are unified, therefore, the start signals input to the counter 201 and the start score measurement array 301 are the same signal; and each channel in the TDC has its own corresponding Each stop signal corresponds to the laser signal reflected back from different positions of the target. Therefore, the signals input to the register 202 and the stop fraction measurement array 302 are a group of stop signals.

In a specific embodiment, a reset needs to be performed before each measurement of the TDC to clear the previously retained measurement value, and the measurement value will be kept until reset after each measurement.

In a specific embodiment, the TDC array adopts the integer timing multiplexing method and the fractional timing one-hot code output method, which simplifies the complexity of the decoding circuit and reduces the consumption of area and power consumption, and is especially suitable for area array detection. Lidar applications.

Referring to FIG. 4 , the digital-to-time converter of the embodiment of the present invention further includes: a decoder 400 and an integrated compensation processing module 500, wherein:

The decoder 400 is used to receive the address signal, decode the address signal, and output the address code, the address code is in the form of one-hot code, and the function of the address code is to measure the register 202, the stop score measurement array 302 and the integer compensation processing module 500. The data in the address is located;

Specifically, the decoder is configured to decode the address signal and output the address code when receiving the stop signal quantization completion signal.

Specifically, after the stop signal quantization is completed, the system control unit receives the stop signal quantization completion signal, and sends the stop signal quantization completion signal to the decoder, and the decoder decodes and outputs the address code after receiving the signal; In another embodiment of the invention, after the stop signal quantization is completed, the stop score measurement array sends the stop signal quantization completion signal to the decoder, and the decoder decodes and outputs the address code after receiving the signal.

Further, the register 202 is also connected to the decoder and the integrated compensation processing module. When receiving the address code, the register 202 outputs the integer time data to the integrated compensation processing module 500 according to the addressing location of the address code.

Further, the stop score measurement array 302 is also connected to the decoder and the integrated compensation processing module. When receiving the address code, the stop score measurement array 302 reads and outputs the second measurement data to the integrated compensation process according to the addressing and positioning of the address code. Module 500.

In a specific embodiment, the TDC array is read by means of address decoding, and the system can change the address line interface to read the measurement value in each array channel, and each channel is independent and has high flexibility.

The integrated compensation processing module 500 is connected to the decoder, the register 202 and the stop fractional measurement array 302 for receiving integer time data, fractional time data (including the first fractional time data and the second fractional time data) and address codes, for integer time The data and fractional time data are integrated and compensated, and the integrated compensation data is output to the post-stage equipment according to the addressing and positioning of the address code.

The embodiment of the present invention adopts the integer time detection array and the fractional time detection array to perform multi-channel measurement on the multi-phase clock generated by the DLL, which greatly improves the accuracy and stability of the measurement, improves the anti-interference ability of the TDC, and the integer time detection The measurement output of the array and fractional time detection array is one-hot code, which simplifies the complexity of the decoding circuit and reduces the power consumption area of the overall TDC. It has broad application prospects in the field of area-array detection lidar.

The delay-locked loop of the embodiment of the present invention has the advantages of low jitter, low phase noise, feedback stability, etc., so that it has good robustness, so that a stable delay can be generated, which solves the problem in TDC due to the manufacturing process, power supply voltage and environment. The problem of clock delay variation caused by temperature changes; and, through delay, load matching and area power optimization, the DLL can provide stable multi-phase clock signals with a small area power consumption.

The embodiment of the present invention also provides a time-to-digital conversion method based on a delay-locked loop, comprising the steps of:

receiving a reference clock signal, delaying the reference clock signal to generate an equally spaced co-frequency clock cluster signal, and outputting the reference clock signal and the equally spaced co-frequency clock cluster signal;

Counting the reference clock signal and outputting integer time data;

Receive the start signal and the stop signal, and quantify the start signal and the stop signal on the basis of the same-frequency clock cluster signal at the same interval, and output fractional time data;

When receiving the stop signal quantization completion signal, the address signal is decoded, and the address code is output;

Perform integrated compensation processing on the integer time data and the fractional time data, and output integrated compensation data according to the address code.

Specifically, counting the reference clock signal, and outputting integer time data, including:

When receiving the start signal, count the reference clock signal; and when receiving the stop signal, record the current count of the reference clock signal, and stop when all the stop signals are received Counting the reference clock signal, and outputting the integer time data;

The integer time data is output according to the address code.

Specifically, the start signal and the stop signal are quantized on the basis of the equal-interval same-frequency clock cluster signal, and the fractional time data is output, including:

The start signal is quantized based on the same-frequency clock cluster signal at the same interval, and the first fractional time data is output;

The stop signal is quantized based on the clock cluster signal at the same interval and the same frequency, and the second fractional time data is output according to the address code.

The above content is a further detailed description of the present invention in combination with specific preferred embodiments, and it cannot be considered that the specific implementation of the present invention is limited to these descriptions. For those of ordinary skill in the technical field of the present invention, without departing from the concept of the present invention, some simple deductions or substitutions can be made, which should be regarded as belonging to the protection scope of the present invention.

Claims (10)

1. a time-to-digital converter based on a delay-locked loop, is characterized in that, comprises: a delay-locked loop for receiving a reference clock signal, delaying the reference clock signal to generate an equally spaced co-frequency clock cluster signal, and outputting the reference clock signal and the equally spaced co-frequency clock cluster signal; An integer time detection array, connected to the delay-locked loop, includes a plurality of integer time detection points, used for receiving the reference clock signal, the start signal and the stop signal, counting the reference clock signal, and outputting integer time data, The integer time data is multi-bit data; A fractional time detection array, connected to the delay-locked loop, includes a plurality of fractional time detection points for receiving the equally spaced co-frequency clock cluster signals, the start signal and the stop signal, and using the equally spaced co-frequency clock cluster signals The start signal and the stop signal are quantized as a reference, and fractional time data is output, and the fractional time data is multi-bit data. 2. the time-to-digital converter based on delay locked loop as claimed in claim 1, is characterized in that, also comprises: a decoder, connected to the integer-time detection array and the fractional-time detection array, for decoding the address signal and outputting an address code; an integrated compensation processing module, connected to the decoder, the integer time detection array and the fractional time detection array, for performing integration compensation processing on the integer time data and the fractional time data, and according to the address The code output integrates the compensation data. 3. The delay-locked loop-based time-to-digital converter of claim 2, wherein the integer time detection array comprises a counter and a register, wherein, the counter is configured to count the reference clock signal when the start signal is received; and output the integer time data when the stop signal is received; The register, connected to the counter, is used for buffering the integer time data. 4. The time-to-digital converter based on a delay-locked loop as claimed in claim 3, wherein the register is also connected to the decoder and the integrated compensation processing module, for outputting according to the address code the integer time data to the integrated compensation processing module. 5. The delay-locked loop-based time-to-digital converter of claim 2, wherein the fractional time detection array comprises a start fractional measurement array and a stop fractional measurement array, wherein, The start fraction measurement array is connected to the delay-locked loop and the integrated compensation processing module, and is used to quantify the start signal based on the equal-spaced co-frequency clock cluster signal, and output the first fractional time data; The stop fraction measurement array is connected to the delay-locked loop and the integrated compensation processing module, and is used for quantizing the stop signal based on the equally spaced co-frequency clock cluster signal, and outputting second fractional time data. 6. The time-to-digital converter based on a delay-locked loop as claimed in claim 5, wherein the stop fraction measurement array is further connected to the decoder for outputting the second signal according to the address code Fractional time data to the integrated compensation processing module. 7. The time-to-digital converter based on a delay-locked loop as claimed in claim 6, wherein the decoder is configured to decode the address signal when receiving the stop signal quantization completion signal . 8. a time-to-digital conversion method based on a delay-locked loop, is characterized in that, comprises the steps: receiving a reference clock signal, delaying the reference clock signal to generate an equally spaced co-frequency clock cluster signal, and outputting the reference clock signal and the equally spaced co-frequency clock cluster signal; Counting the reference clock signal, and outputting integer time data, where the integer time data is multi-bit data; Receive the start signal and the stop signal, quantify the start signal and the stop signal on the basis of the same-frequency clock cluster signal at the same interval, and output fractional time data, and the fractional time data is multi-bit data; When receiving the stop signal quantization completion signal, the address signal is decoded, and the address code is output; Perform integrated compensation processing on the integer time data and the fractional time data, and output integrated compensation data according to the address code. 9. The time-to-digital conversion method based on a delay-locked loop as claimed in claim 8, wherein counting the reference clock signal and outputting integer time data, comprising: When the start signal is received, the reference clock signal is counted; and when the stop signal is received, the integer time data is output according to the address code. 10. The time-to-digital conversion method based on a delay-locked loop as claimed in claim 8, wherein the start signal and the stop signal are quantized on the basis of the equidistant co-frequency clock cluster signal, and output Fractional time data, including: The start signal is quantized based on the same-frequency clock cluster signal at the same interval, and the first fractional time data is output; The stop signal is quantized on the basis of the clock cluster signal at the same interval and the same frequency, and the second fractional time data is output according to the address code.

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