CN109510515A - A kind of timesharing starting module - Google Patents
A kind of timesharing starting module Download PDFInfo
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- CN109510515A CN109510515A CN201910075763.5A CN201910075763A CN109510515A CN 109510515 A CN109510515 A CN 109510515A CN 201910075763 A CN201910075763 A CN 201910075763A CN 109510515 A CN109510515 A CN 109510515A
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-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02P—CONTROL OR REGULATION OF ELECTRIC MOTORS, ELECTRIC GENERATORS OR DYNAMO-ELECTRIC CONVERTERS; CONTROLLING TRANSFORMERS, REACTORS OR CHOKE COILS
- H02P1/00—Arrangements for starting electric motors or dynamo-electric converters
- H02P1/16—Arrangements for starting electric motors or dynamo-electric converters for starting dynamo-electric motors or dynamo-electric converters
- H02P1/54—Arrangements for starting electric motors or dynamo-electric converters for starting dynamo-electric motors or dynamo-electric converters for starting two or more dynamo-electric motors
- H02P1/58—Arrangements for starting electric motors or dynamo-electric converters for starting dynamo-electric motors or dynamo-electric converters for starting two or more dynamo-electric motors sequentially
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of DC power input into DC power output
- H02M3/02—Conversion of DC power input into DC power output without intermediate conversion into AC
- H02M3/04—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of AC power input into DC power output; Conversion of DC power input into AC power output
- H02M7/02—Conversion of AC power input into DC power output without possibility of reversal
- H02M7/04—Conversion of AC power input into DC power output without possibility of reversal by static converters
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02P—CONTROL OR REGULATION OF ELECTRIC MOTORS, ELECTRIC GENERATORS OR DYNAMO-ELECTRIC CONVERTERS; CONTROLLING TRANSFORMERS, REACTORS OR CHOKE COILS
- H02P5/00—Arrangements specially adapted for regulating or controlling the speed or torque of two or more electric motors
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Electronic Switches (AREA)
Abstract
本发明提供了分时启动模块，涉及负载驱动技术领域。该分时启动模块包括启动电路、延时电路以及多个驱动电路，延时电路与启动电路及多个驱动电路电连接，启动电路用于生成时钟信号及复位信号，并将时钟信号及复位信号传输至延时电路，延时电路用于接收到时钟信号及复位信号后，按照预设定的时间间隔依次生成多个启动信号，延时电路还用于将多个启动信号分别传输至与每个启动信号对应的驱动电路，多个驱动电路用于响应对应的启动信号而导通，以使与多个驱动电路分别电连接的多个负载按照预设定的时间间隔依次启动；由于在未采用单片机的情况下实现了负载的延时启动，从而降低了制造分时启动模块的成本，更加贴合于实际应用。
The invention provides a time-sharing starting module, which relates to the technical field of load driving. The time-sharing start-up module includes a start-up circuit, a delay circuit and a plurality of drive circuits. The delay circuit is electrically connected to the start-up circuit and the plurality of drive circuits. The start-up circuit is used to generate a clock signal and a reset signal, and to convert the clock signal and the reset signal Transmission to the delay circuit, the delay circuit is used to generate a plurality of start-up signals in sequence according to a preset time interval after receiving the clock signal and the reset signal, and the delay circuit is also used to transmit the plurality of start-up signals to and from each A plurality of drive circuits corresponding to the start-up signals, and the plurality of drive circuits are used to turn on in response to the corresponding start-up signals, so that the plurality of loads electrically connected to the plurality of drive circuits are turned on in sequence according to the preset time interval; In the case of using the single chip microcomputer, the delayed start of the load is realized, thereby reducing the cost of manufacturing the time-sharing start-up module, which is more suitable for practical applications.
Description
Technical field
The present invention relates to load actuation techniques fields, in particular to a kind of timesharing starting module.
Background technique
The heavy-load high-powers equipment starting such as blower, pump class at present, is broadly divided into and directly initiates and other reduction starting currents
Starting mode, but in some cases, the starting of multiple power equipments can start at times, in this way can be to avoid
Impact of the starting to power grid simultaneously, can also be to avoid the normal work for influencing other equipment when starting simultaneously.
But in the prior art, multicircuit time starting module can start one group of power equipment at times, and guarantee have
Identical starting interval, but single-chip microcontroller control is mostly used greatly, realize the soft start of power equipment；However it places an order in forceful electric power magnetic environment
Piece machine is easier to be interfered, and may result in starting failure, while using the higher cost of single-chip microcontroller, causing entirely to start
The cost of module is high, uneconomical.
Summary of the invention
The purpose of the present invention is to provide a kind of timesharing starting modules, to solve the above problems.
The present invention provides a kind of timesharing starting module, the timesharing starting module include start-up circuit, delay circuit with
And multiple driving circuits, the delay circuit are electrically connected with the start-up circuit and multiple driving circuits；
The start-up circuit is for generating clock signal and reset signal, and by the clock signal and the reset signal
It is transmitted to the delay circuit；
After the delay circuit is used to receive the clock signal and the reset signal, according between the presetting time
Every sequentially generating multiple enabling signals, the multiple enabling signal and the multiple driving circuit are corresponded；
The delay circuit is also used to for the multiple enabling signal being transmitted separately to corresponding with each enabling signal
The driving circuit；
The multiple driving circuit is for responding the corresponding enabling signal and being connected, so that with the multiple driving electricity
Multiple loads that road is electrically connected successively start according to presetting time interval.
Further, the delay circuit includes frequency unit and shift unit, the start-up circuit and the frequency dividing
Unit and shift unit electrical connection, the frequency unit is electrically connected with the shift unit, the shift unit with it is multiple
The driving circuit electrical connection；
The frequency unit is latched for after receiving the clock signal, generating data input clock signal and output
Clock signal, and the data input clock signal and the output latching clock signal are transmitted to the shift unit；
Wherein, the data input clock signal is identical as the output period of latching clock signal and level is opposite；
The shift unit is for after receiving the reset signal, according to the data input clock signal and described
Output latching clock signal sequentially generates the multiple enabling signal.
Further, the frequency unit includes frequency divider, timing resistor, timing capacitor, first switch tube, second switch
Pipe, first resistor, second resistance, 3rd resistor, the 4th resistance, the first signal output end and second signal output end, it is described
First pin of frequency divider is electrically connected with the timing resistor, and the second pin of the frequency divider is electrically connected with the timing capacitor
It connects, the timing resistor is electrically connected with the timing capacitor, the base of the output pin of the frequency divider and the first switch tube
Pole is electrically connected, and is electrically connected after the collector series connection first resistor of the first switch tube with power circuit, described first opens
The emitter ground connection of pipe is closed, the second switch is in parallel with the first switch tube, and the base stage of the second switch is successively
The 3rd resistor, the second resistance of connecting are electrically connected with the power circuit later, the collector of the second switch
It connects and is electrically connected with power circuit after the 4th resistance, the emitter ground connection of the second switch, first signal is defeated
Outlet is electrically connected between the collector of the first switch tube and the first resistor, and with the second resistance and described the
The tie points of three resistance is electrically connected, and the second signal output end is electrically connected to the collector and described the of the second switch
Between four resistance；
First signal output end is for exporting the data input clock signal；
The second signal output end is for exporting the output latching clock signal.
Further, after the frequency unit is used to receive the reset signal, by the output latching clock signal
It resets.
Further, the frequency unit further include first capacitor, first diode, the second diode, third switching tube,
5th resistance and the 6th resistance, the start-up circuit are connected and are opened after the first capacitor, the 5th resistance with the third
The base stage electrical connection of pipe is closed, the first diode and the 5th resistance reverse parallel connection, the base stage of the third switching tube are anti-
It is grounded after to second diode of connecting, the emitter ground connection of the third switching tube, the collector of the third switching tube
It connects and is electrically connected with the power circuit after the 6th resistance, the second signal output end is also electrically coupled to the third and opens
Between the collector and the 6th resistance for closing pipe.
Further, the shift unit includes shift register and multiple signal output units, the multiple signal
Output unit and the multiple driving circuit correspond, the data input clock pin of the shift register and described first
Signal output end electrical connection, the output latch clock pin of the shift register are electrically connected with the second signal output end,
The reset pin of the shift register is electrically connected with a signal output unit in the multiple signal output unit, described
Multiple data output pins of shift register are electrically connected with a signal output unit respectively.
Further, the start-up circuit includes the first power supply signal incoming end, rectifier bridge, optocoupler, the 7th resistance, the 8th
Resistance, third diode, the 4th switching tube, clock signal output terminal and reset signal output end, first power supply signal
Incoming end is sequentially connected in series the rectifier bridge and the optocoupler, the three or two pole described in the first output end differential concatenation of the optocoupler
It is electrically connected after pipe, the 8th resistance with the power circuit, the first output end of the optocoupler is connected after the 7th resistance
It is electrically connected with the base stage of the 4th switching tube, the emitter of the 4th switching tube is electrically connected with the power circuit, described
The grounded collector of the second output terminal of optocoupler and the 4th switching tube, the of the clock signal output terminal and the optocoupler
The electrical connection of one output end, the reset signal output end are electrically connected with the collector of the 4th switching tube；
The clock signal output terminal is for exporting the clock signal；
The reset signal output end is for exporting the reset signal.
Further, each driving circuit includes the 5th switching tube, relay, the second capacitor, third capacitor,
The base stage of nine resistance, the tenth resistance and the 4th diode, the 5th switching tube is electrically connected with the shift register, described
The emitter of 5th switching tube is grounded, the collector of the 5th switching tube connect after the 9th resistance, the relay with
Power circuit electrical connection, the second capacitor forward direction connect after the 4th diode with the 9th resistance and it is described after
Electric appliance is in parallel, the contact shunt that the third capacitor is connected after the tenth resistance with the relay.
Further, the timesharing starting module further includes power circuit, the power circuit and the start-up circuit, institute
It states delay circuit and multiple driving circuits is electrically connected.
Further, the power circuit includes second source signal incoming end, first voltage converting unit and second
Voltage conversion unit, the second source signal incoming end, the first voltage converting unit and second voltage conversion
Unit is sequentially connected electrically；
The first voltage converting unit is for being converted to the supply voltage that the second source signal incoming end accesses
First DC voltage；
The second voltage converting unit is used to first DC voltage being converted to the second DC voltage.
Compared with the prior art, the invention has the following advantages: a kind of timesharing starting module provided by the invention, including
Start-up circuit, delay circuit and multiple driving circuits, delay circuit are electrically connected with start-up circuit and multiple driving circuits, starting
Clock signal and reset signal are transmitted to delay circuit, delay circuit for generating clock signal and reset signal by circuit
After receiving clock signal and reset signal, multiple enabling signals are sequentially generated according to presetting time interval, it is multiple
Enabling signal and multiple driving circuits correspond, and delay circuit is also used to be transmitted separately to multiple enabling signals and each open
The dynamic corresponding driving circuit of signal, multiple driving circuits are for responding corresponding enabling signal and being connected, so that with multiple drivings
Multiple loads that circuit is electrically connected successively start according to presetting time interval；Due to the case where not using single-chip microcontroller
Under realize the delayed startup of load, thus reduce manufacture timesharing starting module cost, more fit in practical application.
To enable the above objects, features and advantages of the present invention to be clearer and more comprehensible, preferred embodiment is cited below particularly, and cooperate
Appended attached drawing, is described in detail below.
Detailed description of the invention
In order to make the object, technical scheme and advantages of the embodiment of the invention clearer, below in conjunction with the embodiment of the present invention
In attached drawing, technical scheme in the embodiment of the invention is clearly and completely described, it is clear that described embodiment is
A part of the embodiment of the present invention, instead of all the embodiments.The present invention being usually described and illustrated herein in the accompanying drawings is implemented
The component of example can be arranged and be designed with a variety of different configurations.
Therefore, the detailed description of the embodiment of the present invention provided in the accompanying drawings is not intended to limit below claimed
The scope of the present invention, but be merely representative of selected embodiment of the invention.Based on the embodiments of the present invention, this field is common
Technical staff's every other embodiment obtained without creative efforts belongs to the model that the present invention protects
It encloses.
Fig. 1 is the circuit structure block diagram of timesharing starting module provided by the present invention.
Fig. 2 is the circuit diagram of power circuit provided by the invention.
Fig. 3 is the circuit diagram of start-up circuit provided by the invention.
Fig. 4 is the further circuit structure block diagram of timesharing starting module provided by the invention.
Fig. 5 is the circuit diagram of frequency unit provided by the invention.
Fig. 6 is the circuit diagram of shift unit provided by the invention.
Fig. 7 is the circuit diagram of driving circuit provided by the invention.
Icon: 100- timesharing starting module；110- power circuit；120- start-up circuit；130- delay circuit；132- frequency dividing
Unit；134- shift unit；140- driving circuit.
Specific embodiment
Below in conjunction with attached drawing in the embodiment of the present invention, technical solution in the embodiment of the present invention carries out clear, complete
Ground description, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.Usually exist
The component of the embodiment of the present invention described and illustrated in attached drawing can be arranged and be designed with a variety of different configurations herein.
Therefore, the detailed description of the embodiment of the present invention provided in the accompanying drawings is not intended to limit below claimed
The scope of the present invention, but be merely representative of selected embodiment of the invention.Based on the embodiment of the present invention, those skilled in the art
Member's every other embodiment obtained without making creative work, shall fall within the protection scope of the present invention.
It should be noted that similar label and letter indicate similar terms in following attached drawing, therefore, once a certain Xiang Yi
It is defined in a attached drawing, does not then need that it is further defined and explained in subsequent attached drawing.Meanwhile of the invention
In description, term " first ", " second " etc. are only used for distinguishing description, are not understood to indicate or imply relative importance.
The present invention provides a kind of timesharing starting modules 100, start multiple loads for timesharing.Referring to Fig. 1, being this hair
The circuit structure block diagram of the timesharing starting module 100 of bright offer.The timesharing starting module 100 includes: power circuit 110, starting
Circuit 120, delay circuit 130 and multiple driving circuits 140, power circuit 110 and start-up circuit 120, delay circuit 130 with
And multiple driving circuits 140 are electrically connected, delay circuit 130 is electrically connected with start-up circuit 120 and multiple driving circuits 140.
Wherein, power circuit 110 is used to provide for start-up circuit 120, delay circuit 130 and multiple driving circuits 140
Voltage.Specifically, power circuit 110 includes second source signal incoming end J2, first voltage converting unit and second voltage
Converting unit, second source signal incoming end J2, first voltage converting unit and second voltage converting unit are sequentially connected electrically.
First voltage converting unit is used to being converted to the second source signal incoming end J2 supply voltage accessed into first straight
Galvanic electricity pressure；Second voltage converting unit is used to the first DC voltage being converted to the second DC voltage.
Referring to Fig. 2, being the circuit diagram of power circuit 110 provided by the invention.Power circuit 110 turns including first voltage
Change chip U5, second voltage conversion chip U6, insurance F, current-limiting resistance RX, the first electrolytic capacitor CX1, the second electrolytic capacitor CX2,
Varistor RV, high frequency fulgurite CY0, Transient Suppression Diode TVS, the 4th capacitor C4, the 5th capacitor C5, the 6th capacitor C6,
Seven capacitor C7, the 8th capacitor C8, the 9th capacitor C9, eleventh resistor R11, twelfth resistor R12, thirteenth resistor R13 and
Light emitting diode L1.
The end L series connection insurance F, current-limiting resistance RX and the third of voltage conversion chip U5 of second source signal incoming end J2 is drawn
Foot electrical connection, the N-terminal of second source signal incoming end J2 are electrically connected with the first pin of voltage conversion chip U5, varistor RV
One end be electrically connected to series connection insurance F, between current-limiting resistance RX, the other end of varistor RV is electrically connected to voltage conversion chip
The first pin of U5, the first electrolytic capacitor CX1 is in parallel with varistor RV, the 5th pin serial connection second of voltage conversion chip U5
It is electrically connected after electrolytic capacitor CX2 with the 7th pin of voltage conversion chip U5, the 7th pin serial connection of voltage conversion chip U5 is high
It is electrically connected after frequency fulgurite CY0 with the 12nd pin of voltage conversion chip U5, the 12nd pin serial connection of voltage conversion chip U5
Be electrically connected after 4th capacitor C4 with the 14th pin of voltage conversion chip U5, Transient Suppression Diode TVS, the 5th capacitor C5,
6th capacitor C6 and the 7th capacitor C7 is in parallel with the 4th capacitor C4 and is grounded, eleventh resistor R11 and twelfth resistor R12
It is series at after parallel connection between the 5th capacitor C5 and the 6th capacitor C6, one end of the 7th capacitor C7 is with second voltage conversion chip U6's
Signal input part electrical connection, the ground terminal ground connection of second voltage conversion chip U6, the signal output of second voltage conversion chip U6
It is grounded after the 8th capacitor C8 of end series connection, the 9th capacitor C9 is in parallel with the 8th capacitor C8, light emitting diode L1 series connection thirteenth resistor
It is in parallel with the 8th capacitor C8 after R13.
Wherein, insurance F is used for overcurrent and overheating protection, and restores automatically when the electric current in circuit restores normal；Current-limiting resistance
RX is exported for limiting second source signal incoming end J2 to the electric current of voltage conversion chip U5；Varistor RV can effectively press down
Surge in circuit processed；When circuit works normally, Transient Suppression Diode TVS is in high-impedance state, once and circuit occurs
Abnormal, Transient Suppression Diode TVS rapidly goes to low resistance state, and by abnormal high pressure clamper within a safe voltage, from
And protect chip and circuit.
In addition, the first DC voltage is exported by the 14th pin of voltage conversion chip U5.In the present embodiment, first is straight
Galvanic electricity pressure is 12V；Second DC voltage is exported by the signal output end of second voltage conversion chip U6.In the present embodiment,
Two DC voltages are 5V.
Therefore, when power circuit 110 works normally, light emitting diode L1 is lit, and shows that power circuit 110 is normal defeated
5V voltage out.
In a kind of optional embodiment, the model LD03-10B12R2 of voltage conversion chip U5, for exchange
Electricity is converted to direct current；Second voltage conversion chip U6 is 7805 voltage-stablizers.
Start-up circuit 120 is believed for generating clock signal, reset signal and enable signal, and by clock signal, reset
Number and enable signal be transmitted to delay circuit 130.
Referring to Fig. 3, being the circuit diagram of start-up circuit 120 provided by the invention.Start-up circuit 120 is believed including the first power supply
Number incoming end J1, rectifier bridge U3, optocoupler U4, the 7th resistance R7, the 8th resistance R8, third diode D3, the 4th switching tube Q4, when
Clock signal output end clock, reset signal output end MR and enable signal output end OE, the first power supply signal incoming end J1 according to
After the first output end differential concatenation third diode D3, the 8th resistance R8 of secondary series rectifier bridge U3 and optocoupler U4, optocoupler U4 with
Power circuit 110 is electrically connected, and is electrically connected after the 7th resistance R7 of the first output end series connection of optocoupler U4 with the base stage of the 4th switching tube Q4
It connects, the emitter of the 4th switching tube Q4 is electrically connected with power circuit 110, the second output terminal of optocoupler U4 and the 4th switching tube Q4's
Grounded collector, clock signal output terminal clock are electrically connected with the first output end of optocoupler U4, reset signal output end MR and
The collector of four switching tube Q4 is electrically connected, enable signal output end OE electrical connection electricity in the 8th resistance R8 and third diode D3 it
Between.Wherein, the 4th switching tube Q4 is PNP triode.
Wherein, clock signal output terminal clock is resetted for exporting clock signal, reset signal output end MR for exporting
Signal, enable signal output end OE is for exporting enable signal.
It is to be appreciated that optocoupler U4 is connected when the first power supply signal incoming end J1 accesses supply voltage, clock signal is defeated
The level of outlet clock is pulled low, so that third diode D3 is connected, so that the level of enable signal output end OE is pulled low,
The base stage of the 4th switching tube Q4 is pulled low as the level of clock signal output terminal clock simultaneously, the 4th switching tube Q4 conducting,
The level of reset signal output end MR is drawn high by power circuit 110.
To, when the first power supply signal incoming end J1 accesses supply voltage, clock signal output terminal clock and enabled
Signal output end OE exports low level, and reset signal output end MR exports high level.
Delay circuit 130 according to presetting time interval for successively giving birth to after receiving clock signal and reset signal
Driving circuit 140 corresponding with each enabling signal is transmitted separately at multiple enabling signals, and by multiple enabling signals.
Wherein, multiple enabling signals and multiple driving circuits 140 correspond.
Referring to Fig. 4, delay circuit 130 includes frequency unit 132 and shift unit 134, start-up circuit 120 and frequency dividing
Unit 132 and shift unit 134 are electrically connected, and frequency unit 132 is electrically connected with shift unit 134, shift unit 134 and multiple drives
Dynamic circuit 140 is electrically connected.
Frequency unit 132 is for after receiving clock signal, generating data input clock signal and output latch clock
Signal, and enter data into clock signal and export latching clock signal and be transmitted to shift unit 134；Wherein, data input
Clock signal is identical as the output period of latching clock signal and level is opposite.
After frequency unit 132 is also used to receive reset signal, output latching clock signal is reset.
Referring to Fig. 5, being the circuit diagram of frequency unit 132 provided by the invention.Frequency unit 132 include frequency divider U1,
Timing resistor Rtc, timing capacitor Ctc, first switch tube Q1, second switch Q2, first resistor R1, second resistance R2, third
Resistance R3, the 4th resistance R4, the first signal output end SH_CP, second signal output end ST_CP, first capacitor C1, the one or two pole
Pipe D1, the second diode D2, third switching tube Q3, the 5th resistance R5 and the 6th resistance R6, frequency divider U1 the first pin with
Timing resistor Rtc electrical connection, the second pin of frequency divider U1 are electrically connected with timing capacitor Ctc, timing resistor Rtc and timing capacitor
Ctc electrical connection, the 6th pin of frequency divider U1 is electrically connected with clock signal output terminal clock, the output pin of frequency divider U1 and
The base stage of first switch tube Q1 is electrically connected, electric with power circuit 110 after the collector series connection first resistor R1 of first switch tube Q1
Connection, the emitter ground connection of first switch tube Q1, second switch Q2 is in parallel with first switch tube Q1, the base of second switch Q2
Pole is electrically connected after being sequentially connected in series 3rd resistor R3, second resistance R2 with power circuit 110, the collector string of second switch Q2
It is electrically connected after joining the 4th resistance R4 with power circuit 110, the emitter ground connection of second switch Q2, the first signal output end SH_
CP is electrically connected between the collector of first switch tube Q1 and first resistor R1, and the company with second resistance R2 and 3rd resistor R3
Contact electrical connection, second signal output end ST_CP are electrically connected between the collector of second switch Q2 and the 4th resistance R4, multiple
It is electrically connected after position signal output end MR series connection first capacitor C1, the 5th resistance R5 with the base stage of third switching tube Q3, the one or two pole
Pipe D1 and the 5th resistance R5 reverse parallel connection are grounded after the second diode of base stage differential concatenation D2 of third switching tube Q3, and third is opened
The emitter ground connection of pipe Q3 is closed, is electrically connected after the 6th resistance R6 of collector series connection of third switching tube Q3 with power circuit 110, the
Binary signal output end ST_CP is also electrically coupled between the collector and the 6th resistance R6 of third switching tube Q3.
Wherein, the first signal output end SH_CP is used for output data input clock signal；Second signal output end ST_CP
For exporting latching clock signal.
In a kind of optional embodiment, frequency divider U1 is CD4541 frequency divider.CD4541 frequency divider is that one kind can be compiled
Journey frequency divider can match its oscillation frequency by timing resistor Rtc, timing capacitor Ctc.
Wherein, the concussion period meets formula: T=2.3nRtc*Ctc, oscillation frequency meet formula:N is frequency dividing
Coefficient.
Frequency division coefficient is determined by the level U1.A and the level U1.B of the 13rd pin of the 12nd pin of frequency divider U1.Tool
Body, if U1.A=0, U1.B=0, then n=4096；If U1.A=0, U1.B=1, then n=512；If U1.A=1, U1.B=
0, then n=128；If U1.A=1, U1.B=1, then n=32768.
For example, timing resistor Rtc is 22 kilo-ohms, timing capacitor Ctc is 10nf, and frequency division coefficient n is 32768, then shaking
Cycle T=2.3 × 32768 × 22 × 10 × 10-6≈16s。
In addition, the 6th pin of frequency divider U1 is reset terminal, high level is effective namely the 6th pin of frequency divider U1 is height
When level, frequency divider U1 resets；When the 6th pin of U1 is low level, frequency divider U1 could be worked normally.To start-up circuit
When 120 normal work, clock signal output terminal clock provides low level signal for the 6th pin of frequency divider U1, makes score
Frequency device U1 can be worked normally.
When frequency divider U1 is worked normally, output pin exports different level signals every a concussion period.With
The period is shaken for for 15s, then the output pin of frequency divider U1 exports high level in 15s, exports low level in 30s,
High level is exported when 45s, and so on.
When the output pin of frequency divider U1 exports high level, first switch tube Q1 conducting, the first signal output end SH_CP
Level by first switch tube Q1 be pulled down to ground, while the base stage of second switch Q2 be low level, second switch Q2 cut-off,
The level of second signal output end ST_CP is drawn high by power circuit 110；When the output pin of frequency divider U1 exports low level,
First switch tube Q1 cut-off, the level of the first signal output end SH_CP is drawn high by power circuit 110, thus second switch Q2
Conducting, the level of second signal output end ST_CP are pulled down to ground by second switch Q2.
To which when the output pin of frequency divider U1 exports high level, the first signal output end SH_CP exports low level letter
Number, second signal output end ST_CP exports high level signal；When the output pin of frequency divider U1 exports low level, the first letter
Number output end SH_CP exports high level signal, and second signal output end ST_CP exports low level signal.That is, second signal is defeated
The level signal of outlet ST_CP and the level signal of second signal output end ST_CP are on the contrary, and the period is shake the period two
Times.
In addition, reset signal output end MR exports high level signal to third and switchs when start-up circuit 120 just starts
The base stage of pipe Q3, so that the level of second signal output end ST_CP is pulled low, is completed primary so that third switching tube Q3 is connected
Clear operation.
It should be noted that the effect of logical exchange stopping direct current is realized, to only open by setting first capacitor C1
When dynamic circuit 120 just starts, the output signal of reset signal output end MR includes AC signal, could make third switching tube
Q3 conducting；And after 120 start completion of start-up circuit, reset signal output end MR exports the direct current signal of high level, then can not lead to
First capacitor C1 is crossed, ensure that second signal output end ST_CP being capable of normal output signal.
Shift unit 134 is for according to data input clock signal and exporting latch clock after receiving reset signal
Signal sequentially generates multiple enabling signals.
Referring to Fig. 6, being the circuit diagram of shift unit 134 provided by the invention.Shift unit 134 includes shift register
U2 and multiple signal output units, multiple signal output units and multiple driving circuits 140 correspond, shift register U2
Data input clock pin SHCP be electrically connected with the first signal output end SH_CP, the output latch clock of shift register U2
Pin STCP is electrically connected with second signal output end ST_CP, the reset pin of shift register U2 and multiple signal output units
In the electrical connection of a signal output unit, multiple data output pins of shift register U2 are single with the output of signal respectively
Member electrical connection, the enabled pin of shift register U2 are electrically connected with the enable signal output end OE of start-up circuit 120, shift LD
The reset pin of device U2 is electrically connected with the reset signal output end MR of start-up circuit 120.
In the present embodiment, shift register U2 is 74HC595, and 74HC595 is for 8 Bits Serial input/output or parallel
Output Shift Register.Wherein, the data input clock pin SHCP of shift register U2 is in rising edge time shift bit register
Data displacement is kept in the data of failing edge time shift bit register；The output latch clock pin STCP of shift register U2 exists
The data of rising edge time shift bit register enter data storage register, and in failing edge, storage register data are constant.
To which when start-up circuit 120 starts, reset signal output end MR exports high level, and is exported by multiple signals
A signal output unit in unit exports high level signal to a driving circuit 140；Meanwhile enable signal output end OE
Low level is exported, shift register U2 is worked normally, while the first signal output end SH_CP and second signal output end ST_CP
Reversed low and high level is just inputted every the concussion period of a frequency unit 132, so that presetting time interval backward shift
The Q0 pin output high level signal of register U2 is simultaneously kept, the Q1 pin output high level letter after presetting time interval
Number and keep, the output of Q2 pin and is kept high level signal after presetting time interval, to realize according to default
Fixed time interval sequentially generates the effect of multiple enabling signals.
Multiple driving circuits 140 are for responding corresponding enabling signal and being connected, so as to distinguish with multiple driving circuits 140
Multiple loads of electrical connection successively start according to presetting time interval.
Referring to Fig. 7, being the circuit diagram of driving circuit 140 provided by the invention.Each driving circuit 140 includes the 5th
Switching tube Q5, relay KM, the second capacitor C2, third capacitor C3, the 9th resistance R9, the tenth resistance R10 and the 4th diode
The base stage of D2, the 5th switching tube Q5 are electrically connected with shift register, the emitter ground connection of the 5th switching tube Q5, the 5th switching tube Q5
Collector connect the 9th resistance R9, be electrically connected with power circuit 110 after relay KM, the second capacitor C2 forward direction connects the four or two
Touching in parallel with the 9th resistance R9 and relay KM after pole pipe D2, after the tenth resistance R10 of third capacitor C3 series connection with relay KM
Point is in parallel.
After driving circuit 140 receives enabling signal, the base stage access high level signal of the 5th switching tube Q5, the 5th
The coil of switching tube Q5 conducting, relay KM is powered to the contact closure of relay KM, thus loaded work piece.
Wherein, the 4th diode D2 is freewheeling diode, its afterflow acts in the coil turn off process of relay KM；The
Nine resistance R9 and the second capacitor C2 can reduce voltage when relay KM is attracted, and reduce the power consumption of relay KM；Tenth resistance
R10 and third capacitor C3 forms RC circuit, and the contact shunt with relay KM, and the spark of the contact relay KM can be absorbed.
Simultaneously because the time that different driving circuits 140 receives enabling signal is different, in each driving circuit
140 receive enabling signal after loaded work piece is all made according to above-mentioned principle, thus realize multiple loads timesharing starting, keep away
Exempt from while having started the impact to power grid.
In addition, in the present invention, the chips such as frequency divider U1, shift register U2 are CMOS chip, anti-interference ability
It is stronger compared to single-chip microcontroller, it is not easy to be disturbed under forceful electric power magnetic environment；Importantly, it is low in cost, so that point produced
When starting module 100 have the market competitiveness.
In conclusion a kind of timesharing starting module provided in an embodiment of the present invention, including start-up circuit, delay circuit and
Multiple driving circuits, delay circuit are electrically connected with start-up circuit and multiple driving circuits, and start-up circuit is for generating clock signal
And reset signal, and clock signal and reset signal are transmitted to delay circuit, delay circuit for receive clock signal and
After reset signal, multiple enabling signals, multiple enabling signals and multiple drivings electricity are sequentially generated according to presetting time interval
Road corresponds, and delay circuit is also used to for multiple enabling signals being transmitted separately to driving electricity corresponding with each enabling signal
Road, multiple driving circuits are for responding corresponding enabling signal and being connected, so as to be electrically connected with multiple driving circuits more
A load successively starts according to presetting time interval；Due to realizing the delay of load in the case where not using single-chip microcontroller
Starting more fits in practical application to reduce the cost of manufacture timesharing starting module.
The foregoing is only a preferred embodiment of the present invention, is not intended to restrict the invention, for the skill of this field
For art personnel, the invention may be variously modified and varied.All within the spirits and principles of the present invention, made any to repair
Change, equivalent replacement, improvement etc., should all be included in the protection scope of the present invention.
Claims (10)
1. a kind of timesharing starting module, which is characterized in that the timesharing starting module includes start-up circuit, delay circuit and more
A driving circuit, the delay circuit are electrically connected with the start-up circuit and multiple driving circuits；
The start-up circuit is transmitted for generating clock signal and reset signal, and by the clock signal and the reset signal
To the delay circuit；
The delay circuit for after receiving the clock signal and the reset signal, according to presetting time interval according to
Secondary to generate multiple enabling signals, the multiple enabling signal and the multiple driving circuit correspond；
The delay circuit is also used to for the multiple enabling signal being transmitted separately to institute corresponding with each enabling signal
State driving circuit；
The multiple driving circuit is for responding the corresponding enabling signal and being connected, so that with the multiple driving circuit point
The multiple loads not being electrically connected successively start according to presetting time interval.
2. timesharing starting module according to claim 1, which is characterized in that the delay circuit include frequency unit and
Shift unit, the start-up circuit are electrically connected with the frequency unit and the shift unit, the frequency unit and the shifting
Bit location electrical connection, the shift unit are electrically connected with multiple driving circuits；
The frequency unit is for after receiving the clock signal, generating data input clock signal and output latch clock
Signal, and the data input clock signal and the output latching clock signal are transmitted to the shift unit；Wherein,
The data input clock signal is identical as the output period of latching clock signal and level is opposite；
After the shift unit is used to receive the reset signal, according to the data input clock signal and the output
Latching clock signal sequentially generates the multiple enabling signal.
3. timesharing starting module according to claim 2, which is characterized in that the frequency unit includes frequency divider, timing
Resistance, timing capacitor, first switch tube, second switch, first resistor, second resistance, 3rd resistor, the 4th resistance, first
First pin of signal output end and second signal output end, the frequency divider is electrically connected with the timing resistor, and described point
The second pin of frequency device is electrically connected with the timing capacitor, and the timing resistor is electrically connected with the timing capacitor, the frequency dividing
The output pin of device is electrically connected with the base stage of the first switch tube, the collector series connection of the first switch tube first electricity
It is electrically connected after resistance with power circuit, the emitter ground connection of the first switch tube, the second switch and the first switch
Pipe is in parallel, and the base stage of the second switch is sequentially connected in series after the 3rd resistor, the second resistance and power supply electricity
Road is electrically connected, and is electrically connected after collector series connection the 4th resistance of the second switch with power circuit, described second opens
The emitter ground connection of pipe is closed, first signal output end is electrically connected to the collector and first electricity of the first switch tube
It between resistance, and is electrically connected with the second resistance with the tie point of the 3rd resistor, the second signal output end electrical connection
Between the collector and the 4th resistance of the second switch；
First signal output end is for exporting the data input clock signal；
The second signal output end is for exporting the output latching clock signal.
4. timesharing starting module according to claim 3, which is characterized in that the frequency unit is described multiple for receiving
After the signal of position, the output latching clock signal is reset.
5. timesharing starting module according to claim 4, which is characterized in that the frequency unit further include first capacitor,
First diode, the second diode, third switching tube, the 5th resistance and the 6th resistance, start-up circuit series connection described the
It is electrically connected after one capacitor, the 5th resistance with the base stage of the third switching tube, the first diode and the 5th electricity
Reverse parallel connection is hindered, is grounded after the second diode described in the base stage differential concatenation of the third switching tube, the third switching tube
Emitter is grounded, and is electrically connected after collector series connection the 6th resistance of the third switching tube with the power circuit, described
Second signal output end is also electrically coupled between the collector of the third switching tube and the 6th resistance.
6. timesharing starting module according to claim 3, which is characterized in that the shift unit include shift register with
And multiple signal output units, the multiple signal output unit and the multiple driving circuit correspond, the displacement is posted
The data input clock pin of storage is electrically connected with first signal output end, the output latch clock of the shift register
Pin is electrically connected with the second signal output end, the reset pin of the shift register and the multiple signal output unit
In a signal output unit electrical connection, multiple data output pins of the shift register respectively with a signal
Output unit electrical connection.
7. timesharing starting module according to claim 6, which is characterized in that the start-up circuit includes the first power supply signal
Incoming end, rectifier bridge, optocoupler, the 7th resistance, the 8th resistance, third diode, the 4th switching tube, clock signal output terminal and
Reset signal output end, the first power supply signal incoming end are sequentially connected in series the rectifier bridge and the optocoupler, the optocoupler
Third diode described in first output end differential concatenation is electrically connected after the 8th resistance with the power circuit, the optocoupler
The first output end connect and be electrically connected with the base stage of the 4th switching tube after the 7th resistance, the hair of the 4th switching tube
Emitter-base bandgap grading is electrically connected with the power circuit, the grounded collector of the second output terminal of the optocoupler and the 4th switching tube, institute
It states clock signal output terminal to be electrically connected with the first output end of the optocoupler, the reset signal output end and the 4th switch
The collector of pipe is electrically connected；
The clock signal output terminal is for exporting the clock signal；
The reset signal output end is for exporting the reset signal.
8. timesharing starting module according to claim 6, which is characterized in that each driving circuit includes the 5th to open
Guan Guan, relay, the second capacitor, third capacitor, the 9th resistance, the tenth resistance and the 4th diode, the 5th switching tube
Base stage be electrically connected with the shift register, the emitter of the 5th switching tube ground connection, the current collection of the 5th switching tube
It is electrically connected after pole series connection the 9th resistance, the relay with the power circuit, described in the second capacitor forward direction series connection
It is in parallel with the 9th resistance and the relay after 4th diode, the third capacitor connect after the tenth resistance with institute
State the contact shunt of relay.
9. timesharing starting module described in any one of -8 according to claim 1, which is characterized in that the timesharing starting module
It further include power circuit, the power circuit and the start-up circuit, the delay circuit and multiple driving circuits are equal
Electrical connection.
10. timesharing starting module according to claim 9, which is characterized in that the power circuit includes second source letter
Number incoming end, first voltage converting unit and second voltage converting unit, the second source signal incoming end, described first
Voltage conversion unit and the second voltage converting unit are sequentially connected electrically；
The first voltage converting unit is used to the supply voltage that the second source signal incoming end accesses being converted to first
DC voltage；
The second voltage converting unit is used to first DC voltage being converted to the second DC voltage.
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| CN201910075763.5A CN109510515A (en) | 2019-01-25 | 2019-01-25 | A kind of timesharing starting module |
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| CN111740405A (en) * | 2020-05-29 | 2020-10-02 | 科华恒盛股份有限公司 | Starting control method, system and device of electrical equipment |
| CN111785569A (en) * | 2020-06-29 | 2020-10-16 | 佛山科学技术学院 | A soft-start relay control circuit and charging circuit |
| CN113437864A (en) * | 2021-06-25 | 2021-09-24 | 中国船舶重工集团公司第七0七研究所 | Time-sharing starting module and method for power supply of fiber-optic gyroscope inertial positioning and orientation system |
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