CN109509732A - The pressure welding dish structure and its process of integrated circuit - Google Patents
The pressure welding dish structure and its process of integrated circuit Download PDFInfo
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- CN109509732A CN109509732A CN201710831363.3A CN201710831363A CN109509732A CN 109509732 A CN109509732 A CN 109509732A CN 201710831363 A CN201710831363 A CN 201710831363A CN 109509732 A CN109509732 A CN 109509732A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
- H01L21/4814—Conductive parts
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/561—Batch processing
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
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Abstract
A kind of the pressure welding dish structure and its process of integrated circuit, the pressure welding dish structure of integrated circuit includes P-type silicon substrate, separation layer, deep N-well, P+ active area, N+ active area, first medium layer, the first metal layer, second dielectric layer, second metal layer, third dielectric layer and third metal layer, wherein, deep N-well is that figure injection is formed in P-type silicon substrate in a distributed manner, and the first metal layer is divided into the firstth area and the secondth area, firstth area connects P+ active area by the metal of one first contact hole, and the secondth area connects N+ active area by the metal of one second contact hole.
Description
Technical field
The present invention relates to the pressure welding dish structures and its process of integrated circuit, espespecially a kind of to be applied to wafer stage chip ruler
The pressure welding dish structure and its process of the integrated circuit of very little encapsulation (WLCSP).
Background technique
In general, high speed integrated circuit (IC) has generallyd use crystal wafer chip dimension encapsulation (WLCSP), such envelope
Dress mode is able to satisfy the application demand of small size, frivolous, data transmission stability and heat dissipation of various portable products etc.,
However this also brings a serious problem, is exactly that wafer-level package mostly uses greatly plant ball mode, and the diameter of soldered ball generally exists
180um or more thus may require that the length and width dimensions of chip pressure welding disk (PAD) metal in 200um or more, such bond pad
The wire-bonding package that the area ratio of PAD is common is much larger (reaching 4~10 times), thus introduces bigger to substrate than what is commonly encapsulated
Parasitic capacitance much may reach hundreds of flying methods (fF), and for the input signal of High Speed ICs, i.e. frequency can be arrived in 800M
Between 10G for signal, the input capacitance of hundreds of fF can bring sizable signal to decay.
For example, for high-speed switch IC, can pass through from input terminal to output end two pressures of the transmission of high speed signal
Pad is possible to then bond pad parasitic capacitance adds up close to 1 pico farad (pf), this will become the master for generating signal decaying
Want factor.The parasitic capacitance over the ground that the bond pad of wafer level packaging introduces so how is effectively reduced, reduces the signal under high frequency
Decaying, becomes a very crucial problem of such high speed circuit.The existing method for reducing the parasitic capacitance has increase core
Piece interconnection metal number, such as 3 layers of metal become 5 layers, and the bond pad metal layer of such top is between the silicon substrate of ground connection
Dielectric thickness increase, so that it may realize the reduction of capacitor, but bring very big process costs in this way and increase, it is every to increase by one layer
Metal will additionally increase by two technique light shield levels, sharply increase chip cost.
Therefore, how a kind of parasitic capacitance over the ground that bond pad can be effectively reduced is provided, and the collection of extra cost can be saved
At the pressure welding dish structure and its process of circuit, as each dealer project urgently to be resolved.
Summary of the invention
In view of the disadvantages of the prior art, the main object of the present invention, that is, being to provide a kind of can be effectively reduced pressure welding
The parasitic capacitance over the ground of disk, and the pressure welding dish structure and its process of the integrated circuit of extra cost can be saved.
In order to achieve the above object and other purposes, the present invention provide a kind of pressure welding dish structure of integrated circuit, including p-type
Silicon substrate, separation layer, deep N-well, P+ active area, N+ active area, first medium layer, the first metal layer, second dielectric layer, the second gold medal
Belong to layer, third dielectric layer and third metal layer.
Wherein, separation layer is formed in P-type silicon substrate；Deep N-well is formed between P-type silicon substrate and separation layer, and deep N-well
It is that figure injection is formed in P-type silicon substrate in a distributed manner；P+ active area is formed in P-type silicon substrate and by separation layer；N+ has
Source region is formed in deep N-well；First medium layer is formed on separation layer；The first metal layer is formed on first medium layer, and first
Metal layer is divided into the firstth area and the secondth area, and the firstth area connects P+ active area by the metal of one first contact hole, and the secondth area is logical
Cross the metal connection N+ active area of one second contact hole；Second dielectric layer is formed on first medium layer；Second metal layer is formed
In second dielectric layer；Third dielectric layer is formed in second metal layer；And third metal layer is formed on third dielectric layer.
In one embodiment, distributed graphic is square, polygon, circle or repetitive pattern ring-like with one heart.
In one embodiment, the spacing of adjacent distributed graphic is between 0.5 times to 1.6 times of deep N-well junction depth.
In one embodiment, deep N-well floating or be connected to a selection of appointed, selection of appointed 0V into integrated circuit most
Between high potential.
It in one embodiment, further include a p type island region domain in deep N-well.
It in one embodiment, further include a n-type region in the domain of p type island region.
In one embodiment, the thickness of second dielectric layer or third dielectric layer is at (thousand angstroms, 1 angstrom=1Angstrom=of 15KA
0.1 nanometer) between 50KA.
The present invention also provides a kind of processes of the pressure welding dish structure of integrated circuit, comprising the following steps: in a P-type silicon
Separation layer is formed on substrate；In separation layer spin coating photoresist, and photoetching is carried out to photoresist to form distributed graphic injection window
Mouthful；Injection is doped to form deep N-well in P-type silicon substrate, and removes photoresist；Thermal diffusion is carried out, to enable deep N-well pass through
Diffusion is mutually overlapping；P+ active area is formed in P-type silicon substrate, and N+ active area is formed in deep N-well；It forms sediment on separation layer
Product forms first medium layer；First medium layer is made by lithography respectively correspond the first contact hole of P+ active area and N+ active area with
And second contact hole, and metal is filled to the first contact hole and the second contact hole；Deposit forms first on first medium layer
Metal layer, and to the first metal layer litho pattern and formed and respectively correspond the first Qu Yu of the first contact hole and the second contact hole
2nd area；Deposit forms second dielectric layer on the first metal layer；Deposit forms second metal layer in second dielectric layer, and to the
Two metal layer lithography figures；Deposit forms third dielectric layer in second metal layer；And it deposits and is formed on third dielectric layer
Third metal layer.
In one embodiment, distributed graphic is square, polygon, circle or repetitive pattern ring-like with one heart.
In one embodiment, the process of the pressure welding dish structure of integrated circuit further includes depositing shape on the first metal layer
After second dielectric layer, second dielectric layer is ground to specified thickness, specified thickness is in 15KA between 50KA.
In one embodiment, the process of the pressure welding dish structure of integrated circuit further includes that shape is deposited in second metal layer
After third dielectric layer, third dielectric layer is ground to specified thickness, specified thickness is in 15KA between 50KA.
Compared to the prior art, due to the pressure welding dish structure of integrated circuit of the invention have be formed in P-type silicon substrate with
Deep N-well between separation layer, and deep N-well is that figure injection is formed in P-type silicon substrate in a distributed manner, deep N-well can be served as a contrast with P-type silicon
Bottom forms the PN junction of lighter doping, and makes the parasitic capacitance of bond pad and P-type silicon substrate because sealing in lesser capacitance of PN junction
Become smaller, on the other hand the thickness of second dielectric layer, third dielectric layer is then increased, to reduce dielectric capacitance, and can be further
Reduce parasitic capacitance.In addition, the pressure welding dish structure of integrated circuit of the invention can be by easily real after existing technologic improvement
It is existing, additional technique light shield level will not be generated, cost will not be increased, substantially overcomes possessed in the prior art ask
Topic.
Detailed description of the invention
Fig. 1 is the configuration diagram of the pressure welding dish structure of the integrated circuit of one embodiment of the invention.
Fig. 2 is the cell layout schematic top plan view of the distributed graphic injection zone of one embodiment of the invention.
Fig. 3 is the cell layout schematic cross-section of the distributed graphic injection zone of one embodiment of the invention.
Fig. 4 is the step flow chart of the process of the pressure welding dish structure of the integrated circuit of one embodiment of the invention.
Fig. 5 is the part steps process of the process of the pressure welding dish structure of the integrated circuit of another embodiment of the present invention
Figure.
Symbol description:
The pressure welding dish structure of 1 integrated circuit
10 P-type silicon substrates
11 separation layers
12 deep N-wells
13 P+ active areas
14 N+ active areas
15 first medium layers
16a the first metal layer (the firstth area)
16b the first metal layer (the secondth area)
17 second dielectric layer
18 second metal layers
19 third dielectric layers
20 third metal layers
21 passivation layers
22 slicker solder soldered balls
23 first contact holes
24 second contact holes
S1~S12 step
S9a, S11a step
Specific embodiment
Illustrate embodiments of the present invention by particular specific embodiment below, those skilled in the art can be by this theory
Other advantages and efficacy of the present invention can be easily understood for the bright revealed content of book.The present invention also can be different specific by other
Embodiment is implemented or is applied.
Referring to Fig. 1, Fig. 1 is the configuration diagram of the pressure welding dish structure of the integrated circuit of one embodiment of the invention.Such as figure
It is shown, the pressure welding dish structure 1 of integrated circuit of the invention, including P-type silicon substrate 10, separation layer 11, deep N-well 12, P+ active area
13, N+ active area 14, first medium layer 15, the first metal layer 16a, 16b, second dielectric layer 17, second metal layer 18, third are situated between
Matter layer 19 and third metal layer 20.
In other examples, the pressure welding dish structure 1 of integrated circuit of the invention is not limited to three-layer metal in Fig. 1
Situation can be the chip of four layers, five layers etc. more metal levels.Metal layer medium (such as first medium layer 15, second medium
Layer 17, third dielectric layer 19) it is not limited to most common oxide layer medium, it further include low-K (low-k) material medium layer
Etc., in addition, can also deposit to form passivation layer 21 on the metal layer of top, and in the passivation layer 21 of top-level metallic
Slicker solder soldered ball 22 is formed in bond pad window.
As shown in Figure 1, separation layer 11 is formed in P-type silicon substrate 10；Deep N-well 12 be formed in P-type silicon substrate 10 be isolated
Between layer 11, and deep N-well 12 is that figure injection is formed in P-type silicon substrate 10 in a distributed manner；P+ active area 13 is formed in P-type silicon
On substrate 10 and by separation layer 11；N+ active area 14 is formed in deep N-well 12；First medium layer 15 is formed on separation layer 11；
The first metal layer 16a, 16b are formed on first medium layer 15, and the first metal layer 16a, 16b points are the first area 16a and second
Area 16b, the first area 16a connect P+ active area 13 by the metal of one first contact hole 23, and the second area 16b passes through one second contact
The metal in hole 24 connects N+ active area 14；Second dielectric layer 17 is formed on first medium layer 15；Second metal layer 18 is formed in
In second dielectric layer 17；Third dielectric layer 19 is formed in second metal layer 18；And third metal layer 20 is formed in third Jie
On matter layer 19.
For convenience of description, enable top-level metallic i.e. third metal layer 20 to the dielectric layer of the silicon face of P-type silicon substrate 10
Capacitor is C1, and the capacitance of PN junction of deep N-well 12 to ground is C2.The parasitic capacitance of pressure welding dish structure in the prior art is about roughly equal to
C1, however, since the pressure welding dish structure 1 of integrated circuit of the invention introduces the capacitance of PN junction C2 that deep N-well 12 arrives ground, so that third
The parasitic capacitance on metal layer 20 to ground becomes the series connection of capacitor C1 and capacitor C2, that is, becomes C1*C2/ (C1+C2), compared with capacitor
The value of C1 is small, and can be because the value of capacitor C2 becomes smaller and enables whole parasitic capacitance smaller.
Still further, the present invention additionally uses a kind of PN junction structure of the deep N-well 12 of distributed graphic to reduce C2.
Due to capacitance of PN junction and the linear inverse relation of depletion width, so C2 can be reduced by increasing PN junction depletion width, that
Slice width is exhausted it is found that reducing PN junction two sides doping concentration and can increase with increase reversed bias voltage according to Semiconductor Physics formula
Degree, i.e. reduction capacitor.Current potential in deep N-well 12 can be accessed in application, and PN junction depletion layer also can be with the increasing of reversed bias voltage
Add and increase, capacitance C2 reduces.
Please refer to figs. 2 and 3, and Fig. 2 is that the cell layout of the distributed graphic injection zone of one embodiment of the invention is overlooked
Schematic diagram, Fig. 3 are the cell layout schematic cross-section of the distributed graphic injection zone of one embodiment of the invention.In an embodiment
In, distributed graphic can be square, polygon, circle or repetitive pattern ring-like with one heart.It is in the embodiment of Fig. 2 and Fig. 3
By taking the distributed graphic of square as an example, deep N-well 12 is that figure injection is formed in P-type silicon substrate 10 in a distributed manner, is then led to
It crosses diffusion to interlink, such figure, which can inject doping concentration compared with 12 figure of monolith deep N-well, to be reduced, and can met
Basic technology rule adjusts shape, size and the spacing of figure to advanced optimize the doping concentration of PN junction in the case where requiring,
Figure, size and the spacing of distribution injection can all have an impact to the pattern of this PN junction.
In Fig. 2, blank square region is the regional graphics for having injection deep N-well 12, and the region filled is photoresist gear
The region that cannot firmly inject after injection, will do it high temperature propulsion, and the doping of deep N-well 12 injected in this way can mutually be handed over by spreading
It is folded, as shown in Figure 3.Region dopant concentration after diffusion can inject lighter than 12 monolith of deep N-well.It is thus reversed in identical PN junction
Under biasing, the deep N-well 12 of this distributed graphic can form the PN junction with wider depletion layer with P-type silicon substrate 10.
In one embodiment, the spacing of adjacent distributed graphic is lifted between 0.5 times to 1.6 times of 12 junction depth of deep N-well
For example, 12 junction depth of deep N-well according to technique is 5um (micron), then the spacing of adjacent distributed graphic is that 2.5um is arrived
Between 8um.
In one embodiment, deep N-well 12 floating or can be connected to a selection of appointed, and selection of appointed is in 0V into integrated circuit
Maximum potential between.
In one embodiment, it may also include a p type island region domain in deep N-well 12, and may also include a n-type region in the domain of p type island region.
P-type can also be reinjected in deep N-well 12 continue series connection and come in a capacitance of PN junction, while can also reinject N-type in the p type island region domain
Region is connected capacitance of PN junction etc. again, can seal in multiple capacitance of PN junction to further decrease parasitic capacitance.
In one embodiment, the thickness of second dielectric layer 17 or third dielectric layer 19 is in 15KA between 50KA.As ditto
Content is stated, the parasitic capacitance of the pressure welding dish structure 1 of integrated circuit of the invention is C1*C2/ (C1+C2), by increasing first layer
The thickness of any inter-level dielectric on metal 16a, 16b, can further decrease capacitor C1, to reduce whole parasitism electricity
Hold.For example, in technique of the line width less than 0.35um, the thickness of second dielectric layer 17 or third dielectric layer 19 15KA extremely
Between 50KA, and in the prior art, the thickness of two inter-level dielectrics is respectively in 10KA or so, and second dielectric layer 17 of the invention
Thickness can be 20KA, and the thickness of third dielectric layer 19 then can be 30KA, and the thickness on third metal layer 20 to ground is several compared with the prior art
It doubles, and the half of the prior art is just decreased by almost in parasitic agent capacitor.Thickening each layer medium can bring one to ask
The problem of topic is exactly the depth-to-width ratio of through-hole 23,24 between metal, but can be constant by metal layer thickness, change the big of through-hole
Small perhaps each metal layer thickness increase accordingly that through-hole is constant or the mode that suitably increases realizes that both methods is in semiconductor
It can be conveniently realized in technique.
Referring to Fig. 4, Fig. 4 flows the step of being the process of the pressure welding dish structure of the integrated circuit of one embodiment of the invention
Cheng Tu.As shown, the present invention also provides a kind of processes of the pressure welding dish structure of integrated circuit, comprising the following steps:
S1: separation layer is formed in a P-type silicon substrate；
S2: in separation layer spin coating photoresist, and photoetching is carried out to photoresist to form distributed graphic injection window；
S3: injection is doped to form deep N-well in P-type silicon substrate, and removes photoresist；
S4: carrying out thermal diffusion, to enable deep N-well mutually overlapping by diffusion；
S5: forming P+ active area in P-type silicon substrate, and N+ active area is formed in deep N-well；
S6: deposit forms first medium layer on separation layer；
S7: the first contact hole and second for respectively corresponding P+ active area and N+ active area is made by lithography to first medium layer
Contact hole, and metal is filled to the first contact hole and the second contact hole；
S8: deposit forms the first metal layer on first medium layer, and to the first metal layer litho pattern and forms difference
The firstth area and the secondth area of corresponding first contact hole and the second contact hole；
S9: deposit forms second dielectric layer on the first metal layer；
S10: deposit forms second metal layer in second dielectric layer, and to second metal layer litho pattern；
S11: deposit forms third dielectric layer in second metal layer；And
S12: deposit forms third metal layer on third dielectric layer.
In addition, can also deposit passivation layer, and Etch Passivation window, expose third metal layer, and in third metal layer
Passivation layer bond pad window in formed slicker solder soldered ball.
For example, high energy ion implantation such as note is carried out in step S3 is doped to phosphorus, dosage 6e13/cm2, energy 1.5MKeV work
After skill step, photoresist is removed, step S4 diffusion is carried out after cleaning and is promoted, diffusion process grows thin oxidation firstly the need of on surface
Layer, then carries out high temperature with 1100 degree~1200 degree, picks into the deep N-well injected in this way within such as 4 hours to 12 hours for a long time
Doping can be mutually overlapping by spreading, and the n-type region lighter than deep N-well injection doping concentration can be obtained after diffusion.
In one embodiment, distributed graphic can be square, polygon, circle or repetitive pattern ring-like with one heart.
Referring to Fig. 5, Fig. 5 is the part of the process of the pressure welding dish structure of the integrated circuit of another embodiment of the present invention
Flow chart of steps.As shown, in one embodiment, the process of the pressure welding dish structure of integrated circuit may additionally include step
S9: on the first metal layer deposit formed after second dielectric layer, carry out step S9a: by second dielectric layer grinding (such as chemistry
Mechanical lapping) specified thickness is arrived, specified thickness is in 15KA between 50KA.
In one embodiment, the process of the pressure welding dish structure of integrated circuit further includes in step S11: in the second metal
Deposit is formed after third dielectric layer on layer, carries out step S11a: third dielectric layer grinding (such as chemical mechanical grinding) is arrived
Specified thickness, specified thickness is in 15KA between 50KA.Second dielectric layer and third dielectric layer can have different specified thicknesss.
In conclusion being formed in P-type silicon substrate and separation layer since the pressure welding dish structure of integrated circuit of the invention has
Between deep N-well, and deep N-well be in a distributed manner figure injection be formed in P-type silicon substrate, deep N-well can be formed with P-type silicon substrate
The PN junction of lighter doping, and because sealing in lesser capacitance of PN junction the parasitic capacitance of bond pad and P-type silicon substrate is become smaller, separately
On the one hand the thickness of second dielectric layer, third dielectric layer is then increased, to reduce dielectric capacitance, and parasitism can be further decreased
Capacitor.In addition, the pressure welding dish structure of integrated circuit of the invention can will not be produced by conveniently realizing after existing technologic improvement
Raw additional technique light shield level, will not increase cost, substantially overcome possessed problem in the prior art.
By the description of the above preferred embodiment, one skilled in the art is of the invention when can more understand
Feature and spirit, only above-described embodiment only illustrates the principle of the present invention and its effect, rather than to limit the present invention.Therefore,
The modification and change without departing from spirit of the invention, and interest field Ying Ruquan of the invention that any pair of above-described embodiment carries out
Listed by sharp claim.
Claims (11)
1. a kind of pressure welding dish structure of integrated circuit, which is characterized in that the pressure welding dish structure of the integrated circuit includes:
P-type silicon substrate；
Separation layer is formed in the P-type silicon substrate；
Deep N-well is formed between the P-type silicon substrate and the separation layer, and the deep N-well is that figure injects shape in a distributed manner
At in the P-type silicon substrate；
P+ active area is formed in the P-type silicon substrate and by the separation layer；
N+ active area is formed in the deep N-well；
First medium layer is formed on the separation layer；
The first metal layer is formed on the first medium layer, and the first metal layer is divided into the firstth area and the secondth area, described
Firstth area connects the P+ active area by the metal of one first contact hole, and secondth area passes through the metal of one second contact hole
Connect the N+ active area；
Second dielectric layer is formed on the first medium layer；
Second metal layer is formed in the second dielectric layer；
Third dielectric layer is formed in the second metal layer；And
Third metal layer is formed on the third dielectric layer.
2. the pressure welding dish structure of integrated circuit as described in claim 1, which is characterized in that the distributed graphic be square,
Polygon, circle or repetitive pattern ring-like with one heart.
3. the pressure welding dish structure of integrated circuit as claimed in claim 2, which is characterized in that the adjacent distributed graphic
Spacing is between 0.5 times to 1.6 times of the deep N-well junction depth.
4. the pressure welding dish structure of integrated circuit as described in claim 1, which is characterized in that the deep N-well floating is connected to
One selection of appointed, the selection of appointed is in 0V between maximum potential into integrated circuit.
5. the pressure welding dish structure of integrated circuit as described in claim 1, which is characterized in that further include a p-type in the deep N-well
Region.
6. the pressure welding dish structure of integrated circuit as claimed in claim 5, which is characterized in that further include a N in the p type island region domain
Type region.
7. the pressure welding dish structure of integrated circuit as described in claim 1, which is characterized in that the second dielectric layer or described
The thickness of three dielectric layers is in 15KA between 50KA.
8. a kind of process of the pressure welding dish structure of integrated circuit, which is characterized in that the process the following steps are included:
Separation layer is formed in a P-type silicon substrate；
In the separation layer spin coating photoresist, and photoetching is carried out to the photoresist to form distributed graphic injection window；
Injection is doped to form deep N-well in the P-type silicon substrate, and removes the photoresist；
Thermal diffusion is carried out, to enable the deep N-well mutually overlapping by diffusion；
P+ active area is formed in the P-type silicon substrate, and N+ active area is formed in the deep N-well；
Deposit forms first medium layer on the separation layer；
The first medium layer is made by lithography respectively correspond the first contact hole of the P+ active area and the N+ active area with
And second contact hole, and metal is filled to first contact hole and second contact hole；
Deposit forms the first metal layer on the first medium layer, and to the first metal layer litho pattern and forms difference
The firstth area and the secondth area of corresponding first contact hole and second contact hole；
Deposit forms second dielectric layer on the first metal layer；
Deposit forms second metal layer in the second dielectric layer, and to the second metal layer litho pattern；
Deposit forms third dielectric layer in the second metal layer；And
Deposit forms third metal layer on the third dielectric layer.
9. the process of the pressure welding dish structure of integrated circuit as claimed in claim 8, which is characterized in that the distributed figure
Shape is square, polygon, circle or repetitive pattern ring-like with one heart.
10. the process of the pressure welding dish structure of integrated circuit as claimed in claim 8, which is characterized in that further include in institute
It states deposit on the first metal layer to be formed after second dielectric layer, the second dielectric layer is ground to specified thickness, it is described specified
Thickness is in 15KA between 50KA.
11. the process of the pressure welding dish structure of integrated circuit as claimed in claim 8, which is characterized in that further include in institute
It states deposit in second metal layer to be formed after third dielectric layer, the third dielectric layer is ground to specified thickness, it is described specified
Thickness is in 15KA between 50KA.
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1281231A (en) * | 2000-08-18 | 2001-01-24 | 中国科学院上海冶金研究所 | Substrate junction isolated integrated silicon inductor and its making method |
| US20050242416A1 (en) * | 2004-04-29 | 2005-11-03 | United Microelectronics Corp. | Low-capacitance bonding pad for semiconductor device |
| CN102024774A (en) * | 2009-09-16 | 2011-04-20 | 上海宏力半导体制造有限公司 | Contact pad |
| CN101656239B (en) * | 2009-07-22 | 2011-06-15 | 上海宏力半导体制造有限公司 | Bonding welding disk lowering parasitic capacitance and preparing method thereof |
-
2017
- 2017-09-15 CN CN201710831363.3A patent/CN109509732B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1281231A (en) * | 2000-08-18 | 2001-01-24 | 中国科学院上海冶金研究所 | Substrate junction isolated integrated silicon inductor and its making method |
| US20050242416A1 (en) * | 2004-04-29 | 2005-11-03 | United Microelectronics Corp. | Low-capacitance bonding pad for semiconductor device |
| CN101656239B (en) * | 2009-07-22 | 2011-06-15 | 上海宏力半导体制造有限公司 | Bonding welding disk lowering parasitic capacitance and preparing method thereof |
| CN102024774A (en) * | 2009-09-16 | 2011-04-20 | 上海宏力半导体制造有限公司 | Contact pad |
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